0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2020 Compass Electronics Group, LLC
0004 */
0005
0006 / {
0007 aliases {
0008 rtc0 = &rtc;
0009 rtc1 = &snvs_rtc;
0010 spi0 = &flexspi;
0011 };
0012
0013 usdhc1_pwrseq: usdhc1_pwrseq {
0014 compatible = "mmc-pwrseq-simple";
0015 pinctrl-names = "default";
0016 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
0017 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
0018 clocks = <&osc_32k>;
0019 clock-names = "ext_clock";
0020 post-power-on-delay-ms = <80>;
0021 };
0022
0023 memory@40000000 {
0024 device_type = "memory";
0025 reg = <0x0 0x40000000 0 0x80000000>;
0026 };
0027 };
0028
0029 &A53_0 {
0030 cpu-supply = <&buck2_reg>;
0031 };
0032
0033 &A53_1 {
0034 cpu-supply = <&buck2_reg>;
0035 };
0036
0037 &A53_2 {
0038 cpu-supply = <&buck2_reg>;
0039 };
0040
0041 &A53_3 {
0042 cpu-supply = <&buck2_reg>;
0043 };
0044
0045 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
0046 &a53_opp_table {
0047 opp-1200000000 {
0048 opp-microvolt = <950000>;
0049 };
0050 };
0051
0052 &ddrc {
0053 operating-points-v2 = <&ddrc_opp_table>;
0054
0055 ddrc_opp_table: opp-table {
0056 compatible = "operating-points-v2";
0057
0058 opp-25M {
0059 opp-hz = /bits/ 64 <25000000>;
0060 };
0061
0062 opp-100M {
0063 opp-hz = /bits/ 64 <100000000>;
0064 };
0065
0066 opp-800M {
0067 opp-hz = /bits/ 64 <800000000>;
0068 };
0069 };
0070 };
0071
0072 &fec1 {
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_fec1>;
0075 phy-mode = "rgmii-id";
0076 phy-handle = <ðphy0>;
0077 phy-supply = <&buck6_reg>;
0078 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0079 fsl,magic-packet;
0080 status = "okay";
0081
0082 mdio {
0083 #address-cells = <1>;
0084 #size-cells = <0>;
0085
0086 ethphy0: ethernet-phy@0 {
0087 compatible = "ethernet-phy-ieee802.3-c22";
0088 reg = <0>;
0089 };
0090 };
0091 };
0092
0093 &flexspi {
0094 pinctrl-names = "default";
0095 pinctrl-0 = <&pinctrl_flexspi>;
0096 status = "okay";
0097
0098 flash@0 {
0099 reg = <0>;
0100 #address-cells = <1>;
0101 #size-cells = <1>;
0102 compatible = "jedec,spi-nor";
0103 spi-max-frequency = <80000000>;
0104 spi-tx-bus-width = <1>;
0105 spi-rx-bus-width = <4>;
0106 };
0107 };
0108
0109 &i2c1 {
0110 clock-frequency = <400000>;
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_i2c1>;
0113 status = "okay";
0114
0115 pmic@4b {
0116 compatible = "rohm,bd71847";
0117 reg = <0x4b>;
0118 pinctrl-names = "default";
0119 pinctrl-0 = <&pinctrl_pmic>;
0120 interrupt-parent = <&gpio1>;
0121 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0122 rohm,reset-snvs-powered;
0123 #clock-cells = <0>;
0124 clocks = <&osc_32k 0>;
0125 clock-output-names = "clk-32k-out";
0126
0127 regulators {
0128 buck1_reg: BUCK1 {
0129 regulator-name = "buck1";
0130 regulator-min-microvolt = <700000>;
0131 regulator-max-microvolt = <1300000>;
0132 regulator-boot-on;
0133 regulator-always-on;
0134 regulator-ramp-delay = <1250>;
0135 };
0136
0137 buck2_reg: BUCK2 {
0138 regulator-name = "buck2";
0139 regulator-min-microvolt = <700000>;
0140 regulator-max-microvolt = <1300000>;
0141 regulator-boot-on;
0142 regulator-always-on;
0143 regulator-ramp-delay = <1250>;
0144 rohm,dvs-run-voltage = <1000000>;
0145 rohm,dvs-idle-voltage = <900000>;
0146 };
0147
0148 buck3_reg: BUCK3 {
0149 // BUCK5 in datasheet
0150 regulator-name = "buck3";
0151 regulator-min-microvolt = <700000>;
0152 regulator-max-microvolt = <1350000>;
0153 regulator-boot-on;
0154 regulator-always-on;
0155 };
0156
0157 buck4_reg: BUCK4 {
0158 // BUCK6 in datasheet
0159 regulator-name = "buck4";
0160 regulator-min-microvolt = <3000000>;
0161 regulator-max-microvolt = <3300000>;
0162 regulator-boot-on;
0163 regulator-always-on;
0164 };
0165
0166 buck5_reg: BUCK5 {
0167 // BUCK7 in datasheet
0168 regulator-name = "buck5";
0169 regulator-min-microvolt = <1605000>;
0170 regulator-max-microvolt = <1995000>;
0171 regulator-boot-on;
0172 regulator-always-on;
0173 };
0174
0175 buck6_reg: BUCK6 {
0176 // BUCK8 in datasheet
0177 regulator-name = "buck6";
0178 regulator-min-microvolt = <800000>;
0179 regulator-max-microvolt = <1400000>;
0180 regulator-boot-on;
0181 regulator-always-on;
0182 };
0183
0184 ldo1_reg: LDO1 {
0185 regulator-name = "ldo1";
0186 regulator-min-microvolt = <1600000>;
0187 regulator-max-microvolt = <3300000>;
0188 regulator-boot-on;
0189 regulator-always-on;
0190 };
0191
0192 ldo2_reg: LDO2 {
0193 regulator-name = "ldo2";
0194 regulator-min-microvolt = <800000>;
0195 regulator-max-microvolt = <900000>;
0196 regulator-boot-on;
0197 regulator-always-on;
0198 };
0199
0200 ldo3_reg: LDO3 {
0201 regulator-name = "ldo3";
0202 regulator-min-microvolt = <1800000>;
0203 regulator-max-microvolt = <3300000>;
0204 regulator-boot-on;
0205 regulator-always-on;
0206 };
0207
0208 ldo4_reg: LDO4 {
0209 regulator-name = "ldo4";
0210 regulator-min-microvolt = <900000>;
0211 regulator-max-microvolt = <1800000>;
0212 regulator-boot-on;
0213 regulator-always-on;
0214 };
0215
0216 ldo6_reg: LDO6 {
0217 regulator-name = "ldo6";
0218 regulator-min-microvolt = <900000>;
0219 regulator-max-microvolt = <1800000>;
0220 regulator-boot-on;
0221 regulator-always-on;
0222 };
0223 };
0224 };
0225 };
0226
0227 &i2c3 {
0228 clock-frequency = <400000>;
0229 pinctrl-names = "default";
0230 pinctrl-0 = <&pinctrl_i2c3>;
0231 status = "okay";
0232
0233 eeprom@50 {
0234 compatible = "microchip,24c64", "atmel,24c64";
0235 pagesize = <32>;
0236 read-only; /* Manufacturing EEPROM programmed at factory */
0237 reg = <0x50>;
0238 };
0239
0240 rtc: rtc@51 {
0241 compatible = "nxp,pcf85263";
0242 reg = <0x51>;
0243 };
0244 };
0245
0246 &uart1 {
0247 pinctrl-names = "default";
0248 pinctrl-0 = <&pinctrl_uart1>;
0249 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
0250 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
0251 uart-has-rtscts;
0252 status = "okay";
0253
0254 bluetooth {
0255 compatible = "brcm,bcm43438-bt";
0256 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
0257 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
0258 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
0259 clocks = <&osc_32k>;
0260 max-speed = <4000000>;
0261 clock-names = "extclk";
0262 };
0263 };
0264
0265 &usdhc1 {
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0269 pinctrl-0 = <&pinctrl_usdhc1>;
0270 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0271 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0272 vmmc-supply = <&buck4_reg>;
0273 vqmmc-supply = <&buck5_reg>;
0274 bus-width = <4>;
0275 non-removable;
0276 cap-power-off-card;
0277 keep-power-in-suspend;
0278 mmc-pwrseq = <&usdhc1_pwrseq>;
0279 status = "okay";
0280
0281 brcmf: bcrmf@1 {
0282 reg = <1>;
0283 compatible = "brcm,bcm4329-fmac";
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_wlan>;
0286 interrupt-parent = <&gpio2>;
0287 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0288 interrupt-names = "host-wake";
0289 };
0290 };
0291
0292 &usdhc3 {
0293 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0294 pinctrl-0 = <&pinctrl_usdhc3>;
0295 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0296 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0297 bus-width = <8>;
0298 non-removable;
0299 status = "okay";
0300 };
0301
0302 &wdog1 {
0303 pinctrl-names = "default";
0304 pinctrl-0 = <&pinctrl_wdog>;
0305 fsl,ext-reset-output;
0306 status = "okay";
0307 };
0308
0309 &iomuxc {
0310 pinctrl_fec1: fec1grp {
0311 fsl,pins = <
0312 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0313 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0314 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0315 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0316 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0317 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0318 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0319 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0320 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0321 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0322 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0323 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0324 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0325 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0326 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
0327 >;
0328 };
0329
0330 pinctrl_i2c1: i2c1grp {
0331 fsl,pins = <
0332 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0333 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0334 >;
0335 };
0336
0337 pinctrl_i2c3: i2c3grp {
0338 fsl,pins = <
0339 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0340 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0341 >;
0342 };
0343
0344 pinctrl_flexspi: flexspigrp {
0345 fsl,pins = <
0346 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0347 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0348 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0349 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0350 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0351 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0352 >;
0353 };
0354
0355 pinctrl_pmic: pmicirqgrp {
0356 fsl,pins = <
0357 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
0358 >;
0359 };
0360
0361 pinctrl_uart1: uart1grp {
0362 fsl,pins = <
0363 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0364 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0365 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
0366 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
0367 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
0368 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
0369 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
0370 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
0371 >;
0372 };
0373
0374 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
0375 fsl,pins = <
0376 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
0377 >;
0378 };
0379
0380 pinctrl_usdhc1: usdhc1grp {
0381 fsl,pins = <
0382 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0383 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0384 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0385 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0386 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0387 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0388 >;
0389 };
0390
0391 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0392 fsl,pins = <
0393 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0394 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0395 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0396 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0397 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0398 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0399 >;
0400 };
0401
0402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0403 fsl,pins = <
0404 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0405 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0406 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0407 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0408 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0409 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0410 >;
0411 };
0412
0413 pinctrl_usdhc3: usdhc3grp {
0414 fsl,pins = <
0415 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0416 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0417 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0418 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0419 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0420 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0421 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0422 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0423 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0424 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0425 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0426 >;
0427 };
0428
0429 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0430 fsl,pins = <
0431 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0432 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0433 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0434 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0435 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0436 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0437 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0438 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0439 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0440 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0441 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0442 >;
0443 };
0444
0445 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0446 fsl,pins = <
0447 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0448 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0449 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0450 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0451 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0452 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0453 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0454 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0455 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0456 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0457 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0458 >;
0459 };
0460
0461 pinctrl_wdog: wdoggrp {
0462 fsl,pins = <
0463 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0464 >;
0465 };
0466
0467 pinctrl_wlan: wlangrp {
0468 fsl,pins = <
0469 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
0470 >;
0471 };
0472 };
