0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 */
0005
0006 #include <dt-bindings/clock/imx8mm-clock.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/power/imx8mm-power.h>
0011 #include <dt-bindings/reset/imx8mq-reset.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013
0014 #include "imx8mm-pinfunc.h"
0015
0016 / {
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 ethernet0 = &fec1;
0023 gpio0 = &gpio1;
0024 gpio1 = &gpio2;
0025 gpio2 = &gpio3;
0026 gpio3 = &gpio4;
0027 gpio4 = &gpio5;
0028 i2c0 = &i2c1;
0029 i2c1 = &i2c2;
0030 i2c2 = &i2c3;
0031 i2c3 = &i2c4;
0032 mmc0 = &usdhc1;
0033 mmc1 = &usdhc2;
0034 mmc2 = &usdhc3;
0035 serial0 = &uart1;
0036 serial1 = &uart2;
0037 serial2 = &uart3;
0038 serial3 = &uart4;
0039 spi0 = &ecspi1;
0040 spi1 = &ecspi2;
0041 spi2 = &ecspi3;
0042 };
0043
0044 cpus {
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047
0048 idle-states {
0049 entry-method = "psci";
0050
0051 cpu_pd_wait: cpu-pd-wait {
0052 compatible = "arm,idle-state";
0053 arm,psci-suspend-param = <0x0010033>;
0054 local-timer-stop;
0055 entry-latency-us = <1000>;
0056 exit-latency-us = <700>;
0057 min-residency-us = <2700>;
0058 };
0059 };
0060
0061 A53_0: cpu@0 {
0062 device_type = "cpu";
0063 compatible = "arm,cortex-a53";
0064 reg = <0x0>;
0065 clock-latency = <61036>; /* two CLK32 periods */
0066 clocks = <&clk IMX8MM_CLK_ARM>;
0067 enable-method = "psci";
0068 i-cache-size = <0x8000>;
0069 i-cache-line-size = <64>;
0070 i-cache-sets = <256>;
0071 d-cache-size = <0x8000>;
0072 d-cache-line-size = <64>;
0073 d-cache-sets = <128>;
0074 next-level-cache = <&A53_L2>;
0075 operating-points-v2 = <&a53_opp_table>;
0076 nvmem-cells = <&cpu_speed_grade>;
0077 nvmem-cell-names = "speed_grade";
0078 cpu-idle-states = <&cpu_pd_wait>;
0079 #cooling-cells = <2>;
0080 };
0081
0082 A53_1: cpu@1 {
0083 device_type = "cpu";
0084 compatible = "arm,cortex-a53";
0085 reg = <0x1>;
0086 clock-latency = <61036>; /* two CLK32 periods */
0087 clocks = <&clk IMX8MM_CLK_ARM>;
0088 enable-method = "psci";
0089 i-cache-size = <0x8000>;
0090 i-cache-line-size = <64>;
0091 i-cache-sets = <256>;
0092 d-cache-size = <0x8000>;
0093 d-cache-line-size = <64>;
0094 d-cache-sets = <128>;
0095 next-level-cache = <&A53_L2>;
0096 operating-points-v2 = <&a53_opp_table>;
0097 cpu-idle-states = <&cpu_pd_wait>;
0098 #cooling-cells = <2>;
0099 };
0100
0101 A53_2: cpu@2 {
0102 device_type = "cpu";
0103 compatible = "arm,cortex-a53";
0104 reg = <0x2>;
0105 clock-latency = <61036>; /* two CLK32 periods */
0106 clocks = <&clk IMX8MM_CLK_ARM>;
0107 enable-method = "psci";
0108 i-cache-size = <0x8000>;
0109 i-cache-line-size = <64>;
0110 i-cache-sets = <256>;
0111 d-cache-size = <0x8000>;
0112 d-cache-line-size = <64>;
0113 d-cache-sets = <128>;
0114 next-level-cache = <&A53_L2>;
0115 operating-points-v2 = <&a53_opp_table>;
0116 cpu-idle-states = <&cpu_pd_wait>;
0117 #cooling-cells = <2>;
0118 };
0119
0120 A53_3: cpu@3 {
0121 device_type = "cpu";
0122 compatible = "arm,cortex-a53";
0123 reg = <0x3>;
0124 clock-latency = <61036>; /* two CLK32 periods */
0125 clocks = <&clk IMX8MM_CLK_ARM>;
0126 enable-method = "psci";
0127 i-cache-size = <0x8000>;
0128 i-cache-line-size = <64>;
0129 i-cache-sets = <256>;
0130 d-cache-size = <0x8000>;
0131 d-cache-line-size = <64>;
0132 d-cache-sets = <128>;
0133 next-level-cache = <&A53_L2>;
0134 operating-points-v2 = <&a53_opp_table>;
0135 cpu-idle-states = <&cpu_pd_wait>;
0136 #cooling-cells = <2>;
0137 };
0138
0139 A53_L2: l2-cache0 {
0140 compatible = "cache";
0141 cache-level = <2>;
0142 cache-size = <0x80000>;
0143 cache-line-size = <64>;
0144 cache-sets = <512>;
0145 };
0146 };
0147
0148 a53_opp_table: opp-table {
0149 compatible = "operating-points-v2";
0150 opp-shared;
0151
0152 opp-1200000000 {
0153 opp-hz = /bits/ 64 <1200000000>;
0154 opp-microvolt = <850000>;
0155 opp-supported-hw = <0xe>, <0x7>;
0156 clock-latency-ns = <150000>;
0157 opp-suspend;
0158 };
0159
0160 opp-1600000000 {
0161 opp-hz = /bits/ 64 <1600000000>;
0162 opp-microvolt = <950000>;
0163 opp-supported-hw = <0xc>, <0x7>;
0164 clock-latency-ns = <150000>;
0165 opp-suspend;
0166 };
0167
0168 opp-1800000000 {
0169 opp-hz = /bits/ 64 <1800000000>;
0170 opp-microvolt = <1000000>;
0171 opp-supported-hw = <0x8>, <0x3>;
0172 clock-latency-ns = <150000>;
0173 opp-suspend;
0174 };
0175 };
0176
0177 osc_32k: clock-osc-32k {
0178 compatible = "fixed-clock";
0179 #clock-cells = <0>;
0180 clock-frequency = <32768>;
0181 clock-output-names = "osc_32k";
0182 };
0183
0184 osc_24m: clock-osc-24m {
0185 compatible = "fixed-clock";
0186 #clock-cells = <0>;
0187 clock-frequency = <24000000>;
0188 clock-output-names = "osc_24m";
0189 };
0190
0191 clk_ext1: clock-ext1 {
0192 compatible = "fixed-clock";
0193 #clock-cells = <0>;
0194 clock-frequency = <133000000>;
0195 clock-output-names = "clk_ext1";
0196 };
0197
0198 clk_ext2: clock-ext2 {
0199 compatible = "fixed-clock";
0200 #clock-cells = <0>;
0201 clock-frequency = <133000000>;
0202 clock-output-names = "clk_ext2";
0203 };
0204
0205 clk_ext3: clock-ext3 {
0206 compatible = "fixed-clock";
0207 #clock-cells = <0>;
0208 clock-frequency = <133000000>;
0209 clock-output-names = "clk_ext3";
0210 };
0211
0212 clk_ext4: clock-ext4 {
0213 compatible = "fixed-clock";
0214 #clock-cells = <0>;
0215 clock-frequency = <133000000>;
0216 clock-output-names = "clk_ext4";
0217 };
0218
0219 psci {
0220 compatible = "arm,psci-1.0";
0221 method = "smc";
0222 };
0223
0224 pmu {
0225 compatible = "arm,cortex-a53-pmu";
0226 interrupts = <GIC_PPI 7
0227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0228 };
0229
0230 timer {
0231 compatible = "arm,armv8-timer";
0232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
0233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
0234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
0235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
0236 clock-frequency = <8000000>;
0237 arm,no-tick-in-suspend;
0238 };
0239
0240 thermal-zones {
0241 cpu-thermal {
0242 polling-delay-passive = <250>;
0243 polling-delay = <2000>;
0244 thermal-sensors = <&tmu>;
0245 trips {
0246 cpu_alert0: trip0 {
0247 temperature = <85000>;
0248 hysteresis = <2000>;
0249 type = "passive";
0250 };
0251
0252 cpu_crit0: trip1 {
0253 temperature = <95000>;
0254 hysteresis = <2000>;
0255 type = "critical";
0256 };
0257 };
0258
0259 cooling-maps {
0260 map0 {
0261 trip = <&cpu_alert0>;
0262 cooling-device =
0263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0267 };
0268 };
0269 };
0270 };
0271
0272 usbphynop1: usbphynop1 {
0273 #phy-cells = <0>;
0274 compatible = "usb-nop-xceiv";
0275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
0276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
0277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
0278 clock-names = "main_clk";
0279 };
0280
0281 usbphynop2: usbphynop2 {
0282 #phy-cells = <0>;
0283 compatible = "usb-nop-xceiv";
0284 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
0285 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
0286 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
0287 clock-names = "main_clk";
0288 };
0289
0290 soc: soc@0 {
0291 compatible = "fsl,imx8mm-soc", "simple-bus";
0292 #address-cells = <1>;
0293 #size-cells = <1>;
0294 ranges = <0x0 0x0 0x0 0x3e000000>;
0295 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
0296 nvmem-cells = <&imx8mm_uid>;
0297 nvmem-cell-names = "soc_unique_id";
0298
0299 aips1: bus@30000000 {
0300 compatible = "fsl,aips-bus", "simple-bus";
0301 reg = <0x30000000 0x400000>;
0302 #address-cells = <1>;
0303 #size-cells = <1>;
0304 ranges = <0x30000000 0x30000000 0x400000>;
0305
0306 spba2: spba-bus@30000000 {
0307 compatible = "fsl,spba-bus", "simple-bus";
0308 #address-cells = <1>;
0309 #size-cells = <1>;
0310 reg = <0x30000000 0x100000>;
0311 ranges;
0312
0313 sai1: sai@30010000 {
0314 #sound-dai-cells = <0>;
0315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
0316 reg = <0x30010000 0x10000>;
0317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0318 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
0319 <&clk IMX8MM_CLK_SAI1_ROOT>,
0320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
0321 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0322 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
0323 dma-names = "rx", "tx";
0324 status = "disabled";
0325 };
0326
0327 sai2: sai@30020000 {
0328 #sound-dai-cells = <0>;
0329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
0330 reg = <0x30020000 0x10000>;
0331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0332 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
0333 <&clk IMX8MM_CLK_SAI2_ROOT>,
0334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
0335 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0336 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
0337 dma-names = "rx", "tx";
0338 status = "disabled";
0339 };
0340
0341 sai3: sai@30030000 {
0342 #sound-dai-cells = <0>;
0343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
0344 reg = <0x30030000 0x10000>;
0345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0346 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
0347 <&clk IMX8MM_CLK_SAI3_ROOT>,
0348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
0349 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0350 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
0351 dma-names = "rx", "tx";
0352 status = "disabled";
0353 };
0354
0355 sai5: sai@30050000 {
0356 #sound-dai-cells = <0>;
0357 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
0358 reg = <0x30050000 0x10000>;
0359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0360 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
0361 <&clk IMX8MM_CLK_SAI5_ROOT>,
0362 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
0363 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0364 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
0365 dma-names = "rx", "tx";
0366 status = "disabled";
0367 };
0368
0369 sai6: sai@30060000 {
0370 #sound-dai-cells = <0>;
0371 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
0372 reg = <0x30060000 0x10000>;
0373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0374 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
0375 <&clk IMX8MM_CLK_SAI6_ROOT>,
0376 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
0377 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0378 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
0379 dma-names = "rx", "tx";
0380 status = "disabled";
0381 };
0382
0383 micfil: audio-controller@30080000 {
0384 compatible = "fsl,imx8mm-micfil";
0385 reg = <0x30080000 0x10000>;
0386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0388 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0389 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0390 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
0391 <&clk IMX8MM_CLK_PDM_ROOT>,
0392 <&clk IMX8MM_AUDIO_PLL1_OUT>,
0393 <&clk IMX8MM_AUDIO_PLL2_OUT>,
0394 <&clk IMX8MM_CLK_EXT3>;
0395 clock-names = "ipg_clk", "ipg_clk_app",
0396 "pll8k", "pll11k", "clkext3";
0397 dmas = <&sdma2 24 25 0x80000000>;
0398 dma-names = "rx";
0399 status = "disabled";
0400 };
0401
0402 spdif1: spdif@30090000 {
0403 compatible = "fsl,imx35-spdif";
0404 reg = <0x30090000 0x10000>;
0405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
0407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
0408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
0409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
0410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
0411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
0412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
0413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
0414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
0415 <&clk IMX8MM_CLK_DUMMY>; /* spba */
0416 clock-names = "core", "rxtx0",
0417 "rxtx1", "rxtx2",
0418 "rxtx3", "rxtx4",
0419 "rxtx5", "rxtx6",
0420 "rxtx7", "spba";
0421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
0422 dma-names = "rx", "tx";
0423 status = "disabled";
0424 };
0425 };
0426
0427 gpio1: gpio@30200000 {
0428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
0429 reg = <0x30200000 0x10000>;
0430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
0433 gpio-controller;
0434 #gpio-cells = <2>;
0435 interrupt-controller;
0436 #interrupt-cells = <2>;
0437 gpio-ranges = <&iomuxc 0 10 30>;
0438 };
0439
0440 gpio2: gpio@30210000 {
0441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
0442 reg = <0x30210000 0x10000>;
0443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
0446 gpio-controller;
0447 #gpio-cells = <2>;
0448 interrupt-controller;
0449 #interrupt-cells = <2>;
0450 gpio-ranges = <&iomuxc 0 40 21>;
0451 };
0452
0453 gpio3: gpio@30220000 {
0454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
0455 reg = <0x30220000 0x10000>;
0456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
0459 gpio-controller;
0460 #gpio-cells = <2>;
0461 interrupt-controller;
0462 #interrupt-cells = <2>;
0463 gpio-ranges = <&iomuxc 0 61 26>;
0464 };
0465
0466 gpio4: gpio@30230000 {
0467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
0468 reg = <0x30230000 0x10000>;
0469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
0472 gpio-controller;
0473 #gpio-cells = <2>;
0474 interrupt-controller;
0475 #interrupt-cells = <2>;
0476 gpio-ranges = <&iomuxc 0 87 32>;
0477 };
0478
0479 gpio5: gpio@30240000 {
0480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
0481 reg = <0x30240000 0x10000>;
0482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
0485 gpio-controller;
0486 #gpio-cells = <2>;
0487 interrupt-controller;
0488 #interrupt-cells = <2>;
0489 gpio-ranges = <&iomuxc 0 119 30>;
0490 };
0491
0492 tmu: tmu@30260000 {
0493 compatible = "fsl,imx8mm-tmu";
0494 reg = <0x30260000 0x10000>;
0495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
0496 #thermal-sensor-cells = <0>;
0497 };
0498
0499 wdog1: watchdog@30280000 {
0500 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
0501 reg = <0x30280000 0x10000>;
0502 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
0504 status = "disabled";
0505 };
0506
0507 wdog2: watchdog@30290000 {
0508 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
0509 reg = <0x30290000 0x10000>;
0510 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0511 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
0512 status = "disabled";
0513 };
0514
0515 wdog3: watchdog@302a0000 {
0516 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
0517 reg = <0x302a0000 0x10000>;
0518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0519 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
0520 status = "disabled";
0521 };
0522
0523 sdma2: dma-controller@302c0000 {
0524 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
0525 reg = <0x302c0000 0x10000>;
0526 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0527 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
0528 <&clk IMX8MM_CLK_SDMA2_ROOT>;
0529 clock-names = "ipg", "ahb";
0530 #dma-cells = <3>;
0531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0532 };
0533
0534 sdma3: dma-controller@302b0000 {
0535 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
0536 reg = <0x302b0000 0x10000>;
0537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0538 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
0539 <&clk IMX8MM_CLK_SDMA3_ROOT>;
0540 clock-names = "ipg", "ahb";
0541 #dma-cells = <3>;
0542 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0543 };
0544
0545 iomuxc: pinctrl@30330000 {
0546 compatible = "fsl,imx8mm-iomuxc";
0547 reg = <0x30330000 0x10000>;
0548 };
0549
0550 gpr: iomuxc-gpr@30340000 {
0551 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
0552 reg = <0x30340000 0x10000>;
0553 };
0554
0555 ocotp: efuse@30350000 {
0556 compatible = "fsl,imx8mm-ocotp", "syscon";
0557 reg = <0x30350000 0x10000>;
0558 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
0559 /* For nvmem subnodes */
0560 #address-cells = <1>;
0561 #size-cells = <1>;
0562
0563 imx8mm_uid: unique-id@410 {
0564 reg = <0x4 0x8>;
0565 };
0566
0567 cpu_speed_grade: speed-grade@10 {
0568 reg = <0x10 4>;
0569 };
0570
0571 fec_mac_address: mac-address@90 {
0572 reg = <0x90 6>;
0573 };
0574 };
0575
0576 anatop: anatop@30360000 {
0577 compatible = "fsl,imx8mm-anatop", "syscon";
0578 reg = <0x30360000 0x10000>;
0579 };
0580
0581 snvs: snvs@30370000 {
0582 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
0583 reg = <0x30370000 0x10000>;
0584
0585 snvs_rtc: snvs-rtc-lp {
0586 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0587 regmap = <&snvs>;
0588 offset = <0x34>;
0589 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0590 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0591 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
0592 clock-names = "snvs-rtc";
0593 };
0594
0595 snvs_pwrkey: snvs-powerkey {
0596 compatible = "fsl,sec-v4.0-pwrkey";
0597 regmap = <&snvs>;
0598 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0599 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
0600 clock-names = "snvs-pwrkey";
0601 linux,keycode = <KEY_POWER>;
0602 wakeup-source;
0603 status = "disabled";
0604 };
0605
0606 snvs_lpgpr: snvs-lpgpr {
0607 compatible = "fsl,imx8mm-snvs-lpgpr",
0608 "fsl,imx7d-snvs-lpgpr";
0609 };
0610 };
0611
0612 clk: clock-controller@30380000 {
0613 compatible = "fsl,imx8mm-ccm";
0614 reg = <0x30380000 0x10000>;
0615 #clock-cells = <1>;
0616 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
0617 <&clk_ext3>, <&clk_ext4>;
0618 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
0619 "clk_ext3", "clk_ext4";
0620 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
0621 <&clk IMX8MM_CLK_A53_CORE>,
0622 <&clk IMX8MM_CLK_NOC>,
0623 <&clk IMX8MM_CLK_AUDIO_AHB>,
0624 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
0625 <&clk IMX8MM_SYS_PLL3>,
0626 <&clk IMX8MM_VIDEO_PLL1>,
0627 <&clk IMX8MM_AUDIO_PLL1>;
0628 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
0629 <&clk IMX8MM_ARM_PLL_OUT>,
0630 <&clk IMX8MM_SYS_PLL3_OUT>,
0631 <&clk IMX8MM_SYS_PLL1_800M>;
0632 assigned-clock-rates = <0>, <0>, <0>,
0633 <400000000>,
0634 <400000000>,
0635 <750000000>,
0636 <594000000>,
0637 <393216000>;
0638 };
0639
0640 src: reset-controller@30390000 {
0641 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
0642 reg = <0x30390000 0x10000>;
0643 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0644 #reset-cells = <1>;
0645 };
0646
0647 gpc: gpc@303a0000 {
0648 compatible = "fsl,imx8mm-gpc";
0649 reg = <0x303a0000 0x10000>;
0650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0651 interrupt-parent = <&gic>;
0652 interrupt-controller;
0653 #interrupt-cells = <3>;
0654
0655 pgc {
0656 #address-cells = <1>;
0657 #size-cells = <0>;
0658
0659 pgc_hsiomix: power-domain@0 {
0660 #power-domain-cells = <0>;
0661 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
0662 clocks = <&clk IMX8MM_CLK_USB_BUS>;
0663 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
0664 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
0665 };
0666
0667 pgc_pcie: power-domain@1 {
0668 #power-domain-cells = <0>;
0669 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
0670 power-domains = <&pgc_hsiomix>;
0671 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
0672 };
0673
0674 pgc_otg1: power-domain@2 {
0675 #power-domain-cells = <0>;
0676 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
0677 power-domains = <&pgc_hsiomix>;
0678 };
0679
0680 pgc_otg2: power-domain@3 {
0681 #power-domain-cells = <0>;
0682 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
0683 power-domains = <&pgc_hsiomix>;
0684 };
0685
0686 pgc_gpumix: power-domain@4 {
0687 #power-domain-cells = <0>;
0688 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
0689 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
0690 <&clk IMX8MM_CLK_GPU_AHB>;
0691 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
0692 <&clk IMX8MM_CLK_GPU_AHB>;
0693 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
0694 <&clk IMX8MM_SYS_PLL1_800M>;
0695 assigned-clock-rates = <800000000>, <400000000>;
0696 };
0697
0698 pgc_gpu: power-domain@5 {
0699 #power-domain-cells = <0>;
0700 reg = <IMX8MM_POWER_DOMAIN_GPU>;
0701 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
0702 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
0703 <&clk IMX8MM_CLK_GPU2D_ROOT>,
0704 <&clk IMX8MM_CLK_GPU3D_ROOT>;
0705 resets = <&src IMX8MQ_RESET_GPU_RESET>;
0706 power-domains = <&pgc_gpumix>;
0707 };
0708
0709 pgc_vpumix: power-domain@6 {
0710 #power-domain-cells = <0>;
0711 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
0712 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
0713 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
0714 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
0715 };
0716
0717 pgc_vpu_g1: power-domain@7 {
0718 #power-domain-cells = <0>;
0719 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
0720 };
0721
0722 pgc_vpu_g2: power-domain@8 {
0723 #power-domain-cells = <0>;
0724 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
0725 };
0726
0727 pgc_vpu_h1: power-domain@9 {
0728 #power-domain-cells = <0>;
0729 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
0730 };
0731
0732 pgc_dispmix: power-domain@10 {
0733 #power-domain-cells = <0>;
0734 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
0735 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
0736 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
0737 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
0738 <&clk IMX8MM_CLK_DISP_APB>;
0739 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
0740 <&clk IMX8MM_SYS_PLL1_800M>;
0741 assigned-clock-rates = <500000000>, <200000000>;
0742 };
0743
0744 pgc_mipi: power-domain@11 {
0745 #power-domain-cells = <0>;
0746 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
0747 };
0748 };
0749 };
0750 };
0751
0752 aips2: bus@30400000 {
0753 compatible = "fsl,aips-bus", "simple-bus";
0754 reg = <0x30400000 0x400000>;
0755 #address-cells = <1>;
0756 #size-cells = <1>;
0757 ranges = <0x30400000 0x30400000 0x400000>;
0758
0759 pwm1: pwm@30660000 {
0760 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
0761 reg = <0x30660000 0x10000>;
0762 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0763 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
0764 <&clk IMX8MM_CLK_PWM1_ROOT>;
0765 clock-names = "ipg", "per";
0766 #pwm-cells = <3>;
0767 status = "disabled";
0768 };
0769
0770 pwm2: pwm@30670000 {
0771 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
0772 reg = <0x30670000 0x10000>;
0773 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0774 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
0775 <&clk IMX8MM_CLK_PWM2_ROOT>;
0776 clock-names = "ipg", "per";
0777 #pwm-cells = <3>;
0778 status = "disabled";
0779 };
0780
0781 pwm3: pwm@30680000 {
0782 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
0783 reg = <0x30680000 0x10000>;
0784 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0785 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
0786 <&clk IMX8MM_CLK_PWM3_ROOT>;
0787 clock-names = "ipg", "per";
0788 #pwm-cells = <3>;
0789 status = "disabled";
0790 };
0791
0792 pwm4: pwm@30690000 {
0793 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
0794 reg = <0x30690000 0x10000>;
0795 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0796 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
0797 <&clk IMX8MM_CLK_PWM4_ROOT>;
0798 clock-names = "ipg", "per";
0799 #pwm-cells = <3>;
0800 status = "disabled";
0801 };
0802
0803 system_counter: timer@306a0000 {
0804 compatible = "nxp,sysctr-timer";
0805 reg = <0x306a0000 0x20000>;
0806 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0807 clocks = <&osc_24m>;
0808 clock-names = "per";
0809 };
0810 };
0811
0812 aips3: bus@30800000 {
0813 compatible = "fsl,aips-bus", "simple-bus";
0814 reg = <0x30800000 0x400000>;
0815 #address-cells = <1>;
0816 #size-cells = <1>;
0817 ranges = <0x30800000 0x30800000 0x400000>,
0818 <0x8000000 0x8000000 0x10000000>;
0819
0820 spba1: spba-bus@30800000 {
0821 compatible = "fsl,spba-bus", "simple-bus";
0822 #address-cells = <1>;
0823 #size-cells = <1>;
0824 reg = <0x30800000 0x100000>;
0825 ranges;
0826
0827 ecspi1: spi@30820000 {
0828 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
0829 #address-cells = <1>;
0830 #size-cells = <0>;
0831 reg = <0x30820000 0x10000>;
0832 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0833 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
0834 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
0835 clock-names = "ipg", "per";
0836 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
0837 dma-names = "rx", "tx";
0838 status = "disabled";
0839 };
0840
0841 ecspi2: spi@30830000 {
0842 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
0843 #address-cells = <1>;
0844 #size-cells = <0>;
0845 reg = <0x30830000 0x10000>;
0846 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0847 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
0848 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
0849 clock-names = "ipg", "per";
0850 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
0851 dma-names = "rx", "tx";
0852 status = "disabled";
0853 };
0854
0855 ecspi3: spi@30840000 {
0856 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
0857 #address-cells = <1>;
0858 #size-cells = <0>;
0859 reg = <0x30840000 0x10000>;
0860 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0861 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
0862 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
0863 clock-names = "ipg", "per";
0864 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
0865 dma-names = "rx", "tx";
0866 status = "disabled";
0867 };
0868
0869 uart1: serial@30860000 {
0870 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
0871 reg = <0x30860000 0x10000>;
0872 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0873 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
0874 <&clk IMX8MM_CLK_UART1_ROOT>;
0875 clock-names = "ipg", "per";
0876 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
0877 dma-names = "rx", "tx";
0878 status = "disabled";
0879 };
0880
0881 uart3: serial@30880000 {
0882 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
0883 reg = <0x30880000 0x10000>;
0884 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0885 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
0886 <&clk IMX8MM_CLK_UART3_ROOT>;
0887 clock-names = "ipg", "per";
0888 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
0889 dma-names = "rx", "tx";
0890 status = "disabled";
0891 };
0892
0893 uart2: serial@30890000 {
0894 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
0895 reg = <0x30890000 0x10000>;
0896 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0897 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
0898 <&clk IMX8MM_CLK_UART2_ROOT>;
0899 clock-names = "ipg", "per";
0900 status = "disabled";
0901 };
0902 };
0903
0904 crypto: crypto@30900000 {
0905 compatible = "fsl,sec-v4.0";
0906 #address-cells = <1>;
0907 #size-cells = <1>;
0908 reg = <0x30900000 0x40000>;
0909 ranges = <0 0x30900000 0x40000>;
0910 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0911 clocks = <&clk IMX8MM_CLK_AHB>,
0912 <&clk IMX8MM_CLK_IPG_ROOT>;
0913 clock-names = "aclk", "ipg";
0914
0915 sec_jr0: jr@1000 {
0916 compatible = "fsl,sec-v4.0-job-ring";
0917 reg = <0x1000 0x1000>;
0918 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0919 status = "disabled";
0920 };
0921
0922 sec_jr1: jr@2000 {
0923 compatible = "fsl,sec-v4.0-job-ring";
0924 reg = <0x2000 0x1000>;
0925 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0926 };
0927
0928 sec_jr2: jr@3000 {
0929 compatible = "fsl,sec-v4.0-job-ring";
0930 reg = <0x3000 0x1000>;
0931 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0932 };
0933 };
0934
0935 i2c1: i2c@30a20000 {
0936 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
0937 #address-cells = <1>;
0938 #size-cells = <0>;
0939 reg = <0x30a20000 0x10000>;
0940 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0941 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
0942 status = "disabled";
0943 };
0944
0945 i2c2: i2c@30a30000 {
0946 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
0947 #address-cells = <1>;
0948 #size-cells = <0>;
0949 reg = <0x30a30000 0x10000>;
0950 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0951 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
0952 status = "disabled";
0953 };
0954
0955 i2c3: i2c@30a40000 {
0956 #address-cells = <1>;
0957 #size-cells = <0>;
0958 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
0959 reg = <0x30a40000 0x10000>;
0960 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0961 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
0962 status = "disabled";
0963 };
0964
0965 i2c4: i2c@30a50000 {
0966 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
0967 #address-cells = <1>;
0968 #size-cells = <0>;
0969 reg = <0x30a50000 0x10000>;
0970 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0971 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
0972 status = "disabled";
0973 };
0974
0975 uart4: serial@30a60000 {
0976 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
0977 reg = <0x30a60000 0x10000>;
0978 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0979 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
0980 <&clk IMX8MM_CLK_UART4_ROOT>;
0981 clock-names = "ipg", "per";
0982 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
0983 dma-names = "rx", "tx";
0984 status = "disabled";
0985 };
0986
0987 mu: mailbox@30aa0000 {
0988 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
0989 reg = <0x30aa0000 0x10000>;
0990 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0991 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
0992 #mbox-cells = <2>;
0993 };
0994
0995 usdhc1: mmc@30b40000 {
0996 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0997 reg = <0x30b40000 0x10000>;
0998 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0999 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1000 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1001 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1002 clock-names = "ipg", "ahb", "per";
1003 fsl,tuning-start-tap = <20>;
1004 fsl,tuning-step = <2>;
1005 bus-width = <4>;
1006 status = "disabled";
1007 };
1008
1009 usdhc2: mmc@30b50000 {
1010 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1011 reg = <0x30b50000 0x10000>;
1012 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1014 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1015 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1016 clock-names = "ipg", "ahb", "per";
1017 fsl,tuning-start-tap = <20>;
1018 fsl,tuning-step = <2>;
1019 bus-width = <4>;
1020 status = "disabled";
1021 };
1022
1023 usdhc3: mmc@30b60000 {
1024 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1025 reg = <0x30b60000 0x10000>;
1026 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1028 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1029 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1030 clock-names = "ipg", "ahb", "per";
1031 fsl,tuning-start-tap = <20>;
1032 fsl,tuning-step = <2>;
1033 bus-width = <4>;
1034 status = "disabled";
1035 };
1036
1037 flexspi: spi@30bb0000 {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "nxp,imx8mm-fspi";
1041 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1042 reg-names = "fspi_base", "fspi_mmap";
1043 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1045 <&clk IMX8MM_CLK_QSPI_ROOT>;
1046 clock-names = "fspi_en", "fspi";
1047 status = "disabled";
1048 };
1049
1050 sdma1: dma-controller@30bd0000 {
1051 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1052 reg = <0x30bd0000 0x10000>;
1053 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1055 <&clk IMX8MM_CLK_AHB>;
1056 clock-names = "ipg", "ahb";
1057 #dma-cells = <3>;
1058 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1059 };
1060
1061 fec1: ethernet@30be0000 {
1062 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1063 reg = <0x30be0000 0x10000>;
1064 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1069 <&clk IMX8MM_CLK_ENET1_ROOT>,
1070 <&clk IMX8MM_CLK_ENET_TIMER>,
1071 <&clk IMX8MM_CLK_ENET_REF>,
1072 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1073 clock-names = "ipg", "ahb", "ptp",
1074 "enet_clk_ref", "enet_out";
1075 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1076 <&clk IMX8MM_CLK_ENET_TIMER>,
1077 <&clk IMX8MM_CLK_ENET_REF>,
1078 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1079 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1080 <&clk IMX8MM_SYS_PLL2_100M>,
1081 <&clk IMX8MM_SYS_PLL2_125M>,
1082 <&clk IMX8MM_SYS_PLL2_50M>;
1083 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1084 fsl,num-tx-queues = <3>;
1085 fsl,num-rx-queues = <3>;
1086 nvmem-cells = <&fec_mac_address>;
1087 nvmem-cell-names = "mac-address";
1088 fsl,stop-mode = <&gpr 0x10 3>;
1089 status = "disabled";
1090 };
1091
1092 };
1093
1094 aips4: bus@32c00000 {
1095 compatible = "fsl,aips-bus", "simple-bus";
1096 reg = <0x32c00000 0x400000>;
1097 #address-cells = <1>;
1098 #size-cells = <1>;
1099 ranges = <0x32c00000 0x32c00000 0x400000>;
1100
1101 csi: csi@32e20000 {
1102 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1103 reg = <0x32e20000 0x1000>;
1104 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1106 clock-names = "mclk";
1107 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1108 status = "disabled";
1109
1110 port {
1111 csi_in: endpoint {
1112 remote-endpoint = <&imx8mm_mipi_csi_out>;
1113 };
1114 };
1115 };
1116
1117 disp_blk_ctrl: blk-ctrl@32e28000 {
1118 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1119 reg = <0x32e28000 0x100>;
1120 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1121 <&pgc_dispmix>, <&pgc_mipi>,
1122 <&pgc_mipi>;
1123 power-domain-names = "bus", "csi-bridge",
1124 "lcdif", "mipi-dsi",
1125 "mipi-csi";
1126 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1127 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1128 <&clk IMX8MM_CLK_CSI1_ROOT>,
1129 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1130 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1131 <&clk IMX8MM_CLK_DISP_ROOT>,
1132 <&clk IMX8MM_CLK_DSI_CORE>,
1133 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1134 <&clk IMX8MM_CLK_CSI1_CORE>,
1135 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1136 clock-names = "csi-bridge-axi","csi-bridge-apb",
1137 "csi-bridge-core", "lcdif-axi",
1138 "lcdif-apb", "lcdif-pix",
1139 "dsi-pclk", "dsi-ref",
1140 "csi-aclk", "csi-pclk";
1141 #power-domain-cells = <1>;
1142 };
1143
1144 mipi_csi: mipi-csi@32e30000 {
1145 compatible = "fsl,imx8mm-mipi-csi2";
1146 reg = <0x32e30000 0x1000>;
1147 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1148 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1149 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1150 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
1151 <&clk IMX8MM_SYS_PLL2_1000M>;
1152 clock-frequency = <333000000>;
1153 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1154 <&clk IMX8MM_CLK_CSI1_ROOT>,
1155 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1156 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1157 clock-names = "pclk", "wrap", "phy", "axi";
1158 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1159 status = "disabled";
1160
1161 ports {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164
1165 port@0 {
1166 reg = <0>;
1167 };
1168
1169 port@1 {
1170 reg = <1>;
1171
1172 imx8mm_mipi_csi_out: endpoint {
1173 remote-endpoint = <&csi_in>;
1174 };
1175 };
1176 };
1177 };
1178
1179 usbotg1: usb@32e40000 {
1180 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1181 reg = <0x32e40000 0x200>;
1182 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1184 clock-names = "usb1_ctrl_root_clk";
1185 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1186 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1187 phys = <&usbphynop1>;
1188 fsl,usbmisc = <&usbmisc1 0>;
1189 power-domains = <&pgc_otg1>;
1190 status = "disabled";
1191 };
1192
1193 usbmisc1: usbmisc@32e40200 {
1194 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1195 #index-cells = <1>;
1196 reg = <0x32e40200 0x200>;
1197 };
1198
1199 usbotg2: usb@32e50000 {
1200 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1201 reg = <0x32e50000 0x200>;
1202 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1204 clock-names = "usb1_ctrl_root_clk";
1205 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1206 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1207 phys = <&usbphynop2>;
1208 fsl,usbmisc = <&usbmisc2 0>;
1209 power-domains = <&pgc_otg2>;
1210 status = "disabled";
1211 };
1212
1213 usbmisc2: usbmisc@32e50200 {
1214 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1215 #index-cells = <1>;
1216 reg = <0x32e50200 0x200>;
1217 };
1218
1219 pcie_phy: pcie-phy@32f00000 {
1220 compatible = "fsl,imx8mm-pcie-phy";
1221 reg = <0x32f00000 0x10000>;
1222 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1223 clock-names = "ref";
1224 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1225 assigned-clock-rates = <100000000>;
1226 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1227 resets = <&src IMX8MQ_RESET_PCIEPHY>;
1228 reset-names = "pciephy";
1229 #phy-cells = <0>;
1230 status = "disabled";
1231 };
1232 };
1233
1234 dma_apbh: dma-controller@33000000 {
1235 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1236 reg = <0x33000000 0x2000>;
1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1242 #dma-cells = <1>;
1243 dma-channels = <4>;
1244 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1245 };
1246
1247 gpmi: nand-controller@33002000{
1248 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1249 #address-cells = <1>;
1250 #size-cells = <1>;
1251 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1252 reg-names = "gpmi-nand", "bch";
1253 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "bch";
1255 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1256 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1257 clock-names = "gpmi_io", "gpmi_bch_apb";
1258 dmas = <&dma_apbh 0>;
1259 dma-names = "rx-tx";
1260 status = "disabled";
1261 };
1262
1263 pcie0: pcie@33800000 {
1264 compatible = "fsl,imx8mm-pcie";
1265 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1266 reg-names = "dbi", "config";
1267 #address-cells = <3>;
1268 #size-cells = <2>;
1269 device_type = "pci";
1270 bus-range = <0x00 0xff>;
1271 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1272 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1273 num-lanes = <1>;
1274 num-viewport = <4>;
1275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "msi";
1277 #interrupt-cells = <1>;
1278 interrupt-map-mask = <0 0 0 0x7>;
1279 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1280 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1281 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1283 fsl,max-link-speed = <2>;
1284 linux,pci-domain = <0>;
1285 power-domains = <&pgc_pcie>;
1286 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1287 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1288 reset-names = "apps", "turnoff";
1289 phys = <&pcie_phy>;
1290 phy-names = "pcie-phy";
1291 status = "disabled";
1292 };
1293
1294 gpu_3d: gpu@38000000 {
1295 compatible = "vivante,gc";
1296 reg = <0x38000000 0x8000>;
1297 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1299 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1300 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1301 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1302 clock-names = "reg", "bus", "core", "shader";
1303 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1304 <&clk IMX8MM_GPU_PLL_OUT>;
1305 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1306 assigned-clock-rates = <0>, <1000000000>;
1307 power-domains = <&pgc_gpu>;
1308 };
1309
1310 gpu_2d: gpu@38008000 {
1311 compatible = "vivante,gc";
1312 reg = <0x38008000 0x8000>;
1313 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1315 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1316 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1317 clock-names = "reg", "bus", "core";
1318 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1319 <&clk IMX8MM_GPU_PLL_OUT>;
1320 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1321 assigned-clock-rates = <0>, <1000000000>;
1322 power-domains = <&pgc_gpu>;
1323 };
1324
1325 vpu_g1: video-codec@38300000 {
1326 compatible = "nxp,imx8mm-vpu-g1";
1327 reg = <0x38300000 0x10000>;
1328 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1329 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1330 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1331 };
1332
1333 vpu_g2: video-codec@38310000 {
1334 compatible = "nxp,imx8mq-vpu-g2";
1335 reg = <0x38310000 0x10000>;
1336 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1338 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1339 };
1340
1341 vpu_blk_ctrl: blk-ctrl@38330000 {
1342 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1343 reg = <0x38330000 0x100>;
1344 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1345 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1346 power-domain-names = "bus", "g1", "g2", "h1";
1347 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1348 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1349 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1350 clock-names = "g1", "g2", "h1";
1351 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1352 <&clk IMX8MM_CLK_VPU_G2>;
1353 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1354 <&clk IMX8MM_VPU_PLL_OUT>;
1355 assigned-clock-rates = <600000000>,
1356 <600000000>;
1357 #power-domain-cells = <1>;
1358 };
1359
1360 gic: interrupt-controller@38800000 {
1361 compatible = "arm,gic-v3";
1362 reg = <0x38800000 0x10000>, /* GIC Dist */
1363 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1364 #interrupt-cells = <3>;
1365 interrupt-controller;
1366 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1367 };
1368
1369 ddrc: memory-controller@3d400000 {
1370 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1371 reg = <0x3d400000 0x400000>;
1372 clock-names = "core", "pll", "alt", "apb";
1373 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1374 <&clk IMX8MM_DRAM_PLL>,
1375 <&clk IMX8MM_CLK_DRAM_ALT>,
1376 <&clk IMX8MM_CLK_DRAM_APB>;
1377 };
1378
1379 ddr-pmu@3d800000 {
1380 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1381 reg = <0x3d800000 0x400000>;
1382 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1383 };
1384 };
1385 };
