0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2022 Toradex
0004 */
0005
0006 #include "dt-bindings/phy/phy-imx8-pcie.h"
0007 #include "dt-bindings/pwm/pwm.h"
0008 #include "imx8mm.dtsi"
0009
0010 / {
0011 chosen {
0012 stdout-path = &uart1;
0013 };
0014
0015 aliases {
0016 rtc0 = &rtc_i2c;
0017 rtc1 = &snvs_rtc;
0018 };
0019
0020 backlight: backlight {
0021 compatible = "pwm-backlight";
0022 brightness-levels = <0 45 63 88 119 158 203 255>;
0023 default-brightness-level = <4>;
0024 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
0025 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
0028 power-supply = <®_3p3v>;
0029 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
0030 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
0031 status = "disabled";
0032 };
0033
0034 /* Fixed clock dedicated to SPI CAN controller */
0035 clk40m: oscillator {
0036 compatible = "fixed-clock";
0037 #clock-cells = <0>;
0038 clock-frequency = <40000000>;
0039 };
0040
0041 gpio-keys {
0042 compatible = "gpio-keys";
0043 pinctrl-names = "default";
0044 pinctrl-0 = <&pinctrl_gpio_keys>;
0045
0046 key-wakeup {
0047 debounce-interval = <10>;
0048 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
0049 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
0050 label = "Wake-Up";
0051 linux,code = <KEY_WAKEUP>;
0052 wakeup-source;
0053 };
0054 };
0055
0056 /* Carrier Board Supplies */
0057 reg_1p8v: regulator-1p8v {
0058 compatible = "regulator-fixed";
0059 regulator-max-microvolt = <1800000>;
0060 regulator-min-microvolt = <1800000>;
0061 regulator-name = "+V1.8_SW";
0062 };
0063
0064 reg_3p3v: regulator-3p3v {
0065 compatible = "regulator-fixed";
0066 regulator-max-microvolt = <3300000>;
0067 regulator-min-microvolt = <3300000>;
0068 regulator-name = "+V3.3_SW";
0069 };
0070
0071 reg_5p0v: regulator-5p0v {
0072 compatible = "regulator-fixed";
0073 regulator-max-microvolt = <5000000>;
0074 regulator-min-microvolt = <5000000>;
0075 regulator-name = "+V5_SW";
0076 };
0077
0078 /* Non PMIC On-module Supplies */
0079 reg_ethphy: regulator-ethphy {
0080 compatible = "regulator-fixed";
0081 enable-active-high;
0082 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
0083 off-on-delay = <500000>;
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_reg_eth>;
0086 regulator-boot-on;
0087 regulator-max-microvolt = <3300000>;
0088 regulator-min-microvolt = <3300000>;
0089 regulator-name = "On-module +V3.3_ETH";
0090 startup-delay-us = <200000>;
0091 };
0092
0093 reg_usb_otg1_vbus: regulator-usb-otg1 {
0094 compatible = "regulator-fixed";
0095 enable-active-high;
0096 /* Verdin USB_1_EN (SODIMM 155) */
0097 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0098 pinctrl-names = "default";
0099 pinctrl-0 = <&pinctrl_reg_usb1_en>;
0100 regulator-max-microvolt = <5000000>;
0101 regulator-min-microvolt = <5000000>;
0102 regulator-name = "USB_1_EN";
0103 };
0104
0105 reg_usb_otg2_vbus: regulator-usb-otg2 {
0106 compatible = "regulator-fixed";
0107 enable-active-high;
0108 /* Verdin USB_2_EN (SODIMM 185) */
0109 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_reg_usb2_en>;
0112 regulator-max-microvolt = <5000000>;
0113 regulator-min-microvolt = <5000000>;
0114 regulator-name = "USB_2_EN";
0115 };
0116
0117 reg_usdhc2_vmmc: regulator-usdhc2 {
0118 compatible = "regulator-fixed";
0119 enable-active-high;
0120 /* Verdin SD_1_PWR_EN (SODIMM 76) */
0121 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
0122 off-on-delay = <100000>;
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
0125 regulator-max-microvolt = <3300000>;
0126 regulator-min-microvolt = <3300000>;
0127 regulator-name = "+V3.3_SD";
0128 startup-delay-us = <2000>;
0129 };
0130
0131 reserved-memory {
0132 #address-cells = <2>;
0133 #size-cells = <2>;
0134 ranges;
0135
0136 /* Use the kernel configuration settings instead */
0137 /delete-node/ linux,cma;
0138 };
0139 };
0140
0141 &A53_0 {
0142 cpu-supply = <®_vdd_arm>;
0143 };
0144
0145 &A53_1 {
0146 cpu-supply = <®_vdd_arm>;
0147 };
0148
0149 &A53_2 {
0150 cpu-supply = <®_vdd_arm>;
0151 };
0152
0153 &A53_3 {
0154 cpu-supply = <®_vdd_arm>;
0155 };
0156
0157 &cpu_alert0 {
0158 temperature = <95000>;
0159 };
0160
0161 &cpu_crit0 {
0162 temperature = <105000>;
0163 };
0164
0165 &ddrc {
0166 operating-points-v2 = <&ddrc_opp_table>;
0167
0168 ddrc_opp_table: opp-table {
0169 compatible = "operating-points-v2";
0170
0171 opp-25M {
0172 opp-hz = /bits/ 64 <25000000>;
0173 };
0174
0175 opp-100M {
0176 opp-hz = /bits/ 64 <100000000>;
0177 };
0178
0179 opp-750M {
0180 opp-hz = /bits/ 64 <750000000>;
0181 };
0182 };
0183 };
0184
0185 /* Verdin SPI_1 */
0186 &ecspi2 {
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_ecspi2>;
0192 };
0193
0194 /* Verdin CAN_1 (On-module) */
0195 &ecspi3 {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_ecspi3>;
0201 status = "okay";
0202
0203 can1: can@0 {
0204 compatible = "microchip,mcp251xfd";
0205 clocks = <&clk40m>;
0206 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
0207 pinctrl-names = "default";
0208 pinctrl-0 = <&pinctrl_can1_int>;
0209 reg = <0>;
0210 spi-max-frequency = <8500000>;
0211 };
0212 };
0213
0214 /* Verdin ETH_1 (On-module PHY) */
0215 &fec1 {
0216 fsl,magic-packet;
0217 phy-handle = <ðphy0>;
0218 phy-mode = "rgmii-id";
0219 phy-supply = <®_ethphy>;
0220 pinctrl-names = "default", "sleep";
0221 pinctrl-0 = <&pinctrl_fec1>;
0222 pinctrl-1 = <&pinctrl_fec1_sleep>;
0223
0224 mdio {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227
0228 ethphy0: ethernet-phy@7 {
0229 compatible = "ethernet-phy-ieee802.3-c22";
0230 interrupt-parent = <&gpio1>;
0231 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
0232 micrel,led-mode = <0>;
0233 reg = <7>;
0234 };
0235 };
0236 };
0237
0238 /* Verdin QSPI_1 */
0239 &flexspi {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_flexspi0>;
0242 };
0243
0244 &gpio1 {
0245 gpio-line-names = "SODIMM_216",
0246 "SODIMM_19",
0247 "",
0248 "",
0249 "",
0250 "",
0251 "",
0252 "",
0253 "SODIMM_220",
0254 "SODIMM_222",
0255 "",
0256 "SODIMM_218",
0257 "SODIMM_155",
0258 "SODIMM_157",
0259 "SODIMM_185",
0260 "SODIMM_187";
0261 };
0262
0263 &gpio2 {
0264 gpio-line-names = "",
0265 "",
0266 "",
0267 "",
0268 "",
0269 "",
0270 "",
0271 "",
0272 "",
0273 "",
0274 "",
0275 "",
0276 "SODIMM_84",
0277 "SODIMM_78",
0278 "SODIMM_74",
0279 "SODIMM_80",
0280 "SODIMM_82",
0281 "SODIMM_70",
0282 "SODIMM_72";
0283 };
0284
0285 &gpio5 {
0286 gpio-line-names = "SODIMM_131",
0287 "",
0288 "SODIMM_91",
0289 "SODIMM_16",
0290 "SODIMM_15",
0291 "SODIMM_208",
0292 "SODIMM_137",
0293 "SODIMM_139",
0294 "SODIMM_141",
0295 "SODIMM_143",
0296 "SODIMM_196",
0297 "SODIMM_200",
0298 "SODIMM_198",
0299 "SODIMM_202",
0300 "",
0301 "",
0302 "SODIMM_55",
0303 "SODIMM_53",
0304 "SODIMM_95",
0305 "SODIMM_93",
0306 "SODIMM_14",
0307 "SODIMM_12",
0308 "",
0309 "",
0310 "",
0311 "",
0312 "SODIMM_210",
0313 "SODIMM_212",
0314 "SODIMM_151",
0315 "SODIMM_153";
0316
0317 ctrl-sleep-moci-hog {
0318 gpio-hog;
0319 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
0320 gpios = <1 GPIO_ACTIVE_HIGH>;
0321 line-name = "CTRL_SLEEP_MOCI#";
0322 output-high;
0323 pinctrl-names = "default";
0324 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
0325 };
0326 };
0327
0328 /* On-module I2C */
0329 &i2c1 {
0330 clock-frequency = <400000>;
0331 pinctrl-names = "default", "gpio";
0332 pinctrl-0 = <&pinctrl_i2c1>;
0333 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0334 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0335 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0336 status = "okay";
0337
0338 pca9450: pmic@25 {
0339 compatible = "nxp,pca9450a";
0340 interrupt-parent = <&gpio1>;
0341 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
0342 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0343 pinctrl-names = "default";
0344 pinctrl-0 = <&pinctrl_pmic>;
0345 reg = <0x25>;
0346 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0347
0348 /*
0349 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
0350 * behind this PMIC.
0351 */
0352
0353 regulators {
0354 reg_vdd_soc: BUCK1 {
0355 nxp,dvs-run-voltage = <850000>;
0356 nxp,dvs-standby-voltage = <800000>;
0357 regulator-always-on;
0358 regulator-boot-on;
0359 regulator-max-microvolt = <850000>;
0360 regulator-min-microvolt = <800000>;
0361 regulator-name = "On-module +VDD_SOC (BUCK1)";
0362 regulator-ramp-delay = <3125>;
0363 };
0364
0365 reg_vdd_arm: BUCK2 {
0366 nxp,dvs-run-voltage = <950000>;
0367 nxp,dvs-standby-voltage = <850000>;
0368 regulator-always-on;
0369 regulator-boot-on;
0370 regulator-max-microvolt = <1050000>;
0371 regulator-min-microvolt = <805000>;
0372 regulator-name = "On-module +VDD_ARM (BUCK2)";
0373 regulator-ramp-delay = <3125>;
0374 };
0375
0376 reg_vdd_dram: BUCK3 {
0377 regulator-always-on;
0378 regulator-boot-on;
0379 regulator-max-microvolt = <1000000>;
0380 regulator-min-microvolt = <805000>;
0381 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
0382 };
0383
0384 reg_vdd_3v3: BUCK4 {
0385 regulator-always-on;
0386 regulator-boot-on;
0387 regulator-max-microvolt = <3300000>;
0388 regulator-min-microvolt = <3300000>;
0389 regulator-name = "On-module +V3.3 (BUCK4)";
0390 };
0391
0392 reg_vdd_1v8: BUCK5 {
0393 regulator-always-on;
0394 regulator-boot-on;
0395 regulator-max-microvolt = <1800000>;
0396 regulator-min-microvolt = <1800000>;
0397 regulator-name = "PWR_1V8_MOCI (BUCK5)";
0398 };
0399
0400 reg_nvcc_dram: BUCK6 {
0401 regulator-always-on;
0402 regulator-boot-on;
0403 regulator-max-microvolt = <1100000>;
0404 regulator-min-microvolt = <1100000>;
0405 regulator-name = "On-module +VDD_DDR (BUCK6)";
0406 };
0407
0408 reg_nvcc_snvs: LDO1 {
0409 regulator-always-on;
0410 regulator-boot-on;
0411 regulator-max-microvolt = <1800000>;
0412 regulator-min-microvolt = <1800000>;
0413 regulator-name = "On-module +V1.8_SNVS (LDO1)";
0414 };
0415
0416 reg_vdd_snvs: LDO2 {
0417 regulator-always-on;
0418 regulator-boot-on;
0419 regulator-max-microvolt = <800000>;
0420 regulator-min-microvolt = <800000>;
0421 regulator-name = "On-module +V0.8_SNVS (LDO2)";
0422 };
0423
0424 reg_vdda: LDO3 {
0425 regulator-always-on;
0426 regulator-boot-on;
0427 regulator-max-microvolt = <1800000>;
0428 regulator-min-microvolt = <1800000>;
0429 regulator-name = "On-module +V1.8A (LDO3)";
0430 };
0431
0432 reg_vdd_phy: LDO4 {
0433 regulator-always-on;
0434 regulator-boot-on;
0435 regulator-max-microvolt = <900000>;
0436 regulator-min-microvolt = <900000>;
0437 regulator-name = "On-module +V0.9_MIPI (LDO4)";
0438 };
0439
0440 reg_nvcc_sd: LDO5 {
0441 regulator-max-microvolt = <3300000>;
0442 regulator-min-microvolt = <1800000>;
0443 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
0444 };
0445 };
0446 };
0447
0448 rtc_i2c: rtc@32 {
0449 compatible = "epson,rx8130";
0450 reg = <0x32>;
0451 };
0452
0453 adc@49 {
0454 compatible = "ti,ads1015";
0455 reg = <0x49>;
0456 #address-cells = <1>;
0457 #size-cells = <0>;
0458
0459 /* Verdin I2C_1 (ADC_4 - ADC_3) */
0460 channel@0 {
0461 reg = <0>;
0462 ti,datarate = <4>;
0463 ti,gain = <2>;
0464 };
0465
0466 /* Verdin I2C_1 (ADC_4 - ADC_1) */
0467 channel@1 {
0468 reg = <1>;
0469 ti,datarate = <4>;
0470 ti,gain = <2>;
0471 };
0472
0473 /* Verdin I2C_1 (ADC_3 - ADC_1) */
0474 channel@2 {
0475 reg = <2>;
0476 ti,datarate = <4>;
0477 ti,gain = <2>;
0478 };
0479
0480 /* Verdin I2C_1 (ADC_2 - ADC_1) */
0481 channel@3 {
0482 reg = <3>;
0483 ti,datarate = <4>;
0484 ti,gain = <2>;
0485 };
0486
0487 /* Verdin I2C_1 ADC_4 */
0488 channel@4 {
0489 reg = <4>;
0490 ti,datarate = <4>;
0491 ti,gain = <2>;
0492 };
0493
0494 /* Verdin I2C_1 ADC_3 */
0495 channel@5 {
0496 reg = <5>;
0497 ti,datarate = <4>;
0498 ti,gain = <2>;
0499 };
0500
0501 /* Verdin I2C_1 ADC_2 */
0502 channel@6 {
0503 reg = <6>;
0504 ti,datarate = <4>;
0505 ti,gain = <2>;
0506 };
0507
0508 /* Verdin I2C_1 ADC_1 */
0509 channel@7 {
0510 reg = <7>;
0511 ti,datarate = <4>;
0512 ti,gain = <2>;
0513 };
0514 };
0515
0516 eeprom@50 {
0517 compatible = "st,24c02";
0518 pagesize = <16>;
0519 reg = <0x50>;
0520 };
0521 };
0522
0523 /* Verdin I2C_2_DSI */
0524 &i2c2 {
0525 clock-frequency = <10000>;
0526 pinctrl-names = "default", "gpio";
0527 pinctrl-0 = <&pinctrl_i2c2>;
0528 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0529 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0530 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0531 status = "disabled";
0532 };
0533
0534 /* Verdin I2C_3_HDMI N/A */
0535
0536 /* Verdin I2C_4_CSI */
0537 &i2c3 {
0538 clock-frequency = <400000>;
0539 pinctrl-names = "default", "gpio";
0540 pinctrl-0 = <&pinctrl_i2c3>;
0541 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0542 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0543 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0544 };
0545
0546 /* Verdin I2C_1 */
0547 &i2c4 {
0548 clock-frequency = <400000>;
0549 pinctrl-names = "default", "gpio";
0550 pinctrl-0 = <&pinctrl_i2c4>;
0551 pinctrl-1 = <&pinctrl_i2c4_gpio>;
0552 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0553 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0554
0555 gpio_expander_21: gpio-expander@21 {
0556 compatible = "nxp,pcal6416";
0557 #gpio-cells = <2>;
0558 gpio-controller;
0559 reg = <0x21>;
0560 vcc-supply = <®_3p3v>;
0561 status = "disabled";
0562 };
0563
0564 lvds_ti_sn65dsi83: bridge@2c {
0565 compatible = "ti,sn65dsi83";
0566 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
0567 /* Verdin GPIO_10_DSI (SODIMM 21) */
0568 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
0569 pinctrl-names = "default";
0570 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
0571 reg = <0x2c>;
0572 status = "disabled";
0573 };
0574
0575 /* Current measurement into module VCC */
0576 hwmon: hwmon@40 {
0577 compatible = "ti,ina219";
0578 reg = <0x40>;
0579 shunt-resistor = <10000>;
0580 status = "disabled";
0581 };
0582
0583 hdmi_lontium_lt8912: hdmi@48 {
0584 compatible = "lontium,lt8912b";
0585 pinctrl-names = "default";
0586 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
0587 reg = <0x48>;
0588 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
0589 /* Verdin GPIO_10_DSI (SODIMM 21) */
0590 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
0591 status = "disabled";
0592 };
0593
0594 atmel_mxt_ts: touch@4a {
0595 compatible = "atmel,maxtouch";
0596 /*
0597 * Verdin GPIO_9_DSI
0598 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
0599 */
0600 interrupt-parent = <&gpio3>;
0601 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
0602 pinctrl-names = "default";
0603 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
0604 reg = <0x4a>;
0605 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
0606 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0607 status = "disabled";
0608 };
0609
0610 /* Temperature sensor on carrier board */
0611 hwmon_temp: sensor@4f {
0612 compatible = "ti,tmp75c";
0613 reg = <0x4f>;
0614 status = "disabled";
0615 };
0616
0617 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
0618 eeprom_display_adapter: eeprom@50 {
0619 compatible = "st,24c02";
0620 pagesize = <16>;
0621 reg = <0x50>;
0622 status = "disabled";
0623 };
0624
0625 /* EEPROM on carrier board */
0626 eeprom_carrier_board: eeprom@57 {
0627 compatible = "st,24c02";
0628 pagesize = <16>;
0629 reg = <0x57>;
0630 status = "disabled";
0631 };
0632 };
0633
0634 /* Verdin PCIE_1 */
0635 &pcie0 {
0636 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0637 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0638 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0639 <&clk IMX8MM_SYS_PLL2_250M>;
0640 assigned-clock-rates = <10000000>, <250000000>;
0641 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0642 <&clk IMX8MM_CLK_PCIE1_PHY>;
0643 clock-names = "pcie", "pcie_aux", "pcie_bus";
0644 pinctrl-names = "default";
0645 pinctrl-0 = <&pinctrl_pcie0>;
0646 /* PCIE_1_RESET# (SODIMM 244) */
0647 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
0648 };
0649
0650 &pcie_phy {
0651 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
0652 fsl,clkreq-unsupported;
0653 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
0654 fsl,tx-deemph-gen1 = <0x2d>;
0655 fsl,tx-deemph-gen2 = <0xf>;
0656 };
0657
0658 /* Verdin PWM_3_DSI */
0659 &pwm1 {
0660 pinctrl-names = "default";
0661 pinctrl-0 = <&pinctrl_pwm_1>;
0662 #pwm-cells = <3>;
0663 };
0664
0665 /* Verdin PWM_1 */
0666 &pwm2 {
0667 pinctrl-names = "default";
0668 pinctrl-0 = <&pinctrl_pwm_2>;
0669 #pwm-cells = <3>;
0670 };
0671
0672 /* Verdin PWM_2 */
0673 &pwm3 {
0674 pinctrl-names = "default";
0675 pinctrl-0 = <&pinctrl_pwm_3>;
0676 #pwm-cells = <3>;
0677 };
0678
0679 /* Verdin I2S_1 */
0680 &sai2 {
0681 #sound-dai-cells = <0>;
0682 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0683 assigned-clock-rates = <24576000>;
0684 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
0685 pinctrl-names = "default";
0686 pinctrl-0 = <&pinctrl_sai2>;
0687 };
0688
0689 &snvs_pwrkey {
0690 status = "okay";
0691 };
0692
0693 /* Verdin UART_3, used as the Linux console */
0694 &uart1 {
0695 pinctrl-names = "default";
0696 pinctrl-0 = <&pinctrl_uart1>;
0697 };
0698
0699 /* Verdin UART_1 */
0700 &uart2 {
0701 pinctrl-names = "default";
0702 pinctrl-0 = <&pinctrl_uart2>;
0703 uart-has-rtscts;
0704 };
0705
0706 /* Verdin UART_2 */
0707 &uart3 {
0708 pinctrl-names = "default";
0709 pinctrl-0 = <&pinctrl_uart3>;
0710 uart-has-rtscts;
0711 };
0712
0713 /*
0714 * Verdin UART_4
0715 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
0716 */
0717 &uart4 {
0718 pinctrl-names = "default";
0719 pinctrl-0 = <&pinctrl_uart4>;
0720 };
0721
0722 /* Verdin USB_1 */
0723 &usbotg1 {
0724 adp-disable;
0725 dr_mode = "otg";
0726 hnp-disable;
0727 over-current-active-low;
0728 samsung,picophy-dc-vol-level-adjust = <7>;
0729 samsung,picophy-pre-emp-curr-control = <3>;
0730 srp-disable;
0731 vbus-supply = <®_usb_otg1_vbus>;
0732 };
0733
0734 /* Verdin USB_2 */
0735 &usbotg2 {
0736 dr_mode = "host";
0737 over-current-active-low;
0738 samsung,picophy-dc-vol-level-adjust = <7>;
0739 samsung,picophy-pre-emp-curr-control = <3>;
0740 vbus-supply = <®_usb_otg2_vbus>;
0741 };
0742
0743 &usbphynop1 {
0744 vcc-supply = <®_vdd_3v3>;
0745 };
0746
0747 &usbphynop2 {
0748 power-domains = <&pgc_otg2>;
0749 vcc-supply = <®_vdd_3v3>;
0750 };
0751
0752 /* On-module eMMC */
0753 &usdhc1 {
0754 bus-width = <8>;
0755 keep-power-in-suspend;
0756 non-removable;
0757 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0758 pinctrl-0 = <&pinctrl_usdhc1>;
0759 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0760 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0761 status = "okay";
0762 };
0763
0764 /* Verdin SD_1 */
0765 &usdhc2 {
0766 bus-width = <4>;
0767 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0768 disable-wp;
0769 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0770 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
0771 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
0772 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
0773 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
0774 vmmc-supply = <®_usdhc2_vmmc>;
0775 };
0776
0777 &wdog1 {
0778 fsl,ext-reset-output;
0779 pinctrl-names = "default";
0780 pinctrl-0 = <&pinctrl_wdog>;
0781 status = "okay";
0782 };
0783
0784 &iomuxc {
0785 pinctrl-names = "default";
0786 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
0787 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
0788 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
0789 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
0790 <&pinctrl_pmic_tpm_ena>;
0791
0792 pinctrl_can1_int: can1intgrp {
0793 fsl,pins =
0794 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
0795 };
0796
0797 pinctrl_can2_int: can2intgrp {
0798 fsl,pins =
0799 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
0800 };
0801
0802 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
0803 fsl,pins =
0804 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
0805 };
0806
0807 pinctrl_ecspi2: ecspi2grp {
0808 fsl,pins =
0809 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
0810 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
0811 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
0812 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
0813 };
0814
0815 pinctrl_ecspi3: ecspi3grp {
0816 fsl,pins =
0817 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
0818 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
0819 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
0820 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
0821 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
0822 };
0823
0824 pinctrl_fec1: fec1grp {
0825 fsl,pins =
0826 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
0827 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
0828 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
0829 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
0830 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
0831 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
0832 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
0833 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
0834 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
0835 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
0836 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
0837 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
0838 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
0839 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
0840 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
0841 };
0842
0843 pinctrl_fec1_sleep: fec1-sleepgrp {
0844 fsl,pins =
0845 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
0846 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
0847 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
0848 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
0849 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
0850 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
0851 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
0852 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
0853 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
0854 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
0855 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
0856 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
0857 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
0858 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
0859 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
0860 };
0861
0862 pinctrl_flexspi0: flexspi0grp {
0863 fsl,pins =
0864 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
0865 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
0866 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
0867 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
0868 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
0869 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
0870 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
0871 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
0872 };
0873
0874 pinctrl_gpio1: gpio1grp {
0875 fsl,pins =
0876 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
0877 };
0878
0879 pinctrl_gpio2: gpio2grp {
0880 fsl,pins =
0881 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
0882 };
0883
0884 pinctrl_gpio3: gpio3grp {
0885 fsl,pins =
0886 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
0887 };
0888
0889 pinctrl_gpio4: gpio4grp {
0890 fsl,pins =
0891 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
0892 };
0893
0894 pinctrl_gpio5: gpio5grp {
0895 fsl,pins =
0896 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
0897 };
0898
0899 pinctrl_gpio6: gpio6grp {
0900 fsl,pins =
0901 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
0902 };
0903
0904 pinctrl_gpio7: gpio7grp {
0905 fsl,pins =
0906 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
0907 };
0908
0909 pinctrl_gpio8: gpio8grp {
0910 fsl,pins =
0911 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
0912 };
0913
0914 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
0915 pinctrl_gpio_9_dsi: gpio9dsigrp {
0916 fsl,pins =
0917 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
0918 };
0919
0920 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
0921 pinctrl_gpio_10_dsi: gpio10dsigrp {
0922 fsl,pins =
0923 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
0924 };
0925
0926 pinctrl_gpio_hog1: gpiohog1grp {
0927 fsl,pins =
0928 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
0929 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
0930 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
0931 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
0932 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
0933 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
0934 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
0935 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
0936 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
0937 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
0938 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
0939 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
0940 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
0941 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
0942 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
0943 };
0944
0945 pinctrl_gpio_hog2: gpiohog2grp {
0946 fsl,pins =
0947 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
0948 };
0949
0950 pinctrl_gpio_hog3: gpiohog3grp {
0951 fsl,pins =
0952 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
0953 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
0954 };
0955
0956 pinctrl_gpio_keys: gpiokeysgrp {
0957 fsl,pins =
0958 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
0959 };
0960
0961 /* On-module I2C */
0962 pinctrl_i2c1: i2c1grp {
0963 fsl,pins =
0964 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
0965 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
0966 };
0967
0968 pinctrl_i2c1_gpio: i2c1gpiogrp {
0969 fsl,pins =
0970 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
0971 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
0972 };
0973
0974 /* Verdin I2C_4_CSI */
0975 pinctrl_i2c2: i2c2grp {
0976 fsl,pins =
0977 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
0978 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
0979 };
0980
0981 pinctrl_i2c2_gpio: i2c2gpiogrp {
0982 fsl,pins =
0983 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
0984 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
0985 };
0986
0987 /* Verdin I2C_2_DSI */
0988 pinctrl_i2c3: i2c3grp {
0989 fsl,pins =
0990 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
0991 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
0992 };
0993
0994 pinctrl_i2c3_gpio: i2c3gpiogrp {
0995 fsl,pins =
0996 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
0997 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
0998 };
0999
1000 /* Verdin I2C_1 */
1001 pinctrl_i2c4: i2c4grp {
1002 fsl,pins =
1003 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1004 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1005 };
1006
1007 pinctrl_i2c4_gpio: i2c4gpiogrp {
1008 fsl,pins =
1009 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1010 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1011 };
1012
1013 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1014 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1015 fsl,pins =
1016 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1017 };
1018
1019 /* Verdin I2S_2_D_OUT shared with SAI5 */
1020 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1021 fsl,pins =
1022 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1023 };
1024
1025 pinctrl_pcie0: pcie0grp {
1026 fsl,pins =
1027 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1028 /* PMIC_EN_PCIe_CLK, unused */
1029 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1030 };
1031
1032 pinctrl_pmic: pmicirqgrp {
1033 fsl,pins =
1034 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1035 };
1036
1037 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1038 pinctrl_pwm_1: pwm1grp {
1039 fsl,pins =
1040 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1041 };
1042
1043 pinctrl_pwm_2: pwm2grp {
1044 fsl,pins =
1045 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1046 };
1047
1048 pinctrl_pwm_3: pwm3grp {
1049 fsl,pins =
1050 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1051 };
1052
1053 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1054 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1055 fsl,pins =
1056 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1057 };
1058
1059 pinctrl_reg_eth: regethgrp {
1060 fsl,pins =
1061 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1062 };
1063
1064 pinctrl_reg_usb1_en: regusb1engrp {
1065 fsl,pins =
1066 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1067 };
1068
1069 pinctrl_reg_usb2_en: regusb2engrp {
1070 fsl,pins =
1071 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1072 };
1073
1074 pinctrl_sai2: sai2grp {
1075 fsl,pins =
1076 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1077 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1078 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1079 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1080 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1081 };
1082
1083 pinctrl_sai5: sai5grp {
1084 fsl,pins =
1085 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1086 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1087 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1088 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1089 };
1090
1091 /* control signal for optional ATTPM20P or SE050 */
1092 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1093 fsl,pins =
1094 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1095 };
1096
1097 pinctrl_tsp: tspgrp {
1098 fsl,pins =
1099 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1100 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1101 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1102 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1103 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1104 };
1105
1106 pinctrl_uart1: uart1grp {
1107 fsl,pins =
1108 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1109 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1110 };
1111
1112 pinctrl_uart2: uart2grp {
1113 fsl,pins =
1114 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1115 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1116 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1117 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1118 };
1119
1120 pinctrl_uart3: uart3grp {
1121 fsl,pins =
1122 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1123 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1124 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1125 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1126 };
1127
1128 pinctrl_uart4: uart4grp {
1129 fsl,pins =
1130 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1131 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1132 };
1133
1134 pinctrl_usdhc1: usdhc1grp {
1135 fsl,pins =
1136 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1137 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1138 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1139 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1140 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1141 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1142 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1143 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1144 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1145 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1146 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1147 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1148 };
1149
1150 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1151 fsl,pins =
1152 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1153 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1154 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1155 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1156 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1157 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1158 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1159 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1160 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1161 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1162 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1163 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1164 };
1165
1166 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1167 fsl,pins =
1168 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1169 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1170 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1171 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1172 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1173 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1174 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1175 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1176 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1177 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1178 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1179 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1180 };
1181
1182 pinctrl_usdhc2_cd: usdhc2cdgrp {
1183 fsl,pins =
1184 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1185 };
1186
1187 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1188 fsl,pins =
1189 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1190 };
1191
1192 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1193 fsl,pins =
1194 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1195 };
1196
1197 /*
1198 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1199 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1200 */
1201 pinctrl_usdhc2: usdhc2grp {
1202 fsl,pins =
1203 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1204 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1205 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1206 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1207 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1208 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1209 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1210 };
1211
1212 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1213 fsl,pins =
1214 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1215 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1216 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1217 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1218 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1219 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1220 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1221 };
1222
1223 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1224 fsl,pins =
1225 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1226 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1227 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1228 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1229 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1230 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1231 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1232 };
1233
1234 /* Avoid backfeeding with removed card power */
1235 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1236 fsl,pins =
1237 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1238 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1239 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1240 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1241 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1242 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1243 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1244 };
1245
1246 /*
1247 * On-module Wi-Fi/BT or type specific SDHC interface
1248 * (e.g. on X52 extension slot of Verdin Development Board)
1249 */
1250 pinctrl_usdhc3: usdhc3grp {
1251 fsl,pins =
1252 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1253 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1254 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1255 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1256 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1257 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1258 };
1259
1260 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1261 fsl,pins =
1262 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1263 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1264 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1265 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1266 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1267 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1268 };
1269
1270 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1271 fsl,pins =
1272 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1273 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1274 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1275 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1276 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1277 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1278 };
1279
1280 pinctrl_wdog: wdoggrp {
1281 fsl,pins =
1282 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1283 };
1284
1285 pinctrl_wifi_ctrl: wifictrlgrp {
1286 fsl,pins =
1287 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1288 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1289 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1290 };
1291
1292 pinctrl_wifi_i2s: bti2sgrp {
1293 fsl,pins =
1294 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1295 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1296 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1297 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1298 };
1299
1300 pinctrl_wifi_pwr_en: wifipwrengrp {
1301 fsl,pins =
1302 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1303 };
1304 };
