0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2021 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/linux-event-codes.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/net/ti-dp83867.h>
0012 #include <dt-bindings/phy/phy-imx8-pcie.h>
0013
0014 #include "imx8mm.dtsi"
0015
0016 / {
0017 model = "Gateworks Venice GW7902 i.MX8MM board";
0018 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
0019
0020 aliases {
0021 ethernet1 = ð1;
0022 usb0 = &usbotg1;
0023 usb1 = &usbotg2;
0024 };
0025
0026 chosen {
0027 stdout-path = &uart2;
0028 };
0029
0030 memory@40000000 {
0031 device_type = "memory";
0032 reg = <0x0 0x40000000 0 0x80000000>;
0033 };
0034
0035 can20m: can20m {
0036 compatible = "fixed-clock";
0037 #clock-cells = <0>;
0038 clock-frequency = <20000000>;
0039 clock-output-names = "can20m";
0040 };
0041
0042 gpio-keys {
0043 compatible = "gpio-keys";
0044
0045 key-user-pb {
0046 label = "user_pb";
0047 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0048 linux,code = <BTN_0>;
0049 };
0050
0051 key-user-pb1x {
0052 label = "user_pb1x";
0053 linux,code = <BTN_1>;
0054 interrupt-parent = <&gsc>;
0055 interrupts = <0>;
0056 };
0057
0058 key-erased {
0059 label = "key_erased";
0060 linux,code = <BTN_2>;
0061 interrupt-parent = <&gsc>;
0062 interrupts = <1>;
0063 };
0064
0065 key-eeprom-wp {
0066 label = "eeprom_wp";
0067 linux,code = <BTN_3>;
0068 interrupt-parent = <&gsc>;
0069 interrupts = <2>;
0070 };
0071
0072 key-tamper {
0073 label = "tamper";
0074 linux,code = <BTN_4>;
0075 interrupt-parent = <&gsc>;
0076 interrupts = <5>;
0077 };
0078
0079 switch-hold {
0080 label = "switch_hold";
0081 linux,code = <BTN_5>;
0082 interrupt-parent = <&gsc>;
0083 interrupts = <7>;
0084 };
0085 };
0086
0087 led-controller {
0088 compatible = "gpio-leds";
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_gpio_leds>;
0091
0092 led-0 {
0093 function = LED_FUNCTION_STATUS;
0094 color = <LED_COLOR_ID_GREEN>;
0095 label = "panel1";
0096 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
0097 default-state = "off";
0098 };
0099
0100 led-1 {
0101 function = LED_FUNCTION_STATUS;
0102 color = <LED_COLOR_ID_GREEN>;
0103 label = "panel2";
0104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0105 default-state = "off";
0106 };
0107
0108 led-2 {
0109 function = LED_FUNCTION_STATUS;
0110 color = <LED_COLOR_ID_GREEN>;
0111 label = "panel3";
0112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
0113 default-state = "off";
0114 };
0115
0116 led-3 {
0117 function = LED_FUNCTION_STATUS;
0118 color = <LED_COLOR_ID_GREEN>;
0119 label = "panel4";
0120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
0121 default-state = "off";
0122 };
0123
0124 led-4 {
0125 function = LED_FUNCTION_STATUS;
0126 color = <LED_COLOR_ID_GREEN>;
0127 label = "panel5";
0128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
0129 default-state = "off";
0130 };
0131 };
0132
0133 pcie0_refclk: pcie0-refclk {
0134 compatible = "fixed-clock";
0135 #clock-cells = <0>;
0136 clock-frequency = <100000000>;
0137 };
0138
0139 pps {
0140 compatible = "pps-gpio";
0141 pinctrl-names = "default";
0142 pinctrl-0 = <&pinctrl_pps>;
0143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
0144 status = "okay";
0145 };
0146
0147 reg_3p3v: regulator-3p3v {
0148 compatible = "regulator-fixed";
0149 regulator-name = "3P3V";
0150 regulator-min-microvolt = <3300000>;
0151 regulator-max-microvolt = <3300000>;
0152 regulator-always-on;
0153 };
0154
0155 reg_usb1_vbus: regulator-usb1 {
0156 compatible = "regulator-fixed";
0157 pinctrl-names = "default";
0158 pinctrl-0 = <&pinctrl_reg_usb1>;
0159 regulator-name = "usb_usb1_vbus";
0160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
0161 enable-active-high;
0162 regulator-min-microvolt = <5000000>;
0163 regulator-max-microvolt = <5000000>;
0164 };
0165
0166 reg_wifi: regulator-wifi {
0167 compatible = "regulator-fixed";
0168 pinctrl-names = "default";
0169 pinctrl-0 = <&pinctrl_reg_wl>;
0170 regulator-name = "wifi";
0171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0172 enable-active-high;
0173 startup-delay-us = <100>;
0174 regulator-min-microvolt = <3300000>;
0175 regulator-max-microvolt = <3300000>;
0176 };
0177 };
0178
0179 &A53_0 {
0180 cpu-supply = <&buck2>;
0181 };
0182
0183 &A53_1 {
0184 cpu-supply = <&buck2>;
0185 };
0186
0187 &A53_2 {
0188 cpu-supply = <&buck2>;
0189 };
0190
0191 &A53_3 {
0192 cpu-supply = <&buck2>;
0193 };
0194
0195 &ddrc {
0196 operating-points-v2 = <&ddrc_opp_table>;
0197
0198 ddrc_opp_table: opp-table {
0199 compatible = "operating-points-v2";
0200
0201 opp-25M {
0202 opp-hz = /bits/ 64 <25000000>;
0203 };
0204
0205 opp-100M {
0206 opp-hz = /bits/ 64 <100000000>;
0207 };
0208
0209 opp-750M {
0210 opp-hz = /bits/ 64 <750000000>;
0211 };
0212 };
0213 };
0214
0215 &ecspi1 {
0216 pinctrl-names = "default";
0217 pinctrl-0 = <&pinctrl_spi1>;
0218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0219 status = "okay";
0220
0221 can@0 {
0222 compatible = "microchip,mcp2515";
0223 reg = <0>;
0224 clocks = <&can20m>;
0225 oscillator-frequency = <20000000>;
0226 interrupt-parent = <&gpio2>;
0227 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0228 spi-max-frequency = <10000000>;
0229 };
0230 };
0231
0232 /* off-board header */
0233 &ecspi2 {
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&pinctrl_spi2>;
0236 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0237 status = "okay";
0238 };
0239
0240 &fec1 {
0241 pinctrl-names = "default";
0242 pinctrl-0 = <&pinctrl_fec1>;
0243 phy-mode = "rgmii-id";
0244 phy-handle = <ðphy0>;
0245 local-mac-address = [00 00 00 00 00 00];
0246 status = "okay";
0247
0248 mdio {
0249 #address-cells = <1>;
0250 #size-cells = <0>;
0251
0252 ethphy0: ethernet-phy@0 {
0253 compatible = "ethernet-phy-ieee802.3-c22";
0254 reg = <0>;
0255 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0256 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0257 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0258 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0259 };
0260 };
0261 };
0262
0263 &gpio1 {
0264 gpio-line-names = "", "", "", "", "", "", "", "",
0265 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
0266 "", "", "", "", "", "", "", "",
0267 "", "", "", "", "", "", "", "";
0268 };
0269
0270 &gpio2 {
0271 gpio-line-names = "", "", "", "", "", "", "", "",
0272 "uart2_en#", "", "", "", "", "", "", "",
0273 "", "", "", "", "", "", "", "",
0274 "", "", "", "", "", "", "", "";
0275 };
0276
0277 &gpio3 {
0278 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
0279 "", "", "", "", "", "", "", "",
0280 "", "", "", "", "", "", "", "",
0281 "", "", "", "", "", "", "", "";
0282 };
0283
0284 &gpio4 {
0285 gpio-line-names = "", "", "", "", "", "", "", "",
0286 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
0287 "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
0288 "", "uart1_term", "uart1_half", "app_gpio2",
0289 "mipi_gpio1", "", "", "";
0290 };
0291
0292 &gpio5 {
0293 gpio-line-names = "", "", "", "mipi_gpio4",
0294 "mipi_gpio3", "mipi_gpio2", "", "",
0295 "", "", "", "", "", "", "", "",
0296 "", "", "", "", "", "", "", "",
0297 "", "", "", "", "", "", "", "";
0298 };
0299
0300 &i2c1 {
0301 clock-frequency = <100000>;
0302 pinctrl-names = "default";
0303 pinctrl-0 = <&pinctrl_i2c1>;
0304 status = "okay";
0305
0306 gsc: gsc@20 {
0307 compatible = "gw,gsc";
0308 reg = <0x20>;
0309 pinctrl-0 = <&pinctrl_gsc>;
0310 interrupt-parent = <&gpio2>;
0311 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
0312 interrupt-controller;
0313 #interrupt-cells = <1>;
0314
0315 adc {
0316 compatible = "gw,gsc-adc";
0317 #address-cells = <1>;
0318 #size-cells = <0>;
0319
0320 channel@6 {
0321 gw,mode = <0>;
0322 reg = <0x06>;
0323 label = "temp";
0324 };
0325
0326 channel@8 {
0327 gw,mode = <1>;
0328 reg = <0x08>;
0329 label = "vdd_bat";
0330 };
0331
0332 channel@82 {
0333 gw,mode = <2>;
0334 reg = <0x82>;
0335 label = "vin";
0336 gw,voltage-divider-ohms = <22100 1000>;
0337 gw,voltage-offset-microvolt = <700000>;
0338 };
0339
0340 channel@84 {
0341 gw,mode = <2>;
0342 reg = <0x84>;
0343 label = "vin_4p0";
0344 gw,voltage-divider-ohms = <10000 10000>;
0345 };
0346
0347 channel@86 {
0348 gw,mode = <2>;
0349 reg = <0x86>;
0350 label = "vdd_3p3";
0351 gw,voltage-divider-ohms = <10000 10000>;
0352 };
0353
0354 channel@88 {
0355 gw,mode = <2>;
0356 reg = <0x88>;
0357 label = "vdd_0p9";
0358 };
0359
0360 channel@8c {
0361 gw,mode = <2>;
0362 reg = <0x8c>;
0363 label = "vdd_soc";
0364 };
0365
0366 channel@8e {
0367 gw,mode = <2>;
0368 reg = <0x8e>;
0369 label = "vdd_arm";
0370 };
0371
0372 channel@90 {
0373 gw,mode = <2>;
0374 reg = <0x90>;
0375 label = "vdd_1p8";
0376 };
0377
0378 channel@92 {
0379 gw,mode = <2>;
0380 reg = <0x92>;
0381 label = "vdd_dram";
0382 };
0383
0384 channel@98 {
0385 gw,mode = <2>;
0386 reg = <0x98>;
0387 label = "vdd_1p0";
0388 };
0389
0390 channel@9a {
0391 gw,mode = <2>;
0392 reg = <0x9a>;
0393 label = "vdd_2p5";
0394 gw,voltage-divider-ohms = <10000 10000>;
0395 };
0396
0397 channel@9c {
0398 gw,mode = <2>;
0399 reg = <0x9c>;
0400 label = "vdd_5p0";
0401 gw,voltage-divider-ohms = <10000 10000>;
0402 };
0403
0404 channel@a2 {
0405 gw,mode = <2>;
0406 reg = <0xa2>;
0407 label = "vdd_gsc";
0408 gw,voltage-divider-ohms = <10000 10000>;
0409 };
0410 };
0411 };
0412
0413 gpio: gpio@23 {
0414 compatible = "nxp,pca9555";
0415 reg = <0x23>;
0416 gpio-controller;
0417 #gpio-cells = <2>;
0418 interrupt-parent = <&gsc>;
0419 interrupts = <4>;
0420 };
0421
0422 pmic@4b {
0423 compatible = "rohm,bd71847";
0424 reg = <0x4b>;
0425 pinctrl-names = "default";
0426 pinctrl-0 = <&pinctrl_pmic>;
0427 interrupt-parent = <&gpio3>;
0428 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0429 rohm,reset-snvs-powered;
0430 #clock-cells = <0>;
0431 clocks = <&osc_32k 0>;
0432 clock-output-names = "clk-32k-out";
0433
0434 regulators {
0435 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
0436 BUCK1 {
0437 regulator-name = "buck1";
0438 regulator-min-microvolt = <700000>;
0439 regulator-max-microvolt = <1300000>;
0440 regulator-boot-on;
0441 regulator-always-on;
0442 regulator-ramp-delay = <1250>;
0443 };
0444
0445 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
0446 buck2: BUCK2 {
0447 regulator-name = "buck2";
0448 regulator-min-microvolt = <700000>;
0449 regulator-max-microvolt = <1300000>;
0450 regulator-boot-on;
0451 regulator-always-on;
0452 regulator-ramp-delay = <1250>;
0453 rohm,dvs-run-voltage = <1000000>;
0454 rohm,dvs-idle-voltage = <900000>;
0455 };
0456
0457 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
0458 BUCK3 {
0459 regulator-name = "buck3";
0460 regulator-min-microvolt = <700000>;
0461 regulator-max-microvolt = <1350000>;
0462 regulator-boot-on;
0463 regulator-always-on;
0464 };
0465
0466 /* vdd_3p3 */
0467 BUCK4 {
0468 regulator-name = "buck4";
0469 regulator-min-microvolt = <3000000>;
0470 regulator-max-microvolt = <3300000>;
0471 regulator-boot-on;
0472 regulator-always-on;
0473 };
0474
0475 /* vdd_1p8 */
0476 BUCK5 {
0477 regulator-name = "buck5";
0478 regulator-min-microvolt = <1605000>;
0479 regulator-max-microvolt = <1995000>;
0480 regulator-boot-on;
0481 regulator-always-on;
0482 };
0483
0484 /* vdd_dram */
0485 BUCK6 {
0486 regulator-name = "buck6";
0487 regulator-min-microvolt = <800000>;
0488 regulator-max-microvolt = <1400000>;
0489 regulator-boot-on;
0490 regulator-always-on;
0491 };
0492
0493 /* nvcc_snvs_1p8 */
0494 LDO1 {
0495 regulator-name = "ldo1";
0496 regulator-min-microvolt = <1600000>;
0497 regulator-max-microvolt = <1900000>;
0498 regulator-boot-on;
0499 regulator-always-on;
0500 };
0501
0502 /* vdd_snvs_0p8 */
0503 LDO2 {
0504 regulator-name = "ldo2";
0505 regulator-min-microvolt = <800000>;
0506 regulator-max-microvolt = <900000>;
0507 regulator-boot-on;
0508 regulator-always-on;
0509 };
0510
0511 /* vdda_1p8 */
0512 LDO3 {
0513 regulator-name = "ldo3";
0514 regulator-min-microvolt = <1800000>;
0515 regulator-max-microvolt = <3300000>;
0516 regulator-boot-on;
0517 regulator-always-on;
0518 };
0519
0520 LDO4 {
0521 regulator-name = "ldo4";
0522 regulator-min-microvolt = <900000>;
0523 regulator-max-microvolt = <1800000>;
0524 regulator-boot-on;
0525 regulator-always-on;
0526 };
0527
0528 LDO6 {
0529 regulator-name = "ldo6";
0530 regulator-min-microvolt = <900000>;
0531 regulator-max-microvolt = <1800000>;
0532 regulator-boot-on;
0533 regulator-always-on;
0534 };
0535 };
0536 };
0537
0538 eeprom@50 {
0539 compatible = "atmel,24c02";
0540 reg = <0x50>;
0541 pagesize = <16>;
0542 };
0543
0544 eeprom@51 {
0545 compatible = "atmel,24c02";
0546 reg = <0x51>;
0547 pagesize = <16>;
0548 };
0549
0550 eeprom@52 {
0551 compatible = "atmel,24c02";
0552 reg = <0x52>;
0553 pagesize = <16>;
0554 };
0555
0556 eeprom@53 {
0557 compatible = "atmel,24c02";
0558 reg = <0x53>;
0559 pagesize = <16>;
0560 };
0561
0562 rtc@68 {
0563 compatible = "dallas,ds1672";
0564 reg = <0x68>;
0565 };
0566 };
0567
0568 &i2c2 {
0569 clock-frequency = <400000>;
0570 pinctrl-names = "default";
0571 pinctrl-0 = <&pinctrl_i2c2>;
0572 status = "okay";
0573
0574 accelerometer@19 {
0575 compatible = "st,lis2de12";
0576 pinctrl-names = "default";
0577 pinctrl-0 = <&pinctrl_accel>;
0578 reg = <0x19>;
0579 st,drdy-int-pin = <1>;
0580 interrupt-parent = <&gpio1>;
0581 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0582 interrupt-names = "INT1";
0583 };
0584 };
0585
0586 /* off-board header */
0587 &i2c3 {
0588 clock-frequency = <400000>;
0589 pinctrl-names = "default";
0590 pinctrl-0 = <&pinctrl_i2c3>;
0591 status = "okay";
0592 };
0593
0594 /* off-board header */
0595 &i2c4 {
0596 clock-frequency = <400000>;
0597 pinctrl-names = "default";
0598 pinctrl-0 = <&pinctrl_i2c4>;
0599 status = "okay";
0600 };
0601
0602 &pcie_phy {
0603 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0604 fsl,clkreq-unsupported;
0605 clocks = <&pcie0_refclk>;
0606 clock-names = "ref";
0607 status = "okay";
0608 };
0609
0610 &pcie0 {
0611 pinctrl-names = "default";
0612 pinctrl-0 = <&pinctrl_pcie0>;
0613 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
0614 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0615 <&pcie0_refclk>;
0616 clock-names = "pcie", "pcie_aux", "pcie_bus";
0617 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0618 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0619 assigned-clock-rates = <10000000>, <250000000>;
0620 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0621 <&clk IMX8MM_SYS_PLL2_250M>;
0622 status = "okay";
0623
0624 pcie@0,0 {
0625 reg = <0x0000 0 0 0 0>;
0626 #address-cells = <1>;
0627 #size-cells = <0>;
0628
0629 eth1: pcie@1,0 {
0630 reg = <0x0000 0 0 0 0>;
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633
0634 local-mac-address = [00 00 00 00 00 00];
0635 };
0636 };
0637 };
0638
0639 /* off-board header */
0640 &sai3 {
0641 pinctrl-names = "default";
0642 pinctrl-0 = <&pinctrl_sai3>;
0643 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
0644 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0645 assigned-clock-rates = <24576000>;
0646 status = "okay";
0647 };
0648
0649 /* RS232/RS485/RS422 selectable */
0650 &uart1 {
0651 pinctrl-names = "default";
0652 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
0653 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
0654 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
0655 uart-has-rtscts;
0656 status = "okay";
0657 };
0658
0659 /* RS232 console */
0660 &uart2 {
0661 pinctrl-names = "default";
0662 pinctrl-0 = <&pinctrl_uart2>;
0663 status = "okay";
0664 };
0665
0666 /* bluetooth HCI */
0667 &uart3 {
0668 pinctrl-names = "default";
0669 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
0670 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
0671 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0672 uart-has-rtscts;
0673 status = "okay";
0674
0675 bluetooth {
0676 compatible = "brcm,bcm4330-bt";
0677 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
0678 };
0679 };
0680
0681 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
0682 &uart4 {
0683 pinctrl-names = "default";
0684 pinctrl-0 = <&pinctrl_uart4>;
0685 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
0686 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
0687 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
0688 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
0689 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
0690 uart-has-rtscts;
0691 status = "okay";
0692 };
0693
0694 &usbotg1 {
0695 dr_mode = "host";
0696 vbus-supply = <®_usb1_vbus>;
0697 disable-over-current;
0698 status = "okay";
0699 };
0700
0701 &usbotg2 {
0702 dr_mode = "host";
0703 disable-over-current;
0704 status = "okay";
0705 };
0706
0707 /* SDIO WiFi */
0708 &usdhc2 {
0709 pinctrl-names = "default";
0710 pinctrl-0 = <&pinctrl_usdhc2>;
0711 bus-width = <4>;
0712 non-removable;
0713 vmmc-supply = <®_wifi>;
0714 status = "okay";
0715 };
0716
0717 /* eMMC */
0718 &usdhc3 {
0719 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0720 pinctrl-0 = <&pinctrl_usdhc3>;
0721 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0722 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0723 bus-width = <8>;
0724 non-removable;
0725 status = "okay";
0726 };
0727
0728 &wdog1 {
0729 pinctrl-names = "default";
0730 pinctrl-0 = <&pinctrl_wdog>;
0731 fsl,ext-reset-output;
0732 status = "okay";
0733 };
0734
0735 &iomuxc {
0736 pinctrl-names = "default";
0737 pinctrl-0 = <&pinctrl_hog>;
0738
0739 pinctrl_hog: hoggrp {
0740 fsl,pins = <
0741 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
0742 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
0743 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
0744 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
0745 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
0746 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
0747 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
0748 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
0749 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
0750 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
0751 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
0752 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
0753 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
0754 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
0755 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
0756 >;
0757 };
0758
0759 pinctrl_accel: accelgrp {
0760 fsl,pins = <
0761 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
0762 >;
0763 };
0764
0765 pinctrl_fec1: fec1grp {
0766 fsl,pins = <
0767 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0768 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0769 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0770 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0771 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0772 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0773 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0774 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0775 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0776 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0777 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0778 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0779 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0780 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0781 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
0782 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
0783 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
0784 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
0785 >;
0786 };
0787
0788 pinctrl_gsc: gscgrp {
0789 fsl,pins = <
0790 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
0791 >;
0792 };
0793
0794 pinctrl_i2c1: i2c1grp {
0795 fsl,pins = <
0796 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0797 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0798 >;
0799 };
0800
0801 pinctrl_i2c2: i2c2grp {
0802 fsl,pins = <
0803 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0804 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0805 >;
0806 };
0807
0808 pinctrl_i2c3: i2c3grp {
0809 fsl,pins = <
0810 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0811 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0812 >;
0813 };
0814
0815 pinctrl_i2c4: i2c4grp {
0816 fsl,pins = <
0817 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
0818 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
0819 >;
0820 };
0821
0822 pinctrl_gpio_leds: gpioledgrp {
0823 fsl,pins = <
0824 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
0825 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
0826 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
0827 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
0828 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
0829 >;
0830 };
0831
0832 pinctrl_pcie0: pciegrp {
0833 fsl,pins = <
0834 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
0835 >;
0836 };
0837
0838 pinctrl_pmic: pmicgrp {
0839 fsl,pins = <
0840 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
0841 >;
0842 };
0843
0844 pinctrl_pps: ppsgrp {
0845 fsl,pins = <
0846 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
0847 >;
0848 };
0849
0850 pinctrl_reg_wl: regwlgrp {
0851 fsl,pins = <
0852 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
0853 >;
0854 };
0855
0856 pinctrl_reg_usb1: regusb1grp {
0857 fsl,pins = <
0858 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
0859 >;
0860 };
0861
0862 pinctrl_sai3: sai3grp {
0863 fsl,pins = <
0864 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0865 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0866 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0867 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0868 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0869 >;
0870 };
0871
0872 pinctrl_spi1: spi1grp {
0873 fsl,pins = <
0874 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
0875 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
0876 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
0877 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
0878 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
0879 >;
0880 };
0881
0882 pinctrl_spi2: spi2grp {
0883 fsl,pins = <
0884 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
0885 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
0886 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
0887 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
0888 >;
0889 };
0890
0891 pinctrl_uart1: uart1grp {
0892 fsl,pins = <
0893 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0894 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0895 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
0896 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
0897 >;
0898 };
0899
0900 pinctrl_uart1_gpio: uart1gpiogrp {
0901 fsl,pins = <
0902 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
0903 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
0904 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
0905 >;
0906 };
0907
0908 pinctrl_uart2: uart2grp {
0909 fsl,pins = <
0910 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0911 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0912 >;
0913 };
0914
0915 pinctrl_uart3_gpio: uart3_gpiogrp {
0916 fsl,pins = <
0917 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
0918 >;
0919 };
0920
0921 pinctrl_uart3: uart3grp {
0922 fsl,pins = <
0923 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0924 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0925 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
0926 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
0927 >;
0928 };
0929
0930 pinctrl_uart4: uart4grp {
0931 fsl,pins = <
0932 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0933 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0934 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
0935 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
0936 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
0937 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
0938 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
0939 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
0940 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
0941 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
0942 >;
0943 };
0944
0945 pinctrl_usdhc2: usdhc2grp {
0946 fsl,pins = <
0947 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0948 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0949 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0950 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0951 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0952 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0953 >;
0954 };
0955
0956 pinctrl_usdhc3: usdhc3grp {
0957 fsl,pins = <
0958 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0959 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0960 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0961 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0962 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0963 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0964 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0965 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0966 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0967 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0968 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0969 >;
0970 };
0971
0972 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0973 fsl,pins = <
0974 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0975 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0976 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0977 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0978 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0979 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0980 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0981 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0982 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0983 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0984 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0985 >;
0986 };
0987
0988 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0989 fsl,pins = <
0990 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0991 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0992 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0993 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0994 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0995 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0996 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0997 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0998 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0999 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1000 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1001 >;
1002 };
1003
1004 pinctrl_wdog: wdoggrp {
1005 fsl,pins = <
1006 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1007 >;
1008 };
1009 };
