0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2020 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/leds/common.h>
0008 #include <dt-bindings/phy/phy-imx8-pcie.h>
0009
0010 / {
0011 aliases {
0012 ethernet1 = ð1;
0013 usb0 = &usbotg1;
0014 usb1 = &usbotg2;
0015 };
0016
0017 led-controller {
0018 compatible = "gpio-leds";
0019 pinctrl-names = "default";
0020 pinctrl-0 = <&pinctrl_gpio_leds>;
0021
0022 led-0 {
0023 function = LED_FUNCTION_STATUS;
0024 color = <LED_COLOR_ID_GREEN>;
0025 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0026 default-state = "on";
0027 linux,default-trigger = "heartbeat";
0028 };
0029
0030 led-1 {
0031 function = LED_FUNCTION_STATUS;
0032 color = <LED_COLOR_ID_RED>;
0033 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0034 default-state = "off";
0035 };
0036 };
0037
0038 pcie0_refclk: pcie0-refclk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 clock-frequency = <100000000>;
0042 };
0043
0044 pps {
0045 compatible = "pps-gpio";
0046 pinctrl-names = "default";
0047 pinctrl-0 = <&pinctrl_pps>;
0048 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
0049 status = "okay";
0050 };
0051
0052 reg_3p3v: regulator-3p3v {
0053 compatible = "regulator-fixed";
0054 regulator-name = "3P3V";
0055 regulator-min-microvolt = <3300000>;
0056 regulator-max-microvolt = <3300000>;
0057 regulator-always-on;
0058 };
0059
0060 reg_usb_otg1_vbus: regulator-usb-otg1 {
0061 pinctrl-names = "default";
0062 pinctrl-0 = <&pinctrl_reg_usb1_en>;
0063 compatible = "regulator-fixed";
0064 regulator-name = "usb_otg1_vbus";
0065 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0066 enable-active-high;
0067 regulator-min-microvolt = <5000000>;
0068 regulator-max-microvolt = <5000000>;
0069 };
0070
0071 reg_usb_otg2_vbus: regulator-usb-otg2 {
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&pinctrl_reg_usb2_en>;
0074 compatible = "regulator-fixed";
0075 regulator-name = "usb_otg2_vbus";
0076 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0077 enable-active-high;
0078 regulator-min-microvolt = <5000000>;
0079 regulator-max-microvolt = <5000000>;
0080 };
0081 };
0082
0083 /* off-board header */
0084 &ecspi2 {
0085 pinctrl-names = "default";
0086 pinctrl-0 = <&pinctrl_spi2>;
0087 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0088 status = "okay";
0089 };
0090
0091 &gpio1 {
0092 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
0093 "", "", "pci_usb_sel", "dio0",
0094 "", "dio1", "", "", "", "", "", "",
0095 "", "", "", "", "", "", "", "",
0096 "", "", "", "", "", "", "", "";
0097 };
0098
0099 &gpio4 {
0100 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
0101 "mipi_gpio1", "", "", "pci_wdis#",
0102 "", "", "", "", "", "", "", "",
0103 "", "", "", "", "", "", "", "",
0104 "", "", "", "", "", "", "", "";
0105 };
0106
0107 &i2c2 {
0108 clock-frequency = <400000>;
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_i2c2>;
0111 status = "okay";
0112
0113 accelerometer@19 {
0114 pinctrl-names = "default";
0115 pinctrl-0 = <&pinctrl_accel>;
0116 compatible = "st,lis2de12";
0117 reg = <0x19>;
0118 st,drdy-int-pin = <1>;
0119 interrupt-parent = <&gpio4>;
0120 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0121 interrupt-names = "INT1";
0122 };
0123 };
0124
0125 /* off-board header */
0126 &i2c3 {
0127 clock-frequency = <400000>;
0128 pinctrl-names = "default";
0129 pinctrl-0 = <&pinctrl_i2c3>;
0130 status = "okay";
0131 };
0132
0133 &pcie_phy {
0134 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0135 fsl,clkreq-unsupported;
0136 clocks = <&pcie0_refclk>;
0137 clock-names = "ref";
0138 status = "okay";
0139 };
0140
0141 &pcie0 {
0142 pinctrl-names = "default";
0143 pinctrl-0 = <&pinctrl_pcie0>;
0144 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
0145 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0146 <&pcie0_refclk>;
0147 clock-names = "pcie", "pcie_aux", "pcie_bus";
0148 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0149 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0150 assigned-clock-rates = <10000000>, <250000000>;
0151 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0152 <&clk IMX8MM_SYS_PLL2_250M>;
0153 status = "okay";
0154
0155 pcie@0,0 {
0156 reg = <0x0000 0 0 0 0>;
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159
0160 pcie@1,0 {
0161 reg = <0x0000 0 0 0 0>;
0162 #address-cells = <1>;
0163 #size-cells = <0>;
0164
0165 pcie@2,3 {
0166 reg = <0x1800 0 0 0 0>;
0167 #address-cells = <1>;
0168 #size-cells = <0>;
0169
0170 eth1: pcie@5,0 {
0171 reg = <0x0000 0 0 0 0>;
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 local-mac-address = [00 00 00 00 00 00];
0176 };
0177 };
0178 };
0179 };
0180 };
0181
0182 /* off-board header */
0183 &sai3 {
0184 pinctrl-names = "default";
0185 pinctrl-0 = <&pinctrl_sai3>;
0186 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
0187 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0188 assigned-clock-rates = <24576000>;
0189 status = "okay";
0190 };
0191
0192 /* GPS */
0193 &uart1 {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&pinctrl_uart1>;
0196 status = "okay";
0197 };
0198
0199 /* off-board header */
0200 &uart3 {
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_uart3>;
0203 status = "okay";
0204 };
0205
0206 /* RS232 */
0207 &uart4 {
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&pinctrl_uart4>;
0210 status = "okay";
0211 };
0212
0213 &usbotg1 {
0214 dr_mode = "otg";
0215 over-current-active-low;
0216 vbus-supply = <®_usb_otg1_vbus>;
0217 status = "okay";
0218 };
0219
0220 &usbotg2 {
0221 dr_mode = "host";
0222 disable-over-current;
0223 vbus-supply = <®_usb_otg2_vbus>;
0224 status = "okay";
0225 };
0226
0227 /* microSD */
0228 &usdhc2 {
0229 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0230 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0231 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0232 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0233 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0234 bus-width = <4>;
0235 vmmc-supply = <®_3p3v>;
0236 status = "okay";
0237 };
0238
0239 &iomuxc {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_hog>;
0242
0243 pinctrl_hog: hoggrp {
0244 fsl,pins = <
0245 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
0246 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
0247 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
0248 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
0249 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
0250 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
0251 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
0252 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
0253 >;
0254 };
0255
0256 pinctrl_accel: accelgrp {
0257 fsl,pins = <
0258 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
0259 >;
0260 };
0261
0262 pinctrl_gpio_leds: gpioledgrp {
0263 fsl,pins = <
0264 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
0265 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
0266 >;
0267 };
0268
0269 pinctrl_i2c3: i2c3grp {
0270 fsl,pins = <
0271 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0272 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0273 >;
0274 };
0275
0276 pinctrl_pcie0: pcie0grp {
0277 fsl,pins = <
0278 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
0279 >;
0280 };
0281
0282 pinctrl_pps: ppsgrp {
0283 fsl,pins = <
0284 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
0285 >;
0286 };
0287
0288 pinctrl_reg_usb1_en: regusb1grp {
0289 fsl,pins = <
0290 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
0291 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
0292 >;
0293 };
0294
0295 pinctrl_reg_usb2_en: regusb2grp {
0296 fsl,pins = <
0297 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
0298 >;
0299 };
0300
0301 pinctrl_sai3: sai3grp {
0302 fsl,pins = <
0303 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0304 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0305 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0306 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0307 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0308 >;
0309 };
0310
0311 pinctrl_spi2: spi2grp {
0312 fsl,pins = <
0313 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
0314 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
0315 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
0316 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
0317 >;
0318 };
0319
0320 pinctrl_uart1: uart1grp {
0321 fsl,pins = <
0322 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0323 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0324 >;
0325 };
0326
0327 pinctrl_uart3: uart3grp {
0328 fsl,pins = <
0329 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0330 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0331 >;
0332 };
0333
0334 pinctrl_uart4: uart4grp {
0335 fsl,pins = <
0336 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0337 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0338 >;
0339 };
0340
0341 pinctrl_usdhc1: usdhc1grp {
0342 fsl,pins = <
0343 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0344 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0345 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0346 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0347 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0348 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0349 >;
0350 };
0351
0352 pinctrl_usdhc2: usdhc2grp {
0353 fsl,pins = <
0354 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0355 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0356 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0357 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0358 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0359 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0360 >;
0361 };
0362
0363 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0364 fsl,pins = <
0365 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0366 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0367 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0368 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0369 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0370 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0371 >;
0372 };
0373
0374 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0375 fsl,pins = <
0376 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0377 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0378 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0379 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0380 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0381 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0382 >;
0383 };
0384
0385 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0386 fsl,pins = <
0387 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
0388 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
0389 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0390 >;
0391 };
0392 };
