0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2020 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/leds/common.h>
0008 #include <dt-bindings/phy/phy-imx8-pcie.h>
0009
0010 / {
0011 aliases {
0012 usb0 = &usbotg1;
0013 usb1 = &usbotg2;
0014 };
0015
0016 led-controller {
0017 compatible = "gpio-leds";
0018 pinctrl-names = "default";
0019 pinctrl-0 = <&pinctrl_gpio_leds>;
0020
0021 led-0 {
0022 function = LED_FUNCTION_STATUS;
0023 color = <LED_COLOR_ID_GREEN>;
0024 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0025 default-state = "on";
0026 linux,default-trigger = "heartbeat";
0027 };
0028
0029 led-1 {
0030 function = LED_FUNCTION_STATUS;
0031 color = <LED_COLOR_ID_RED>;
0032 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0033 default-state = "off";
0034 };
0035 };
0036
0037 pcie0_refclk: pcie0-refclk {
0038 compatible = "fixed-clock";
0039 #clock-cells = <0>;
0040 clock-frequency = <100000000>;
0041 };
0042
0043 pps {
0044 compatible = "pps-gpio";
0045 pinctrl-names = "default";
0046 pinctrl-0 = <&pinctrl_pps>;
0047 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
0048 status = "okay";
0049 };
0050
0051 reg_usb_otg1_vbus: regulator-usb-otg1 {
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_reg_usb1_en>;
0054 compatible = "regulator-fixed";
0055 regulator-name = "usb_otg1_vbus";
0056 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0057 enable-active-high;
0058 regulator-min-microvolt = <5000000>;
0059 regulator-max-microvolt = <5000000>;
0060 };
0061 };
0062
0063 /* off-board header */
0064 &ecspi2 {
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_spi2>;
0067 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0068 status = "okay";
0069 };
0070
0071 &gpio1 {
0072 gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
0073 "", "dio1", "", "", "", "", "", "",
0074 "", "", "", "", "", "", "", "",
0075 "", "", "", "", "", "", "", "";
0076 };
0077
0078 &gpio4 {
0079 gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
0080 "", "", "", "", "", "", "", "",
0081 "", "", "", "", "", "", "", "",
0082 "", "", "", "", "", "", "", "";
0083 };
0084
0085 &i2c2 {
0086 clock-frequency = <400000>;
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&pinctrl_i2c2>;
0089 status = "okay";
0090
0091 accelerometer@19 {
0092 pinctrl-names = "default";
0093 pinctrl-0 = <&pinctrl_accel>;
0094 compatible = "st,lis2de12";
0095 reg = <0x19>;
0096 st,drdy-int-pin = <1>;
0097 interrupt-parent = <&gpio4>;
0098 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0099 interrupt-names = "INT1";
0100 };
0101 };
0102
0103 /* off-board header */
0104 &i2c3 {
0105 clock-frequency = <400000>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&pinctrl_i2c3>;
0108 status = "okay";
0109 };
0110
0111 &pcie_phy {
0112 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0113 fsl,clkreq-unsupported;
0114 clocks = <&pcie0_refclk>;
0115 clock-names = "ref";
0116 status = "okay";
0117 };
0118
0119 &pcie0 {
0120 pinctrl-names = "default";
0121 pinctrl-0 = <&pinctrl_pcie0>;
0122 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
0123 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0124 <&pcie0_refclk>;
0125 clock-names = "pcie", "pcie_aux", "pcie_bus";
0126 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0127 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0128 assigned-clock-rates = <10000000>, <250000000>;
0129 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0130 <&clk IMX8MM_SYS_PLL2_250M>;
0131 status = "okay";
0132 };
0133
0134 /* GPS */
0135 &uart1 {
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&pinctrl_uart1>;
0138 status = "okay";
0139 };
0140
0141 /* off-board header */
0142 &uart3 {
0143 pinctrl-names = "default";
0144 pinctrl-0 = <&pinctrl_uart3>;
0145 status = "okay";
0146 };
0147
0148 &usbotg1 {
0149 dr_mode = "otg";
0150 over-current-active-low;
0151 vbus-supply = <®_usb_otg1_vbus>;
0152 status = "okay";
0153 };
0154
0155 &usbotg2 {
0156 dr_mode = "host";
0157 disable-over-current;
0158 status = "okay";
0159 };
0160
0161 &iomuxc {
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_hog>;
0164
0165 pinctrl_hog: hoggrp {
0166 fsl,pins = <
0167 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
0168 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
0169 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
0170 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
0171 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
0172 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
0173 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
0174 >;
0175 };
0176
0177 pinctrl_accel: accelgrp {
0178 fsl,pins = <
0179 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
0180 >;
0181 };
0182
0183 pinctrl_gpio_leds: gpioledgrp {
0184 fsl,pins = <
0185 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
0186 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
0187 >;
0188 };
0189
0190 pinctrl_i2c3: i2c3grp {
0191 fsl,pins = <
0192 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0193 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0194 >;
0195 };
0196
0197 pinctrl_pcie0: pcie0grp {
0198 fsl,pins = <
0199 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
0200 >;
0201 };
0202
0203 pinctrl_pps: ppsgrp {
0204 fsl,pins = <
0205 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
0206 >;
0207 };
0208
0209 pinctrl_reg_usb1_en: regusb1grp {
0210 fsl,pins = <
0211 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
0212 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
0213 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
0214 >;
0215 };
0216
0217 pinctrl_spi2: spi2grp {
0218 fsl,pins = <
0219 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
0220 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
0221 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
0222 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
0223 >;
0224 };
0225
0226 pinctrl_uart1: uart1grp {
0227 fsl,pins = <
0228 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0229 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0230 >;
0231 };
0232
0233 pinctrl_uart3: uart3grp {
0234 fsl,pins = <
0235 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0236 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0237 >;
0238 };
0239 };
