0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
0005 */
0006
0007 #include "imx8mm.dtsi"
0008
0009 / {
0010 model = "Variscite VAR-SOM-MX8MM module";
0011 compatible = "variscite,var-som-mx8mm", "fsl,imx8mm";
0012
0013 chosen {
0014 stdout-path = &uart4;
0015 };
0016
0017 memory@40000000 {
0018 device_type = "memory";
0019 reg = <0x0 0x40000000 0 0x80000000>;
0020 };
0021
0022 reg_eth_phy: regulator-eth-phy {
0023 compatible = "regulator-fixed";
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&pinctrl_reg_eth_phy>;
0026 regulator-name = "eth_phy_pwr";
0027 regulator-min-microvolt = <3300000>;
0028 regulator-max-microvolt = <3300000>;
0029 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
0030 enable-active-high;
0031 };
0032 };
0033
0034 &A53_0 {
0035 cpu-supply = <&buck2_reg>;
0036 };
0037
0038 &A53_1 {
0039 cpu-supply = <&buck2_reg>;
0040 };
0041
0042 &A53_2 {
0043 cpu-supply = <&buck2_reg>;
0044 };
0045
0046 &A53_3 {
0047 cpu-supply = <&buck2_reg>;
0048 };
0049
0050 &ddrc {
0051 operating-points-v2 = <&ddrc_opp_table>;
0052
0053 ddrc_opp_table: opp-table {
0054 compatible = "operating-points-v2";
0055
0056 opp-25M {
0057 opp-hz = /bits/ 64 <25000000>;
0058 };
0059
0060 opp-100M {
0061 opp-hz = /bits/ 64 <100000000>;
0062 };
0063
0064 opp-750M {
0065 opp-hz = /bits/ 64 <750000000>;
0066 };
0067 };
0068 };
0069
0070 &ecspi1 {
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_ecspi1>;
0073 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
0074 <&gpio1 0 GPIO_ACTIVE_LOW>;
0075 /delete-property/ dmas;
0076 /delete-property/ dma-names;
0077 status = "okay";
0078
0079 /* Resistive touch controller */
0080 touchscreen@0 {
0081 reg = <0>;
0082 compatible = "ti,ads7846";
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_restouch>;
0085 interrupt-parent = <&gpio1>;
0086 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
0087
0088 spi-max-frequency = <1500000>;
0089 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
0090
0091 ti,x-min = /bits/ 16 <125>;
0092 touchscreen-size-x = <4008>;
0093 ti,y-min = /bits/ 16 <282>;
0094 touchscreen-size-y = <3864>;
0095 ti,x-plate-ohms = /bits/ 16 <180>;
0096 touchscreen-max-pressure = <255>;
0097 touchscreen-average-samples = <10>;
0098 ti,debounce-tol = /bits/ 16 <3>;
0099 ti,debounce-rep = /bits/ 16 <1>;
0100 ti,settle-delay-usec = /bits/ 16 <150>;
0101 ti,keep-vref-on;
0102 wakeup-source;
0103 };
0104 };
0105
0106 &fec1 {
0107 pinctrl-names = "default";
0108 pinctrl-0 = <&pinctrl_fec1>;
0109 phy-mode = "rgmii";
0110 phy-handle = <ðphy>;
0111 phy-supply = <®_eth_phy>;
0112 fsl,magic-packet;
0113 status = "okay";
0114
0115 mdio {
0116 #address-cells = <1>;
0117 #size-cells = <0>;
0118
0119 ethphy: ethernet-phy@4 {
0120 compatible = "ethernet-phy-ieee802.3-c22";
0121 reg = <4>;
0122 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0123 reset-assert-us = <10000>;
0124 reset-deassert-us = <10000>;
0125 };
0126 };
0127 };
0128
0129 &i2c1 {
0130 clock-frequency = <400000>;
0131 pinctrl-names = "default";
0132 pinctrl-0 = <&pinctrl_i2c1>;
0133 status = "okay";
0134
0135 pmic@4b {
0136 compatible = "rohm,bd71847";
0137 reg = <0x4b>;
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_pmic>;
0140 interrupt-parent = <&gpio2>;
0141 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0142 rohm,reset-snvs-powered;
0143
0144 #clock-cells = <0>;
0145 clocks = <&osc_32k 0>;
0146 clock-output-names = "clk-32k-out";
0147
0148 regulators {
0149 buck1_reg: BUCK1 {
0150 regulator-name = "buck1";
0151 regulator-min-microvolt = <700000>;
0152 regulator-max-microvolt = <1300000>;
0153 regulator-boot-on;
0154 regulator-always-on;
0155 regulator-ramp-delay = <1250>;
0156 };
0157
0158 buck2_reg: BUCK2 {
0159 regulator-name = "buck2";
0160 regulator-min-microvolt = <700000>;
0161 regulator-max-microvolt = <1300000>;
0162 regulator-boot-on;
0163 regulator-always-on;
0164 regulator-ramp-delay = <1250>;
0165 rohm,dvs-run-voltage = <1000000>;
0166 rohm,dvs-idle-voltage = <900000>;
0167 };
0168
0169 buck3_reg: BUCK3 {
0170 regulator-name = "buck3";
0171 regulator-min-microvolt = <700000>;
0172 regulator-max-microvolt = <1350000>;
0173 regulator-boot-on;
0174 regulator-always-on;
0175 };
0176
0177 buck4_reg: BUCK4 {
0178 regulator-name = "buck4";
0179 regulator-min-microvolt = <3000000>;
0180 regulator-max-microvolt = <3300000>;
0181 regulator-boot-on;
0182 regulator-always-on;
0183 };
0184
0185 buck5_reg: BUCK5 {
0186 regulator-name = "buck5";
0187 regulator-min-microvolt = <1605000>;
0188 regulator-max-microvolt = <1995000>;
0189 regulator-boot-on;
0190 regulator-always-on;
0191 };
0192
0193 buck6_reg: BUCK6 {
0194 regulator-name = "buck6";
0195 regulator-min-microvolt = <800000>;
0196 regulator-max-microvolt = <1400000>;
0197 regulator-boot-on;
0198 regulator-always-on;
0199 };
0200
0201 ldo1_reg: LDO1 {
0202 regulator-name = "ldo1";
0203 regulator-min-microvolt = <1600000>;
0204 regulator-max-microvolt = <1900000>;
0205 regulator-boot-on;
0206 regulator-always-on;
0207 };
0208
0209 ldo2_reg: LDO2 {
0210 regulator-name = "ldo2";
0211 regulator-min-microvolt = <800000>;
0212 regulator-max-microvolt = <900000>;
0213 regulator-boot-on;
0214 regulator-always-on;
0215 };
0216
0217 ldo3_reg: LDO3 {
0218 regulator-name = "ldo3";
0219 regulator-min-microvolt = <1800000>;
0220 regulator-max-microvolt = <3300000>;
0221 regulator-boot-on;
0222 regulator-always-on;
0223 };
0224
0225 ldo4_reg: LDO4 {
0226 regulator-name = "ldo4";
0227 regulator-min-microvolt = <900000>;
0228 regulator-max-microvolt = <1800000>;
0229 regulator-boot-on;
0230 regulator-always-on;
0231 };
0232
0233 ldo5_reg: LDO5 {
0234 regulator-compatible = "ldo5";
0235 regulator-min-microvolt = <1800000>;
0236 regulator-max-microvolt = <1800000>;
0237 regulator-always-on;
0238 };
0239
0240 ldo6_reg: LDO6 {
0241 regulator-name = "ldo6";
0242 regulator-min-microvolt = <900000>;
0243 regulator-max-microvolt = <1800000>;
0244 regulator-boot-on;
0245 regulator-always-on;
0246 };
0247 };
0248 };
0249 };
0250
0251 &i2c3 {
0252 clock-frequency = <400000>;
0253 pinctrl-names = "default";
0254 pinctrl-0 = <&pinctrl_i2c3>;
0255 status = "okay";
0256
0257 /* TODO: configure audio, as of now just put a placeholder */
0258 wm8904: codec@1a {
0259 compatible = "wlf,wm8904";
0260 reg = <0x1a>;
0261 status = "disabled";
0262 };
0263 };
0264
0265 &snvs_pwrkey {
0266 status = "okay";
0267 };
0268
0269 /* Bluetooth */
0270 &uart2 {
0271 pinctrl-names = "default";
0272 pinctrl-0 = <&pinctrl_uart2>;
0273 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
0274 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0275 uart-has-rtscts;
0276 status = "okay";
0277 };
0278
0279 /* Console */
0280 &uart4 {
0281 pinctrl-names = "default";
0282 pinctrl-0 = <&pinctrl_uart4>;
0283 status = "okay";
0284 };
0285
0286 &usbotg1 {
0287 dr_mode = "otg";
0288 usb-role-switch;
0289 status = "okay";
0290 };
0291
0292 &usbotg2 {
0293 dr_mode = "otg";
0294 usb-role-switch;
0295 status = "okay";
0296 };
0297
0298 /* WIFI */
0299 &usdhc1 {
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0303 pinctrl-0 = <&pinctrl_usdhc1>;
0304 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0305 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0306 bus-width = <4>;
0307 non-removable;
0308 keep-power-in-suspend;
0309 status = "okay";
0310
0311 brcmf: bcrmf@1 {
0312 reg = <1>;
0313 compatible = "brcm,bcm4329-fmac";
0314 };
0315 };
0316
0317 /* SD */
0318 &usdhc2 {
0319 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
0320 assigned-clock-rates = <200000000>;
0321 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0322 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0323 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0324 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0325 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
0326 bus-width = <4>;
0327 vmmc-supply = <®_usdhc2_vmmc>;
0328 status = "okay";
0329 };
0330
0331 /* eMMC */
0332 &usdhc3 {
0333 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
0334 assigned-clock-rates = <400000000>;
0335 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0336 pinctrl-0 = <&pinctrl_usdhc3>;
0337 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0338 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0339 bus-width = <8>;
0340 non-removable;
0341 status = "okay";
0342 };
0343
0344 &wdog1 {
0345 pinctrl-names = "default";
0346 pinctrl-0 = <&pinctrl_wdog>;
0347 fsl,ext-reset-output;
0348 status = "okay";
0349 };
0350
0351 &iomuxc {
0352 pinctrl_ecspi1: ecspi1grp {
0353 fsl,pins = <
0354 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
0355 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
0356 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
0357 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
0358 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
0359 >;
0360 };
0361
0362 pinctrl_fec1: fec1grp {
0363 fsl,pins = <
0364 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0365 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0366 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0367 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0368 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0369 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0370 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0371 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0372 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0373 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0374 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0375 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0376 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0377 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0378 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0379 >;
0380 };
0381
0382 pinctrl_i2c1: i2c1grp {
0383 fsl,pins = <
0384 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0385 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0386 >;
0387 };
0388
0389 pinctrl_i2c3: i2c3grp {
0390 fsl,pins = <
0391 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0392 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0393 >;
0394 };
0395
0396 pinctrl_pmic: pmicirqgrp {
0397 fsl,pins = <
0398 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
0399 >;
0400 };
0401
0402 pinctrl_reg_eth_phy: regethphygrp {
0403 fsl,pins = <
0404 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
0405 >;
0406 };
0407
0408 pinctrl_restouch: restouchgrp {
0409 fsl,pins = <
0410 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
0411 >;
0412 };
0413
0414 pinctrl_uart2: uart2grp {
0415 fsl,pins = <
0416 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
0417 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
0418 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
0419 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
0420 >;
0421 };
0422
0423 pinctrl_uart4: uart4grp {
0424 fsl,pins = <
0425 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0426 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0427 >;
0428 };
0429
0430 pinctrl_usdhc1: usdhc1grp {
0431 fsl,pins = <
0432 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0433 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0434 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0435 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0436 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0437 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0438 >;
0439 };
0440
0441 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0442 fsl,pins = <
0443 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0444 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0445 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0446 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0447 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0448 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0449 >;
0450 };
0451
0452 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0453 fsl,pins = <
0454 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0455 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0456 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0457 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0458 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0459 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0460 >;
0461 };
0462
0463 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0464 fsl,pins = <
0465 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
0466 >;
0467 };
0468
0469 pinctrl_usdhc2: usdhc2grp {
0470 fsl,pins = <
0471 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0472 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0473 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0474 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0475 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0476 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0477 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0478 >;
0479 };
0480
0481 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0482 fsl,pins = <
0483 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0484 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0485 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0486 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0487 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0488 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0489 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0490 >;
0491 };
0492
0493 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0494 fsl,pins = <
0495 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0496 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0497 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0498 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0499 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0500 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0501 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0502 >;
0503 };
0504
0505 pinctrl_usdhc3: usdhc3grp {
0506 fsl,pins = <
0507 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0508 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0509 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0510 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0511 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0512 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0513 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0514 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0515 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0516 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0517 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0518 >;
0519 };
0520
0521 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0522 fsl,pins = <
0523 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0524 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0525 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0526 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0527 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0528 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0529 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0530 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0531 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0532 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0533 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0534 >;
0535 };
0536
0537 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0538 fsl,pins = <
0539 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0540 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0541 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0542 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0543 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0544 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0545 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0546 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0547 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0548 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0549 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0550 >;
0551 };
0552
0553 pinctrl_wdog: wdoggrp {
0554 fsl,pins = <
0555 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
0556 >;
0557 };
0558 };
