0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2020-2021 TQ-Systems GmbH
0004 */
0005
0006 #include <dt-bindings/phy/phy-imx8-pcie.h>
0007 #include "imx8mm.dtsi"
0008
0009 / {
0010 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
0011 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
0012
0013 memory@40000000 {
0014 device_type = "memory";
0015 /* our minimum RAM config will be 1024 MiB */
0016 reg = <0x00000000 0x40000000 0 0x40000000>;
0017 };
0018
0019 /* e-MMC IO, needed for HS modes */
0020 reg_vcc1v8: regulator-vcc1v8 {
0021 compatible = "regulator-fixed";
0022 regulator-name = "TQMA8MXML_VCC1V8";
0023 regulator-min-microvolt = <1800000>;
0024 regulator-max-microvolt = <1800000>;
0025 };
0026
0027 /* identical to buck4_reg, but should never change */
0028 reg_vcc3v3: regulator-vcc3v3 {
0029 compatible = "regulator-fixed";
0030 regulator-name = "TQMA8MXML_VCC3V3";
0031 regulator-min-microvolt = <3300000>;
0032 regulator-max-microvolt = <3300000>;
0033 };
0034
0035 reserved-memory {
0036 #address-cells = <2>;
0037 #size-cells = <2>;
0038 ranges;
0039
0040 /* global autoconfigured region for contiguous allocations */
0041 linux,cma {
0042 compatible = "shared-dma-pool";
0043 reusable;
0044 /* 640 MiB */
0045 size = <0 0x28000000>;
0046 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
0047 alloc-ranges = <0 0x40000000 0 0x78000000>;
0048 linux,cma-default;
0049 };
0050 };
0051 };
0052
0053 &A53_0 {
0054 cpu-supply = <&buck2_reg>;
0055 };
0056
0057 &flexspi {
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_flexspi>;
0060 status = "okay";
0061
0062 flash0: flash@0 {
0063 compatible = "jedec,spi-nor";
0064 reg = <0>;
0065 #address-cells = <1>;
0066 #size-cells = <1>;
0067 spi-max-frequency = <84000000>;
0068 spi-tx-bus-width = <1>;
0069 spi-rx-bus-width = <4>;
0070 };
0071 };
0072
0073 &gpu_2d {
0074 status = "okay";
0075 };
0076
0077 &gpu_3d {
0078 status = "okay";
0079 };
0080
0081 &i2c1 {
0082 clock-frequency = <100000>;
0083 pinctrl-names = "default", "gpio";
0084 pinctrl-0 = <&pinctrl_i2c1>;
0085 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0086 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0087 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0088 status = "okay";
0089
0090 sensor0: temperature-sensor-eeprom@1b {
0091 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0092 reg = <0x1b>;
0093 };
0094
0095 pca9450: pmic@25 {
0096 compatible = "nxp,pca9450a";
0097 reg = <0x25>;
0098
0099 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
0100 pinctrl-0 = <&pinctrl_pmic>;
0101 pinctrl-names = "default";
0102 interrupt-parent = <&gpio1>;
0103 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0104
0105 regulators {
0106 /* V_0V85_SOC: 0.85 */
0107 buck1_reg: BUCK1 {
0108 regulator-name = "BUCK1";
0109 regulator-min-microvolt = <850000>;
0110 regulator-max-microvolt = <850000>;
0111 regulator-boot-on;
0112 regulator-always-on;
0113 regulator-ramp-delay = <3125>;
0114 };
0115
0116 /* VDD_ARM */
0117 buck2_reg: BUCK2 {
0118 regulator-name = "BUCK2";
0119 regulator-min-microvolt = <850000>;
0120 regulator-max-microvolt = <1000000>;
0121 regulator-boot-on;
0122 regulator-always-on;
0123 nxp,dvs-run-voltage = <950000>;
0124 nxp,dvs-standby-voltage = <850000>;
0125 regulator-ramp-delay = <3125>;
0126 };
0127
0128 /* V_0V85_GPU / DRAM / VPU */
0129 buck3_reg: BUCK3 {
0130 regulator-name = "BUCK3";
0131 regulator-min-microvolt = <850000>;
0132 regulator-max-microvolt = <950000>;
0133 regulator-boot-on;
0134 regulator-always-on;
0135 regulator-ramp-delay = <3125>;
0136 };
0137
0138 /* VCC3V3 -> VMMC, ... must not be changed */
0139 buck4_reg: BUCK4 {
0140 regulator-name = "BUCK4";
0141 regulator-min-microvolt = <3300000>;
0142 regulator-max-microvolt = <3300000>;
0143 regulator-boot-on;
0144 regulator-always-on;
0145 };
0146
0147 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
0148 buck5_reg: BUCK5 {
0149 regulator-name = "BUCK5";
0150 regulator-min-microvolt = <1800000>;
0151 regulator-max-microvolt = <1800000>;
0152 regulator-boot-on;
0153 regulator-always-on;
0154 };
0155
0156 /* V_1V1 -> RAM, ... must not be changed */
0157 buck6_reg: BUCK6 {
0158 regulator-name = "BUCK6";
0159 regulator-min-microvolt = <1100000>;
0160 regulator-max-microvolt = <1100000>;
0161 regulator-boot-on;
0162 regulator-always-on;
0163 };
0164
0165 /* V_1V8_SNVS */
0166 ldo1_reg: LDO1 {
0167 regulator-name = "LDO1";
0168 regulator-min-microvolt = <1800000>;
0169 regulator-max-microvolt = <1800000>;
0170 regulator-boot-on;
0171 regulator-always-on;
0172 };
0173
0174 /* V_0V8_SNVS */
0175 ldo2_reg: LDO2 {
0176 regulator-name = "LDO2";
0177 regulator-min-microvolt = <800000>;
0178 regulator-max-microvolt = <850000>;
0179 regulator-boot-on;
0180 regulator-always-on;
0181 };
0182
0183 /* V_1V8_ANA */
0184 ldo3_reg: LDO3 {
0185 regulator-name = "LDO3";
0186 regulator-min-microvolt = <1800000>;
0187 regulator-max-microvolt = <1800000>;
0188 regulator-boot-on;
0189 regulator-always-on;
0190 };
0191
0192 /* V_0V9_MIPI */
0193 ldo4_reg: LDO4 {
0194 regulator-name = "LDO4";
0195 regulator-min-microvolt = <900000>;
0196 regulator-max-microvolt = <900000>;
0197 regulator-boot-on;
0198 regulator-always-on;
0199 };
0200
0201 /* VCC SD IO - switched using SD2 VSELECT */
0202 ldo5_reg: LDO5 {
0203 regulator-name = "LDO5";
0204 regulator-min-microvolt = <1800000>;
0205 regulator-max-microvolt = <3300000>;
0206 };
0207 };
0208 };
0209
0210
0211 pcf85063: rtc@51 {
0212 compatible = "nxp,pcf85063a";
0213 reg = <0x51>;
0214 quartz-load-femtofarads = <7000>;
0215 };
0216
0217 eeprom1: eeprom@53 {
0218 compatible = "nxp,se97b", "atmel,24c02";
0219 read-only;
0220 reg = <0x53>;
0221 pagesize = <16>;
0222 };
0223
0224 eeprom0: eeprom@57 {
0225 compatible = "atmel,24c64";
0226 reg = <0x57>;
0227 pagesize = <32>;
0228 };
0229 };
0230
0231 &pcie_phy {
0232 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0233 fsl,clkreq-unsupported;
0234 };
0235
0236 &usdhc3 {
0237 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0238 pinctrl-0 = <&pinctrl_usdhc3>;
0239 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0240 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0241 bus-width = <8>;
0242 non-removable;
0243 no-sd;
0244 no-sdio;
0245 vmmc-supply = <®_vcc3v3>;
0246 vqmmc-supply = <®_vcc1v8>;
0247 status = "okay";
0248 };
0249
0250 /*
0251 * Attention:
0252 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
0253 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
0254 */
0255 &wdog1 {
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&pinctrl_wdog>;
0258 fsl,ext-reset-output;
0259 status = "okay";
0260 };
0261
0262 &iomuxc {
0263 pinctrl_flexspi: flexspigrp {
0264 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
0265 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
0266 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
0267 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
0268 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
0269 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
0270 };
0271
0272 pinctrl_i2c1: i2c1grp {
0273 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
0274 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
0275 };
0276
0277 pinctrl_i2c1_gpio: i2c1gpiogrp {
0278 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
0279 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
0280 };
0281
0282 pinctrl_pmic: pmicgrp {
0283 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
0284 };
0285
0286 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0287 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
0288 };
0289
0290 pinctrl_usdhc3: usdhc3grp {
0291 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
0292 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0293 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0294 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0295 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0296 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0297 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0298 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0299 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0300 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0301 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0302 /* option USDHC3_RESET_B not defined, only in RM */
0303 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
0304 };
0305
0306 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0307 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
0308 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0309 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0310 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0311 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0312 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0313 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0314 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0315 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0316 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0317 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0318 /* option USDHC3_RESET_B not defined, only in RM */
0319 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
0320 };
0321
0322 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0323 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
0324 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0325 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0326 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0327 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0328 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0329 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0330 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0331 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0332 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0333 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0334 /* option USDHC3_RESET_B not defined, only in RM */
0335 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
0336 };
0337
0338 pinctrl_wdog: wdoggrp {
0339 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
0340 };
0341 };
