0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2020-2021 TQ-Systems GmbH
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mm-tqma8mqml.dtsi"
0009 #include "mba8mx.dtsi"
0010
0011 / {
0012 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
0013 compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
0014
0015 aliases {
0016 eeprom0 = &eeprom3;
0017 mmc0 = &usdhc3;
0018 mmc1 = &usdhc2;
0019 mmc2 = &usdhc1;
0020 rtc0 = &pcf85063;
0021 rtc1 = &snvs_rtc;
0022 };
0023
0024 reg_usdhc2_vmmc: regulator-vmmc {
0025 compatible = "regulator-fixed";
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0028 regulator-name = "VSD_3V3";
0029 regulator-min-microvolt = <3300000>;
0030 regulator-max-microvolt = <3300000>;
0031 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0032 enable-active-high;
0033 startup-delay-us = <100>;
0034 off-on-delay-us = <12000>;
0035 };
0036
0037 extcon_usbotg1: extcon-usbotg1 {
0038 compatible = "linux,extcon-usb-gpio";
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_usb1_extcon>;
0041 id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0042 };
0043 };
0044
0045 &i2c1 {
0046 expander2: gpio@27 {
0047 compatible = "nxp,pca9555";
0048 reg = <0x27>;
0049 gpio-controller;
0050 #gpio-cells = <2>;
0051 vcc-supply = <®_vcc_3v3>;
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_expander>;
0054 interrupt-parent = <&gpio1>;
0055 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
0056 interrupt-controller;
0057 #interrupt-cells = <2>;
0058 };
0059 };
0060
0061 &pcie_phy {
0062 clocks = <&pcie0_refclk>;
0063 status = "okay";
0064 };
0065
0066 &pcie0 {
0067 reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
0068 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0069 <&pcie0_refclk>;
0070 clock-names = "pcie", "pcie_aux", "pcie_bus";
0071 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0072 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0073 assigned-clock-rates = <10000000>, <250000000>;
0074 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0075 <&clk IMX8MM_SYS_PLL2_250M>;
0076 status = "okay";
0077 };
0078
0079 &sai3 {
0080 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
0081 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0082 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
0083 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
0084 <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
0085 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
0086 <&clk IMX8MM_AUDIO_PLL2_OUT>;
0087 };
0088
0089 &tlv320aic3x04 {
0090 clock-names = "mclk";
0091 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
0092 };
0093
0094 &uart1 {
0095 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
0096 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0097 };
0098
0099 &uart2 {
0100 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
0101 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0102 };
0103
0104 &usbotg1 {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_usbotg1>;
0107 dr_mode = "otg";
0108 extcon = <&extcon_usbotg1>;
0109 srp-disable;
0110 hnp-disable;
0111 adp-disable;
0112 power-active-high;
0113 over-current-active-low;
0114 status = "okay";
0115 };
0116
0117 &usbotg2 {
0118 dr_mode = "host";
0119 disable-over-current;
0120 vbus-supply = <®_hub_vbus>;
0121 status = "okay";
0122 };
0123
0124 &iomuxc {
0125 pinctrl_ecspi1: ecspi1grp {
0126 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>,
0127 <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000006>,
0128 <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x00000006>,
0129 <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00000006>;
0130 };
0131
0132 pinctrl_ecspi2: ecspi2grp {
0133 fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>,
0134 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x00000006>,
0135 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x00000006>,
0136 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000006>;
0137 };
0138
0139 pinctrl_expander: expandergrp {
0140 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>;
0141 };
0142
0143 pinctrl_fec1: fec1grp {
0144 fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>,
0145 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002>,
0146 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14>,
0147 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14>,
0148 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14>,
0149 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14>,
0150 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90>,
0151 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90>,
0152 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90>,
0153 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90>,
0154 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14>,
0155 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90>,
0156 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>,
0157 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>;
0158 };
0159
0160 pinctrl_gpiobutton: gpiobuttongrp {
0161 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>,
0162 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x84>,
0163 <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x84>;
0164 };
0165
0166 pinctrl_gpioled: gpioledgrp {
0167 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>,
0168 <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x84>;
0169 };
0170
0171 pinctrl_i2c2: i2c2grp {
0172 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>,
0173 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000004>;
0174 };
0175
0176 pinctrl_i2c2_gpio: i2c2gpiogrp {
0177 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>,
0178 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000004>;
0179 };
0180
0181 pinctrl_i2c3: i2c3grp {
0182 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>,
0183 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000004>;
0184 };
0185
0186 pinctrl_i2c3_gpio: i2c3gpiogrp {
0187 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>,
0188 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000004>;
0189 };
0190
0191 pinctrl_pwm3: pwm3grp {
0192 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>;
0193 };
0194
0195 pinctrl_pwm4: pwm4grp {
0196 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>;
0197 };
0198
0199 pinctrl_sai3: sai3grp {
0200 fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>,
0201 <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x94>,
0202 <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x94>,
0203 <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x94>,
0204 <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x94>,
0205 <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x94>,
0206 <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x94>;
0207 };
0208
0209 pinctrl_uart1: uart1grp {
0210 fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>,
0211 <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x16>;
0212 };
0213
0214 pinctrl_uart2: uart2grp {
0215 fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>,
0216 <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x16>;
0217 };
0218
0219 pinctrl_uart3: uart3grp {
0220 fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>,
0221 <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x16>;
0222 };
0223
0224 pinctrl_uart4: uart4grp {
0225 fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>,
0226 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x16>;
0227 };
0228
0229 pinctrl_usbotg1: usbotg1grp {
0230 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
0231 <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>;
0232 };
0233
0234 pinctrl_usb1_extcon: usb1-extcongrp {
0235 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
0236 };
0237
0238 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
0239 fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>;
0240 };
0241
0242 pinctrl_usdhc2: usdhc2grp {
0243 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
0244 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
0245 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
0246 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
0247 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
0248 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
0249 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
0250 };
0251
0252 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0253 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
0254 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
0255 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
0256 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
0257 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
0258 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
0259 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
0260 };
0261
0262 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0263 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
0264 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
0265 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
0266 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
0267 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
0268 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
0269 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
0270 };
0271 };
