0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 */
0006
0007 #include "imx8mm.dtsi"
0008 #include <dt-bindings/net/ti-dp83867.h>
0009
0010 / {
0011 model = "PHYTEC phyCORE-i.MX8MM";
0012 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
0013
0014 aliases {
0015 rtc0 = &rv3028;
0016 rtc1 = &snvs_rtc;
0017 };
0018
0019 memory@40000000 {
0020 device_type = "memory";
0021 reg = <0x0 0x40000000 0 0x80000000>;
0022 };
0023
0024 reg_vdd_3v3_s: regulator-vdd-3v3-s {
0025 compatible = "regulator-fixed";
0026 regulator-always-on;
0027 regulator-boot-on;
0028 regulator-max-microvolt = <3300000>;
0029 regulator-min-microvolt = <3300000>;
0030 regulator-name = "VDD_3V3_S";
0031 };
0032 };
0033
0034 &A53_0 {
0035 cpu-supply = <®_vdd_arm>;
0036 };
0037
0038 &A53_1 {
0039 cpu-supply = <®_vdd_arm>;
0040 };
0041
0042 &A53_2 {
0043 cpu-supply = <®_vdd_arm>;
0044 };
0045
0046 &A53_3 {
0047 cpu-supply = <®_vdd_arm>;
0048 };
0049
0050 &ddrc {
0051 operating-points-v2 = <&ddrc_opp_table>;
0052
0053 ddrc_opp_table: opp-table {
0054 compatible = "operating-points-v2";
0055
0056 opp-25M {
0057 opp-hz = /bits/ 64 <25000000>;
0058 };
0059
0060 opp-100M {
0061 opp-hz = /bits/ 64 <100000000>;
0062 };
0063
0064 opp-750M {
0065 opp-hz = /bits/ 64 <750000000>;
0066 };
0067 };
0068 };
0069
0070 /* Ethernet */
0071 &fec1 {
0072 fsl,magic-packet;
0073 phy-mode = "rgmii-id";
0074 phy-handle = <ðphy0>;
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_fec1>;
0077 status = "okay";
0078
0079 mdio {
0080 #address-cells = <1>;
0081 #size-cells = <0>;
0082
0083 ethphy0: ethernet-phy@0 {
0084 compatible = "ethernet-phy-ieee802.3-c22";
0085 enet-phy-lane-no-swap;
0086 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0087 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0088 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0089 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0090 reg = <0>;
0091 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
0092 reset-assert-us = <1000>;
0093 reset-deassert-us = <1000>;
0094 };
0095 };
0096 };
0097
0098 /* SPI Flash */
0099 &flexspi {
0100 pinctrl-names = "default";
0101 pinctrl-0 = <&pinctrl_flexspi0>;
0102 status = "okay";
0103
0104 som_flash: flash@0 {
0105 compatible = "jedec,spi-nor";
0106 reg = <0>;
0107 spi-max-frequency = <80000000>;
0108 spi-rx-bus-width = <4>;
0109 spi-tx-bus-width = <1>;
0110 };
0111 };
0112
0113 &gpio1 {
0114 gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
0115 "", "", "", "RESET_ETHPHY",
0116 "", "", "nENABLE_FLATLINK";
0117 };
0118
0119 /* I2C1 */
0120 &i2c1 {
0121 clock-frequency = <400000>;
0122 pinctrl-names = "default","gpio";
0123 pinctrl-0 = <&pinctrl_i2c1>;
0124 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0125 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0126 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0127 status = "okay";
0128
0129 pmic@8 {
0130 compatible = "nxp,pf8121a";
0131 reg = <0x08>;
0132
0133 regulators {
0134 reg_nvcc_sd1: ldo1 {
0135 regulator-always-on;
0136 regulator-boot-on;
0137 regulator-max-microvolt = <3300000>;
0138 regulator-min-microvolt = <3300000>;
0139 regulator-name = "NVCC_SD1 (LDO1)";
0140
0141 regulator-state-mem {
0142 regulator-off-in-suspend;
0143 };
0144 };
0145
0146 reg_nvcc_sd2: ldo2 {
0147 regulator-always-on;
0148 regulator-boot-on;
0149 regulator-max-microvolt = <3300000>;
0150 regulator-min-microvolt = <1800000>;
0151 regulator-name = "NVCC_SD2 (LDO2)";
0152 vselect-en;
0153
0154 regulator-state-mem {
0155 regulator-off-in-suspend;
0156 };
0157 };
0158
0159 reg_vcc_enet: ldo3 {
0160 regulator-always-on;
0161 regulator-boot-on;
0162 regulator-max-microvolt = <2500000>;
0163 regulator-min-microvolt = <1500000>;
0164 regulator-name = "VCC_ENET_2V5 (LDO3)";
0165
0166 regulator-state-mem {
0167 regulator-off-in-suspend;
0168 };
0169 };
0170
0171 reg_vdda_1v8: ldo4 {
0172 regulator-always-on;
0173 regulator-boot-on;
0174 regulator-max-microvolt = <1800000>;
0175 regulator-min-microvolt = <1500000>;
0176 regulator-name = "VDDA_1V8 (LDO4)";
0177
0178 regulator-state-mem {
0179 regulator-on-in-suspend;
0180 regulator-suspend-min-microvolt = <1500000>;
0181 regulator-suspend-max-microvolt = <1500000>;
0182 };
0183 };
0184
0185 reg_soc_vdda_phy: buck1 {
0186 regulator-always-on;
0187 regulator-boot-on;
0188 regulator-max-microvolt = <900000>;
0189 regulator-min-microvolt = <400000>;
0190 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
0191
0192 regulator-state-mem {
0193 regulator-on-in-suspend;
0194 regulator-suspend-min-microvolt = <400000>;
0195 regulator-suspend-max-microvolt = <400000>;
0196 };
0197 };
0198
0199 reg_vdd_gpu_dram: buck2 {
0200 regulator-always-on;
0201 regulator-boot-on;
0202 regulator-max-microvolt = <1000000>;
0203 regulator-min-microvolt = <1000000>;
0204 regulator-name = "VDD_GPU_DRAM (BUCK2)";
0205
0206 regulator-state-mem {
0207 regulator-on-in-suspend;
0208 regulator-suspend-max-microvolt = <1000000>;
0209 regulator-suspend-min-microvolt = <1000000>;
0210 };
0211 };
0212
0213 reg_vdd_gpu: buck3 {
0214 regulator-always-on;
0215 regulator-boot-on;
0216 regulator-max-microvolt = <1000000>;
0217 regulator-min-microvolt = <400000>;
0218 regulator-name = "VDD_VPU (BUCK3)";
0219
0220 regulator-state-mem {
0221 regulator-off-in-suspend;
0222 };
0223 };
0224
0225 reg_vdd_mipi: buck4 {
0226 regulator-always-on;
0227 regulator-boot-on;
0228 regulator-max-microvolt = <1050000>;
0229 regulator-min-microvolt = <900000>;
0230 regulator-name = "VDD_MIPI_0P9 (BUCK4)";
0231
0232 regulator-state-mem {
0233 regulator-off-in-suspend;
0234 };
0235 };
0236
0237 reg_vdd_arm: buck5 {
0238 regulator-always-on;
0239 regulator-boot-on;
0240 regulator-max-microvolt = <1050000>;
0241 regulator-min-microvolt = <400000>;
0242 regulator-name = "VDD_ARM (BUCK5)";
0243
0244 regulator-state-mem {
0245 regulator-off-in-suspend;
0246 };
0247 };
0248
0249 reg_vdd_1v8: buck6 {
0250 regulator-always-on;
0251 regulator-boot-on;
0252 regulator-max-microvolt = <1800000>;
0253 regulator-min-microvolt = <1800000>;
0254 regulator-name = "VDD_1V8 (BUCK6)";
0255
0256 regulator-state-mem {
0257 regulator-on-in-suspend;
0258 regulator-suspend-max-microvolt = <1800000>;
0259 regulator-suspend-min-microvolt = <1800000>;
0260 };
0261 };
0262
0263 reg_nvcc_dram: buck7 {
0264 regulator-always-on;
0265 regulator-boot-on;
0266 regulator-max-microvolt = <1100000>;
0267 regulator-min-microvolt = <1100000>;
0268 regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
0269 };
0270
0271 reg_vsnvs: vsnvs {
0272 regulator-always-on;
0273 regulator-boot-on;
0274 regulator-max-microvolt = <1800000>;
0275 regulator-min-microvolt = <1800000>;
0276 regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
0277 };
0278 };
0279 };
0280
0281 sn65dsi83: bridge@2d {
0282 compatible = "ti,sn65dsi83";
0283 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_sn65dsi83>;
0286 reg = <0x2d>;
0287 status = "disabled";
0288 };
0289
0290 eeprom@51 {
0291 compatible = "atmel,24c32";
0292 pagesize = <32>;
0293 reg = <0x51>;
0294 vcc-supply = <®_vdd_3v3_s>;
0295 };
0296
0297 rv3028: rtc@52 {
0298 compatible = "microcrystal,rv3028";
0299 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0300 interrupt-parent = <&gpio1>;
0301 pinctrl-names = "default";
0302 pinctrl-0 = <&pinctrl_rtc>;
0303 reg = <0x52>;
0304 };
0305 };
0306
0307 /* EMMC */
0308 &usdhc3 {
0309 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
0310 assigned-clock-rates = <400000000>;
0311 bus-width = <8>;
0312 keep-power-in-suspend;
0313 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0314 pinctrl-0 = <&pinctrl_usdhc3>;
0315 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0316 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0317 non-removable;
0318 status = "okay";
0319 };
0320
0321 /* Watchdog */
0322 &wdog1 {
0323 fsl,ext-reset-output;
0324 pinctrl-names = "default";
0325 pinctrl-0 = <&pinctrl_wdog>;
0326 status = "okay";
0327 };
0328
0329 &iomuxc {
0330 pinctrl_fec1: fec1grp {
0331 fsl,pins = <
0332 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
0333 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
0334 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
0335 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
0336 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
0337 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
0338 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
0339 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
0340 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
0341 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
0342 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
0343 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
0344 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
0345 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
0346 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
0347 >;
0348 };
0349
0350 pinctrl_flexspi0: flexspi0grp {
0351 fsl,pins = <
0352 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0353 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0354 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0355 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0356 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0357 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0358 >;
0359 };
0360
0361 pinctrl_i2c1: i2c1grp {
0362 fsl,pins = <
0363 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
0364 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
0365 >;
0366 };
0367
0368 pinctrl_i2c1_gpio: i2c1gpiogrp {
0369 fsl,pins = <
0370 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
0371 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
0372 >;
0373 };
0374
0375 pinctrl_rtc: rtcgrp {
0376 fsl,pins = <
0377 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
0378 >;
0379 };
0380
0381 pinctrl_sn65dsi83: sn65dsi83grp {
0382 fsl,pins = <
0383 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
0384 >;
0385 };
0386
0387 pinctrl_usdhc3: usdhc3grp {
0388 fsl,pins = <
0389 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0390 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0391 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0392 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0393 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0394 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0395 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0396 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0397 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0398 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0399 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0400 >;
0401 };
0402
0403 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0404 fsl,pins = <
0405 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0406 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0407 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0408 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0409 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0410 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0411 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0412 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0413 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0414 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0415 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0416 >;
0417 };
0418
0419 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0420 fsl,pins = <
0421 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0422 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0423 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0424 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0425 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0426 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0427 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0428 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0429 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0430 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0431 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0432 >;
0433 };
0434
0435 pinctrl_wdog: wdoggrp {
0436 fsl,pins = <
0437 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
0438 >;
0439 };
0440 };
