0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/phy/phy-imx8-pcie.h>
0012 #include "imx8mm-phycore-som.dtsi"
0013
0014 / {
0015 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
0016 compatible = "phytec,imx8mm-phyboard-polis-rdk",
0017 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
0018
0019 chosen {
0020 stdout-path = &uart3;
0021 };
0022
0023 bt_osc_32k: bt-lp-clock {
0024 compatible = "fixed-clock";
0025 clock-frequency = <32768>;
0026 clock-output-names = "bt_osc_32k";
0027 #clock-cells = <0>;
0028 };
0029
0030 can_osc_40m: can-clock {
0031 compatible = "fixed-clock";
0032 clock-frequency = <40000000>;
0033 clock-output-names = "can_osc_40m";
0034 #clock-cells = <0>;
0035 };
0036
0037 fan {
0038 compatible = "gpio-fan";
0039 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
0040 gpio-fan,speed-map = <0 0
0041 13000 1>;
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&pinctrl_fan>;
0044 #cooling-cells = <2>;
0045 };
0046
0047 leds {
0048 compatible = "gpio-leds";
0049 pinctrl-names = "default";
0050 pinctrl-0 = <&pinctrl_leds>;
0051
0052 led-0 {
0053 color = <LED_COLOR_ID_RED>;
0054 function = LED_FUNCTION_DISK;
0055 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
0056 linux,default-trigger = "mmc2";
0057 };
0058
0059 led-1 {
0060 color = <LED_COLOR_ID_BLUE>;
0061 function = LED_FUNCTION_DISK;
0062 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
0063 linux,default-trigger = "mmc1";
0064 };
0065
0066 led-2 {
0067 color = <LED_COLOR_ID_GREEN>;
0068 function = LED_FUNCTION_CPU;
0069 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
0070 linux,default-trigger = "heartbeat";
0071 };
0072 };
0073
0074 usdhc1_pwrseq: pwr-seq {
0075 compatible = "mmc-pwrseq-simple";
0076 post-power-on-delay-ms = <100>;
0077 power-off-delay-us = <60>;
0078 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
0079 };
0080
0081 reg_can_en: regulator-can-en {
0082 compatible = "regulator-fixed";
0083 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_can_en>;
0086 regulator-max-microvolt = <3300000>;
0087 regulator-min-microvolt = <3300000>;
0088 regulator-name = "CAN_EN";
0089 startup-delay-us = <20>;
0090 };
0091
0092 reg_usb_otg1_vbus: regulator-usb-otg1 {
0093 compatible = "regulator-fixed";
0094 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0095 enable-active-high;
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
0098 regulator-name = "usb_otg1_vbus";
0099 regulator-max-microvolt = <5000000>;
0100 regulator-min-microvolt = <5000000>;
0101 };
0102
0103 reg_usdhc2_vmmc: regulator-usdhc2 {
0104 compatible = "regulator-fixed";
0105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0106 enable-active-high;
0107 off-on-delay-us = <20000>;
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0110 regulator-max-microvolt = <3300000>;
0111 regulator-min-microvolt = <3300000>;
0112 regulator-name = "VSD_3V3";
0113 };
0114
0115 reg_vcc_3v3: regulator-vcc-3v3 {
0116 compatible = "regulator-fixed";
0117 regulator-max-microvolt = <3300000>;
0118 regulator-min-microvolt = <3300000>;
0119 regulator-name = "VCC_3V3";
0120 };
0121 };
0122
0123 /* SPI - CAN MCP251XFD */
0124 &ecspi1 {
0125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0126 pinctrl-names = "default";
0127 pinctrl-0 = <&pinctrl_ecspi1>;
0128 status = "okay";
0129
0130 can0: can@0 {
0131 compatible = "microchip,mcp251xfd";
0132 clocks = <&can_osc_40m>;
0133 interrupt-parent = <&gpio1>;
0134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&pinctrl_can_int>;
0137 reg = <0>;
0138 spi-max-frequency = <20000000>;
0139 xceiver-supply = <®_can_en>;
0140 };
0141 };
0142
0143 &gpio1 {
0144 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
0145 "", "", "", "RESET_ETHPHY",
0146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
0147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
0148 };
0149
0150 &gpio2 {
0151 gpio-line-names = "", "", "", "",
0152 "", "", "BT_REG_ON", "WL_REG_ON",
0153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
0154 "X_SD2_CD_B", "", "", "",
0155 "", "", "", "SD2_RESET_B";
0156 };
0157
0158 &gpio4 {
0159 gpio-line-names = "", "", "", "",
0160 "", "", "", "",
0161 "FAN", "miniPCIe_nPERST", "", "",
0162 "COEX1", "COEX2";
0163 };
0164
0165 &gpio5 {
0166 gpio-line-names = "", "", "", "",
0167 "", "", "", "",
0168 "", "ECSPI1_SS0";
0169 };
0170
0171 /* PCIe */
0172 &pcie0 {
0173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0174 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0176 <&clk IMX8MM_SYS_PLL2_250M>;
0177 assigned-clock-rates = <10000000>, <250000000>;
0178 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0179 <&clk IMX8MM_CLK_PCIE1_PHY>;
0180 clock-names = "pcie", "pcie_aux", "pcie_bus";
0181 pinctrl-names = "default";
0182 pinctrl-0 = <&pinctrl_pcie>;
0183 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
0184 status = "okay";
0185 };
0186
0187 &pcie_phy {
0188 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
0189 fsl,clkreq-unsupported;
0190 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
0191 fsl,tx-deemph-gen1 = <0x2d>;
0192 fsl,tx-deemph-gen2 = <0xf>;
0193 status = "okay";
0194 };
0195
0196 &rv3028 {
0197 trickle-resistor-ohms = <3000>;
0198 };
0199
0200 &snvs_pwrkey {
0201 status = "okay";
0202 };
0203
0204 /* UART - RS232/RS485 */
0205 &uart1 {
0206 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
0207 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&pinctrl_uart1>;
0210 uart-has-rtscts;
0211 status = "okay";
0212 };
0213
0214 /* UART - Sterling-LWB Bluetooth */
0215 &uart2 {
0216 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
0217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0218 fsl,dte-mode;
0219 pinctrl-names = "default";
0220 pinctrl-0 = <&pinctrl_uart2_bt>;
0221 uart-has-rtscts;
0222 status = "okay";
0223
0224 bluetooth {
0225 compatible = "brcm,bcm43438-bt";
0226 clocks = <&bt_osc_32k>;
0227 clock-names = "lpo";
0228 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
0229 interrupt-names = "host-wakeup";
0230 interrupt-parent = <&gpio2>;
0231 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
0232 max-speed = <2000000>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_bt>;
0235 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
0236 vddio-supply = <®_vcc_3v3>;
0237 };
0238 };
0239
0240 /* UART - console */
0241 &uart3 {
0242 pinctrl-names = "default";
0243 pinctrl-0 = <&pinctrl_uart3>;
0244 status = "okay";
0245 };
0246
0247 /* USB */
0248 &usbotg1 {
0249 adp-disable;
0250 dr_mode = "otg";
0251 over-current-active-low;
0252 samsung,picophy-pre-emp-curr-control = <3>;
0253 samsung,picophy-dc-vol-level-adjust = <7>;
0254 srp-disable;
0255 vbus-supply = <®_usb_otg1_vbus>;
0256 status = "okay";
0257 };
0258
0259 &usbotg2 {
0260 disable-over-current;
0261 dr_mode = "host";
0262 samsung,picophy-pre-emp-curr-control = <3>;
0263 samsung,picophy-dc-vol-level-adjust = <7>;
0264 status = "okay";
0265 };
0266
0267 /* SDIO - Sterling-LWB Wifi */
0268 &usdhc1 {
0269 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
0270 assigned-clock-rates = <200000000>;
0271 bus-width = <4>;
0272 mmc-pwrseq = <&usdhc1_pwrseq>;
0273 non-removable;
0274 no-1-8-v;
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
0277 #address-cells = <1>;
0278 #size-cells = <0>;
0279 status = "okay";
0280
0281 brcmf: wifi@1 {
0282 compatible = "brcm,bcm4329-fmac";
0283 reg = <1>;
0284 };
0285 };
0286
0287 /* SD-Card */
0288 &usdhc2 {
0289 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
0290 assigned-clock-rates = <200000000>;
0291 bus-width = <4>;
0292 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0293 disable-wp;
0294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0295 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0296 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0297 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0298 vmmc-supply = <®_usdhc2_vmmc>;
0299 vqmmc-supply = <®_nvcc_sd2>;
0300 status = "okay";
0301 };
0302
0303 &iomuxc {
0304 pinctrl_bt: btgrp {
0305 fsl,pins = <
0306 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
0307 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
0308 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
0309 >;
0310 };
0311
0312 pinctrl_can_en: can-engrp {
0313 fsl,pins = <
0314 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
0315 >;
0316 };
0317
0318 pinctrl_can_int: can-intgrp {
0319 fsl,pins = <
0320 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
0321 >;
0322 };
0323
0324 pinctrl_ecspi1: ecspi1grp {
0325 fsl,pins = <
0326 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
0327 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
0328 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
0329 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
0330 >;
0331 };
0332
0333 pinctrl_fan: fan0grp {
0334 fsl,pins = <
0335 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
0336 >;
0337 };
0338
0339 pinctrl_leds: leds1grp {
0340 fsl,pins = <
0341 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
0342 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
0343 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
0344 >;
0345 };
0346
0347 pinctrl_pcie: pciegrp {
0348 fsl,pins = <
0349 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
0350 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
0351 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
0352 >;
0353 };
0354
0355 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0356 fsl,pins = <
0357 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
0358 >;
0359 };
0360
0361 pinctrl_uart1: uart1grp {
0362 fsl,pins = <
0363 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
0364 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
0365 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
0366 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
0367 >;
0368 };
0369
0370 pinctrl_uart2_bt: uart2btgrp {
0371 fsl,pins = <
0372 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
0373 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
0374 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
0375 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
0376 >;
0377 };
0378
0379 pinctrl_uart3: uart3grp {
0380 fsl,pins = <
0381 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
0382 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
0383 >;
0384 };
0385
0386 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
0387 fsl,pins = <
0388 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
0389 >;
0390 };
0391
0392 pinctrl_usdhc1: usdhc1grp {
0393 fsl,pins = <
0394 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
0395 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
0396 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
0397 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
0398 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
0399 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
0400 >;
0401 };
0402
0403 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0404 fsl,pins = <
0405 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
0406 >;
0407 };
0408
0409 pinctrl_usdhc2: usdhc2grp {
0410 fsl,pins = <
0411 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0412 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
0413 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
0414 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
0415 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
0416 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
0417 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
0418 >;
0419 };
0420
0421 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0422 fsl,pins = <
0423 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0424 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0425 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0426 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0427 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0428 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0429 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0430 >;
0431 };
0432
0433 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0434 fsl,pins = <
0435 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0436 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0437 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0438 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0439 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0440 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0441 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0442 >;
0443 };
0444
0445 pinctrl_wlan: wlangrp {
0446 fsl,pins = <
0447 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
0448 >;
0449 };
0450 };
