0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board.
0004 * Adrien Grassein <adrien.grassein@gmail.com.com>
0005 */
0006 /dts-v1/;
0007 #include "imx8mm.dtsi"
0008
0009 / {
0010 model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
0011 compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
0012
0013 reg_vref_1v8: regulator-vref-1v8 {
0014 compatible = "regulator-fixed";
0015 regulator-name = "vref-1v8";
0016 regulator-min-microvolt = <1800000>;
0017 regulator-max-microvolt = <1800000>;
0018 };
0019
0020 reg_vref_3v3: regulator-vref-3v3 {
0021 compatible = "regulator-fixed";
0022 regulator-name = "vref-3v3";
0023 regulator-min-microvolt = <3300000>;
0024 regulator-max-microvolt = <3300000>;
0025 };
0026
0027 reg_wlan_vmmc: regulator-wlan-vmmc {
0028 compatible = "regulator-fixed";
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
0031 regulator-name = "reg_wlan_vmmc";
0032 regulator-min-microvolt = <3300000>;
0033 regulator-max-microvolt = <3300000>;
0034 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
0035 enable-active-high;
0036 };
0037
0038 sound-wm8960 {
0039 audio-cpu = <&sai1>;
0040 audio-codec = <&wm8960>;
0041 audio-routing =
0042 "Headphone Jack", "HP_L",
0043 "Headphone Jack", "HP_R",
0044 "Ext Spk", "SPK_LP",
0045 "Ext Spk", "SPK_LN",
0046 "Ext Spk", "SPK_RP",
0047 "Ext Spk", "SPK_RN",
0048 "RINPUT1", "Mic Jack",
0049 "Mic Jack", "MICB";
0050 compatible = "fsl,imx-audio-wm8960";
0051 /* JD2: hp detect high for headphone*/
0052 hp-det-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0053 /* Jack is not stuffed */
0054 mic-det-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0055 model = "wm8960-audio";
0056 pinctrl-names = "default";
0057 pinctrl-0 = <&pinctrl_sound_wm8960>;
0058 };
0059 };
0060
0061 &A53_0 {
0062 cpu-supply = <®_buck3>;
0063 };
0064
0065 &A53_1 {
0066 cpu-supply = <®_buck3>;
0067 };
0068
0069 &A53_2 {
0070 cpu-supply = <®_buck3>;
0071 };
0072
0073 &A53_3 {
0074 cpu-supply = <®_buck3>;
0075 };
0076
0077 /* J15 */
0078 &ecspi2 {
0079 assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
0080 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
0081 assigned-clock-rates = <40000000>;
0082 pinctrl-names = "default";
0083 pinctrl-0 = <&pinctrl_ecspi2>;
0084 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0085 status = "okay";
0086 };
0087
0088 &fec1 {
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_fec1>;
0091 phy-mode = "rgmii-id";
0092 phy-handle = <ðphy0>;
0093 fsl,magic-packet;
0094 status = "okay";
0095
0096 mdio {
0097 #address-cells = <1>;
0098 #size-cells = <0>;
0099
0100 ethphy0: ethernet-phy@4 {
0101 compatible = "ethernet-phy-ieee802.3-c22";
0102 reg = <4>;
0103 interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>;
0104 };
0105 };
0106 };
0107
0108 &flexspi {
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_flexspi>;
0111 status = "okay";
0112 };
0113
0114 &i2c1 {
0115 clock-frequency = <100000>;
0116 pinctrl-names = "default";
0117 pinctrl-0 = <&pinctrl_i2c1>;
0118 status = "okay";
0119
0120 pmic@8 {
0121 compatible = "nxp,pf8121a";
0122 reg = <0x8>;
0123
0124 regulators {
0125 reg_ldo1: ldo1 {
0126 regulator-min-microvolt = <1500000>;
0127 regulator-max-microvolt = <5000000>;
0128 regulator-boot-on;
0129 regulator-always-on;
0130 };
0131
0132 reg_ldo2: ldo2 {
0133 regulator-min-microvolt = <1500000>;
0134 regulator-max-microvolt = <5000000>;
0135 regulator-boot-on;
0136 regulator-always-on;
0137 };
0138
0139 reg_ldo3: ldo3 {
0140 regulator-min-microvolt = <1500000>;
0141 regulator-max-microvolt = <5000000>;
0142 regulator-boot-on;
0143 regulator-always-on;
0144 };
0145
0146 reg_ldo4: ldo4 {
0147 regulator-min-microvolt = <1500000>;
0148 regulator-max-microvolt = <5000000>;
0149 regulator-boot-on;
0150 regulator-always-on;
0151 };
0152
0153 reg_buck1: buck1 {
0154 regulator-min-microvolt = <400000>;
0155 regulator-max-microvolt = <1800000>;
0156 regulator-boot-on;
0157 regulator-always-on;
0158 };
0159
0160 reg_buck2: buck2 {
0161 regulator-min-microvolt = <400000>;
0162 regulator-max-microvolt = <1800000>;
0163 regulator-boot-on;
0164 regulator-always-on;
0165 };
0166
0167 reg_buck3: buck3 {
0168 regulator-min-microvolt = <400000>;
0169 regulator-max-microvolt = <1800000>;
0170 regulator-boot-on;
0171 regulator-always-on;
0172 };
0173
0174 reg_buck4: buck4 {
0175 regulator-min-microvolt = <400000>;
0176 regulator-max-microvolt = <1800000>;
0177 regulator-boot-on;
0178 regulator-always-on;
0179 };
0180
0181 reg_buck5: buck5 {
0182 regulator-min-microvolt = <400000>;
0183 regulator-max-microvolt = <1800000>;
0184 regulator-boot-on;
0185 regulator-always-on;
0186 };
0187
0188 reg_buck6: buck6 {
0189 regulator-min-microvolt = <400000>;
0190 regulator-max-microvolt = <1800000>;
0191 regulator-boot-on;
0192 regulator-always-on;
0193 };
0194
0195 reg_buck7: buck7 {
0196 regulator-min-microvolt = <3300000>;
0197 regulator-max-microvolt = <3300000>;
0198 regulator-boot-on;
0199 regulator-always-on;
0200 };
0201
0202 reg_vsnvs: vsnvs {
0203 regulator-min-microvolt = <1800000>;
0204 regulator-max-microvolt = <3300000>;
0205 regulator-boot-on;
0206 };
0207 };
0208 };
0209 };
0210
0211 &i2c3 {
0212 clock-frequency = <100000>;
0213 pinctrl-names = "default";
0214 pinctrl-0 = <&pinctrl_i2c3>;
0215 status = "okay";
0216
0217 i2cmux@70 {
0218 compatible = "nxp,pca9540";
0219 reg = <0x70>;
0220 #address-cells = <1>;
0221 #size-cells = <0>;
0222
0223 i2c3@0 {
0224 reg = <0>;
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227
0228 rtc@68 {
0229 compatible = "microcrystal,rv4162";
0230 reg = <0x68>;
0231 pinctrl-names = "default";
0232 pinctrl-0 = <&pinctrl_i2c3a_rv4162>;
0233 interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>;
0234 wakeup-source;
0235 };
0236 };
0237 };
0238 };
0239
0240 &i2c4 {
0241 clock-frequency = <100000>;
0242 pinctrl-names = "default";
0243 pinctrl-0 = <&pinctrl_i2c4>;
0244 status = "okay";
0245
0246 wm8960: codec@1a {
0247 compatible = "wlf,wm8960";
0248 reg = <0x1a>;
0249 clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
0250 clock-names = "mclk1";
0251 wlf,shared-lrclk;
0252 #sound-dai-cells = <0>;
0253 };
0254 };
0255
0256 &pwm1 {
0257 pinctrl-names = "default";
0258 pinctrl-0 = <&pinctrl_pwm1>;
0259 status = "okay";
0260 };
0261
0262 &pwm2 {
0263 assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
0264 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
0265 assigned-clock-rates = <40000000>;
0266 pinctrl-names = "default";
0267 pinctrl-0 = <&pinctrl_pwm2>;
0268 status = "okay";
0269 };
0270
0271 &pwm3 {
0272 pinctrl-names = "default";
0273 pinctrl-0 = <&pinctrl_pwm3>;
0274 status = "okay";
0275 };
0276
0277 &pwm4 {
0278 pinctrl-names = "default";
0279 pinctrl-0 = <&pinctrl_pwm4>;
0280 status = "okay";
0281 };
0282
0283 &sai1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_sai1>;
0286 status = "okay";
0287 };
0288
0289 &sai2 {
0290 pinctrl-names = "default";
0291 pinctrl-0 = <&pinctrl_sai2>;
0292 status = "okay";
0293 };
0294
0295 /* BT */
0296 &uart1 {
0297 pinctrl-names = "default";
0298 pinctrl-0 = <&pinctrl_uart1>;
0299 uart-has-rtscts;
0300 status = "okay";
0301 };
0302
0303 /* console */
0304 &uart2 {
0305 pinctrl-names = "default";
0306 pinctrl-0 = <&pinctrl_uart2>;
0307 status = "okay";
0308 };
0309
0310 /* J15 */
0311 &uart3 {
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&pinctrl_uart3>;
0314 uart-has-rtscts;
0315 status = "okay";
0316 };
0317
0318 /* J9 */
0319 &uart4 {
0320 pinctrl-names = "default";
0321 pinctrl-0 = <&pinctrl_uart4>;
0322 status = "okay";
0323 };
0324
0325 /* eMMC */
0326 &usdhc1 {
0327 bus-width = <8>;
0328 sdhci-caps-mask = <0x80000000 0x0>;
0329 non-removable;
0330 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0331 pinctrl-0 = <&pinctrl_usdhc1>;
0332 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0333 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0334 vmmc-supply = <®_vref_3v3>;
0335 vqmmc-supply = <®_vref_1v8>;
0336 status = "okay";
0337 };
0338
0339 /* sdcard */
0340 &usdhc2 {
0341 bus-width = <4>;
0342 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0343 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0344 pinctrl-0 = <&pinctrl_usdhc2>;
0345 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0346 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0347 vqmmc-supply = <®_ldo2>;
0348 status = "okay";
0349 };
0350
0351 /* wlan */
0352 &usdhc3 {
0353 bus-width = <4>;
0354 sdhci-caps-mask = <0x2 0x0>;
0355 non-removable;
0356 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0357 pinctrl-0 = <&pinctrl_usdhc3>;
0358 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0359 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0360 vmmc-supply = <®_wlan_vmmc>;
0361 vqmmc-supply = <®_vref_1v8>;
0362 status = "okay";
0363 };
0364
0365 /* USB OTG port */
0366 &usbotg1 {
0367 dr_mode = "otg";
0368 over-current-active-low;
0369 pinctrl-names = "default";
0370 pinctrl-0 = <&pinctrl_usbotg1>;
0371 power-active-high;
0372 status = "okay";
0373 };
0374
0375 /* USB Host port */
0376 &usbotg2 {
0377 dr_mode = "host";
0378 over-current-active-low;
0379 pinctrl-names = "default";
0380 pinctrl-0 = <&pinctrl_usbotg2>;
0381 power-active-high;
0382 /*
0383 * FIXME: having USB2 enabled hangs the boot just after:
0384 *[ 1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller
0385 *[ 1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2
0386 *[ 1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
0387 *[ 1.687730] hub 2-0:1.0: USB hub found
0388 *[ 1.691528] hub 2-0:1.0: 1 port detected
0389 */
0390 status = "disabled";
0391 };
0392
0393 &wdog1 {
0394 pinctrl-names = "default";
0395 pinctrl-0 = <&pinctrl_wdog>;
0396 fsl,ext-reset-output;
0397 status = "okay";
0398 };
0399
0400 &iomuxc {
0401 pinctrl-names = "default";
0402 pinctrl-0 = <&pinctrl_hog>;
0403
0404 pinctrl_ecspi2: ecspi2grp {
0405 fsl,pins = <
0406 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
0407 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
0408 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
0409 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
0410 >;
0411 };
0412
0413 pinctrl_fec1: fec1grp {
0414 fsl,pins = <
0415 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0416 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0417 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0418 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0419 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0420 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0421 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0422 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0423 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0424 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0425 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0426 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0427 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0428 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0429 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159
0430 >;
0431 };
0432
0433 pinctrl_flexspi: flexspigrp {
0434 fsl,pins = <
0435 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0436 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0437 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0438 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0439 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0440 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0441 >;
0442 };
0443
0444 pinctrl_hog: hoggrp {
0445 fsl,pins = <
0446 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
0447 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09
0448 >;
0449 };
0450
0451 pinctrl_i2c1: i2c1grp {
0452 fsl,pins = <
0453 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0454 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0455 >;
0456 };
0457
0458 pinctrl_i2c3: i2c3grp {
0459 fsl,pins = <
0460 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0461 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0462 >;
0463 };
0464
0465 pinctrl_i2c4: i2c4grp {
0466 fsl,pins = <
0467 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
0468 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
0469 >;
0470 };
0471
0472 pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {
0473 fsl,pins = <
0474 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
0475 >;
0476 };
0477
0478 pinctrl_pwm1: pwm1grp {
0479 fsl,pins = <
0480 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
0481 >;
0482 };
0483
0484 pinctrl_pwm2: pwm2grp {
0485 fsl,pins = <
0486 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
0487 >;
0488 };
0489
0490 pinctrl_pwm3: pwm3grp {
0491 fsl,pins = <
0492 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
0493 >;
0494 };
0495
0496 pinctrl_pwm4: pwm4grp {
0497 fsl,pins = <
0498 MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
0499 >;
0500 };
0501
0502 pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
0503 fsl,pins = <
0504 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
0505 >;
0506 };
0507
0508 pinctrl_sai1: sai1grp {
0509 fsl,pins = <
0510 /* wm8960 */
0511 MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
0512 MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
0513 MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
0514 MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
0515 MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
0516 >;
0517 };
0518
0519 pinctrl_sai2: sai2grp {
0520 fsl,pins = <
0521 /* Bluetooth PCM */
0522 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
0523 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
0524 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
0525 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
0526 >;
0527 };
0528
0529 pinctrl_sound_wm8960: sound-wm8960grp {
0530 fsl,pins = <
0531 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x80
0532 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x80
0533 >;
0534 };
0535
0536 pinctrl_uart1: uart1grp {
0537 fsl,pins = <
0538 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0539 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0540 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
0541 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
0542 >;
0543 };
0544
0545 pinctrl_uart2: uart2grp {
0546 fsl,pins = <
0547 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0548 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0549 >;
0550 };
0551
0552 pinctrl_uart3: uart3grp {
0553 fsl,pins = <
0554 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
0555 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
0556 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
0557 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
0558 >;
0559 };
0560
0561 pinctrl_uart4: uart4grp {
0562 fsl,pins = <
0563 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0564 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0565 >;
0566 };
0567
0568 pinctrl_usbotg1: usbotg1grp {
0569 fsl,pins = <
0570 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16
0571 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156
0572 >;
0573 };
0574
0575 pinctrl_usbotg2: usbotg2grp {
0576 fsl,pins = <
0577 MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
0578 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x15
0579 >;
0580 };
0581
0582 pinctrl_usdhc1: usdhc1grp {
0583 fsl,pins = <
0584 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0585 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0586 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0587 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0588 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0589 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0590 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
0591 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
0592 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
0593 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
0594 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x141
0595 >;
0596 };
0597
0598 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
0599 fsl,pins = <
0600 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0601 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0602 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0603 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0604 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0605 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0606 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
0607 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
0608 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
0609 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
0610 >;
0611 };
0612
0613 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
0614 fsl,pins = <
0615 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0616 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0617 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0618 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0619 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0620 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0621 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
0622 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
0623 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
0624 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
0625 >;
0626 };
0627
0628 pinctrl_usdhc2: usdhc2grp {
0629 fsl,pins = <
0630 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0631 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0632 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0633 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0634 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0635 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0636 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
0637 >;
0638 };
0639
0640 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
0641 fsl,pins = <
0642 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0643 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0644 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0645 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0646 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0647 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0648 >;
0649 };
0650
0651 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
0652 fsl,pins = <
0653 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0654 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0655 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0656 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0657 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0658 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0659 >;
0660 };
0661
0662 pinctrl_usdhc3: usdhc3grp {
0663 fsl,pins = <
0664 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0665 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0666 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0667 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0668 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0669 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0670 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
0671 >;
0672 };
0673
0674 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
0675 fsl,pins = <
0676 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0677 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0678 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0679 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0680 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0681 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0682 >;
0683 };
0684
0685 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
0686 fsl,pins = <
0687 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0688 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0689 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0690 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0691 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0692 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0693 >;
0694 };
0695
0696 pinctrl_wdog: wdoggrp {
0697 fsl,pins = <
0698 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
0699 >;
0700 };
0701 };
