0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 /*
0003 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mm-verdin.dtsi"
0009
0010 / {
0011 model = "MENLO MX8MM EMBEDDED DEVICE";
0012 compatible = "menlo,mx8menlo",
0013 "toradex,verdin-imx8mm",
0014 "fsl,imx8mm";
0015
0016 /delete-node/ gpio-keys;
0017
0018 leds {
0019 compatible = "gpio-leds";
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_led>;
0022
0023 led-1 {
0024 label = "TestLed601";
0025 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
0026 linux,default-trigger = "mmc0";
0027 };
0028
0029 led-2 {
0030 label = "TestLed602";
0031 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
0032 linux,default-trigger = "heartbeat";
0033 };
0034 };
0035
0036 beeper {
0037 compatible = "gpio-beeper";
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&pinctrl_beeper>;
0040 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
0041 };
0042
0043 /* Fixed clock dedicated to SPI CAN on carrier board */
0044 clk_xtal20: clk-xtal20 {
0045 compatible = "fixed-clock";
0046 #clock-cells = <0>;
0047 clock-frequency = <20000000>;
0048 };
0049 };
0050
0051 &ecspi1 {
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&pinctrl_ecspi1>;
0056 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0057 status = "okay";
0058
0059 /* CAN controller on the baseboard */
0060 canfd: can@0 {
0061 compatible = "microchip,mcp2518fd";
0062 clocks = <&clk_xtal20>;
0063 interrupt-parent = <&gpio1>;
0064 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
0065 reg = <0>;
0066 spi-max-frequency = <2000000>;
0067 };
0068
0069 };
0070
0071 &ecspi2 {
0072 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
0073 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
0074 status = "okay";
0075
0076 spidev@0 {
0077 compatible = "menlo,m53cpld";
0078 reg = <0>;
0079 spi-max-frequency = <25000000>;
0080 };
0081
0082 spidev@1 {
0083 compatible = "menlo,m53cpld";
0084 reg = <1>;
0085 spi-max-frequency = <25000000>;
0086 };
0087
0088 };
0089
0090 ðphy0 {
0091 max-speed = <100>;
0092 };
0093
0094 &fec1 {
0095 status = "okay";
0096 };
0097
0098 &flexspi {
0099 status = "okay";
0100
0101 flash@0 {
0102 reg = <0>;
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 compatible = "jedec,spi-nor";
0106 spi-max-frequency = <66000000>;
0107 spi-rx-bus-width = <4>;
0108 spi-tx-bus-width = <4>;
0109 };
0110 };
0111
0112 &gpio1 {
0113 gpio-line-names =
0114 "", "", "", "",
0115 "", "", "", "",
0116 "", "", "", "",
0117 "", "", "", "",
0118 "", "", "", "",
0119 "", "", "", "",
0120 "", "", "", "",
0121 "", "", "", "";
0122 };
0123
0124 &gpio2 {
0125 gpio-line-names =
0126 "", "", "", "",
0127 "", "", "", "",
0128 "", "", "", "",
0129 "", "", "", "",
0130 "", "", "", "",
0131 "", "", "", "",
0132 "", "", "", "",
0133 "", "", "", "";
0134 };
0135
0136 &gpio3 {
0137 gpio-line-names =
0138 "", "", "", "",
0139 "", "", "", "",
0140 "", "", "", "",
0141 "", "", "", "",
0142 "", "", "", "",
0143 "", "", "DISP_reset", "KBD_intI",
0144 "", "", "", "",
0145 "", "", "", "";
0146 };
0147
0148 &gpio4 {
0149 /*
0150 * CPLD_D[n] is ARM_CPLD[n] in schematic
0151 * CPLD_int is SA_INTERRUPT in schematic
0152 * CPLD_reset is RESET_SOFT in schematic
0153 */
0154 gpio-line-names =
0155 "CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
0156 "", "CPLD_D[7]", "", "",
0157 "", "", "", "CPLD_D[5]",
0158 "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
0159 "CPLD_D[0]", "", "", "",
0160 "", "", "", "",
0161 "", "", "", "KBD_intK",
0162 "", "", "", "";
0163 };
0164
0165 &gpio5 {
0166 gpio-line-names =
0167 "", "", "", "",
0168 "", "", "", "",
0169 "", "", "", "",
0170 "", "", "", "",
0171 "", "", "", "",
0172 "", "", "", "",
0173 "", "", "", "",
0174 "", "", "", "";
0175 };
0176
0177 &gpio_expander_21 {
0178 status = "okay";
0179 };
0180
0181 &hwmon {
0182 status = "okay";
0183 };
0184
0185 &i2c3 {
0186 status = "okay";
0187 };
0188
0189 &i2c4 {
0190 /* None of this is present on the SoM. */
0191 /delete-node/ bridge@2c;
0192 /delete-node/ hdmi@48;
0193 /delete-node/ touch@4a;
0194 /delete-node/ sensor@4f;
0195 /delete-node/ eeprom@50;
0196 /delete-node/ eeprom@57;
0197 };
0198
0199 &iomuxc {
0200 pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
0201 <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
0202
0203 pinctrl_beeper: beepergrp {
0204 fsl,pins = <
0205 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
0206 >;
0207 };
0208
0209 pinctrl_ecspi1: ecspi1grp {
0210 fsl,pins = <
0211 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
0212 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
0213 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
0214 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
0215 >;
0216 };
0217
0218 pinctrl_led: ledgrp {
0219 fsl,pins = <
0220 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
0221 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
0222 >;
0223 };
0224
0225 pinctrl_uart4_rts: uart4rtsgrp {
0226 fsl,pins = <
0227 /* SODIMM 222 */
0228 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
0229 >;
0230 };
0231 };
0232
0233 &pinctrl_gpio1 {
0234 fsl,pins = <
0235 /* SODIMM 206 */
0236 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
0237 >;
0238 };
0239
0240 &pinctrl_gpio_hog1 {
0241 fsl,pins = <
0242 /* SODIMM 88 */
0243 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
0244 /* CPLD_int */
0245 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
0246 /* CPLD_reset */
0247 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
0248 /* SODIMM 94 */
0249 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
0250 /* SODIMM 96 */
0251 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
0252 /* CPLD_D[7] */
0253 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
0254 /* CPLD_D[6] */
0255 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
0256 /* CPLD_D[5] */
0257 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
0258 /* CPLD_D[4] */
0259 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
0260 /* CPLD_D[3] */
0261 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
0262 /* CPLD_D[2] */
0263 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
0264 /* CPLD_D[1] */
0265 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
0266 /* CPLD_D[0] */
0267 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
0268 /* KBD_intK */
0269 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
0270 /* DISP_reset */
0271 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
0272 /* KBD_intI */
0273 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
0274 /* SODIMM 46 */
0275 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
0276 >;
0277 };
0278
0279 &pinctrl_uart1 {
0280 fsl,pins = <
0281 /* SODIMM 149 */
0282 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
0283 /* SODIMM 147 */
0284 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
0285 /* SODIMM 210 */
0286 MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
0287 /* SODIMM 212 */
0288 MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
0289 >;
0290 };
0291
0292 ®_usb_otg1_vbus {
0293 /delete-property/ enable-active-high;
0294 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
0295 };
0296
0297 ®_usb_otg2_vbus {
0298 /delete-property/ enable-active-high;
0299 gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
0300 };
0301
0302 &sai2 {
0303 status = "disabled";
0304 };
0305
0306 &uart1 {
0307 uart-has-rtscts;
0308 status = "okay";
0309 };
0310
0311 &uart2 {
0312 status = "okay";
0313 };
0314
0315 &uart4 {
0316 pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
0317 linux,rs485-enabled-at-boot-time;
0318 rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0319 status = "okay";
0320 };
0321
0322 &usbotg1 {
0323 dr_mode = "peripheral";
0324 status = "okay";
0325 };
0326
0327 &usbotg2 {
0328 dr_mode = "host";
0329 status = "okay";
0330 };
0331
0332 &usdhc2 {
0333 status = "okay";
0334 };
