0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019-2020 NXP
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/usb/pd.h>
0009 #include "imx8mm-evk.dtsi"
0010
0011 / {
0012 model = "FSL i.MX8MM EVK board";
0013 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
0014
0015 aliases {
0016 spi0 = &flexspi;
0017 };
0018 };
0019
0020 &ddrc {
0021 operating-points-v2 = <&ddrc_opp_table>;
0022
0023 ddrc_opp_table: opp-table {
0024 compatible = "operating-points-v2";
0025
0026 opp-25M {
0027 opp-hz = /bits/ 64 <25000000>;
0028 };
0029
0030 opp-100M {
0031 opp-hz = /bits/ 64 <100000000>;
0032 };
0033
0034 opp-750M {
0035 opp-hz = /bits/ 64 <750000000>;
0036 };
0037 };
0038 };
0039
0040 &flexspi {
0041 pinctrl-names = "default";
0042 pinctrl-0 = <&pinctrl_flexspi>;
0043 status = "okay";
0044
0045 flash@0 {
0046 reg = <0>;
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049 compatible = "jedec,spi-nor";
0050 spi-max-frequency = <80000000>;
0051 spi-tx-bus-width = <1>;
0052 spi-rx-bus-width = <4>;
0053 };
0054 };
0055
0056 &usdhc3 {
0057 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
0058 assigned-clock-rates = <400000000>;
0059 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0060 pinctrl-0 = <&pinctrl_usdhc3>;
0061 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0062 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0063 bus-width = <8>;
0064 non-removable;
0065 status = "okay";
0066 };
0067
0068 &iomuxc {
0069 pinctrl_flexspi: flexspigrp {
0070 fsl,pins = <
0071 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0072 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0073 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0074 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0075 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0076 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0077 >;
0078 };
0079
0080 pinctrl_usdhc3: usdhc3grp {
0081 fsl,pins = <
0082 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0083 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0084 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0085 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0086 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0087 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0088 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0089 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0090 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0091 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0092 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0093 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0094 >;
0095 };
0096
0097 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0098 fsl,pins = <
0099 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0100 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0101 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0102 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0103 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0104 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0105 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0106 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0107 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0108 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0109 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0110 >;
0111 };
0112
0113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0114 fsl,pins = <
0115 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0116 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0117 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0118 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0119 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0120 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0121 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0122 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0123 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0124 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0125 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0126 >;
0127 };
0128 };
