0001 // SPDX-License-Identifier: (GPL-2.0 or MIT)
0002 //
0003 // Copyright 2018 NXP
0004 // Copyright (C) 2021 emtrion GmbH
0005 //
0006
0007 /dts-v1/;
0008
0009 #include "imx8mm.dtsi"
0010
0011 / {
0012 chosen {
0013 stdout-path = &uart1;
0014 };
0015
0016 som_leds: leds {
0017 compatible = "gpio-leds";
0018 pinctrl-names = "default";
0019 pinctrl-0 = <&pinctrl_gpio_led>;
0020
0021 green {
0022 label = "som:green";
0023 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
0024 default-state = "on";
0025 linux,default-trigger = "heartbeat";
0026 };
0027
0028 red {
0029 label = "som:red";
0030 gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
0031 default-state = "off";
0032 };
0033 };
0034
0035 lvds_backlight: lvds-backlight {
0036 compatible = "pwm-backlight";
0037 enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
0038 pwms = <&pwm1 0 50000 0>;
0039 brightness-levels = <
0040 0 4 8 16 32 64 80 96 112
0041 128 144 160 176 250
0042 >;
0043 default-brightness-level = <9>;
0044 status = "disabled";
0045 };
0046
0047 reg_usdhc1_vmmc: regulator-emmc {
0048 compatible = "regulator-fixed";
0049 regulator-name = "eMMC";
0050 regulator-min-microvolt = <3300000>;
0051 regulator-max-microvolt = <3300000>;
0052 };
0053
0054 reg_usdhc2_vmmc: regulator-usdhc2 {
0055 compatible = "regulator-fixed";
0056 regulator-name = "sdcard_3V3";
0057 regulator-min-microvolt = <3300000>;
0058 regulator-max-microvolt = <3300000>;
0059 };
0060 };
0061
0062 &A53_0 {
0063 cpu-supply = <&buck2_reg>;
0064 };
0065
0066 &ecspi1 {
0067 pinctrl-names = "default";
0068 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
0069 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
0070 <&gpio5 13 GPIO_ACTIVE_LOW>;
0071 status = "okay";
0072 };
0073
0074 &fec1 {
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_fec1>;
0077 phy-mode = "rgmii-id";
0078 phy-handle = <ðphy0>;
0079 fsl,magic-packet;
0080 status = "okay";
0081
0082 mdio {
0083 #address-cells = <1>;
0084 #size-cells = <0>;
0085
0086 ethphy0: ethernet-phy@0 {
0087 compatible = "ethernet-phy-ieee802.3-c22";
0088 reg = <0>;
0089 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0090 reset-assert-us = <10000>;
0091 };
0092 };
0093 };
0094
0095 &flexspi {
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&pinctrl_flexspi0>;
0098 pinctrl-1 = <&pinctrl_flexspi1>;
0099 status = "okay";
0100
0101 flash0: flash@0 {
0102 reg = <0>;
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 compatible = "jedec,spi-nor";
0106 spi-max-frequency = <40000000>;
0107 };
0108 };
0109
0110 &iomuxc {
0111 pinctrl-names = "default";
0112
0113 pinctrl_csi_pwn: csi-pwn-grp {
0114 fsl,pins = <
0115 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
0116 >;
0117 };
0118
0119 pinctrl_ecspi1: ecspi1-grp {
0120 fsl,pins = <
0121 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
0122 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
0123 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
0124 >;
0125 };
0126
0127 pinctrl_ecspi1_cs: ecspi1-cs {
0128 fsl,pins = <
0129 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
0130 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
0131 >;
0132 };
0133
0134 pinctrl_fec1: fec1-grp {
0135 fsl,pins = <
0136 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0137 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0138 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0139 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0140 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0141 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0142 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0143 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0144 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0145 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0146 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0147 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0148 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0149 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0150 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0151 >;
0152 };
0153
0154 pinctrl_flexspi0: flexspi0-grp {
0155 fsl,pins = <
0156 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0157 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0158 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0159 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0160 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0161 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0162 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82
0163 >;
0164 };
0165
0166 pinctrl_flexspi1: flexspi1-grp {
0167 fsl,pins = <
0168 MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2
0169 MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82
0170 MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82
0171 MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82
0172 MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82
0173 MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82
0174 >;
0175 };
0176
0177 pinctrl_gpio_led: gpio-led-grp {
0178 fsl,pins = <
0179 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19
0180 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
0181 >;
0182 };
0183
0184 pinctrl_i2c1: i2c1-grp {
0185 fsl,pins = <
0186 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0187 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0188 >;
0189 };
0190
0191 pinctrl_i2c2: i2c2grp {
0192 fsl,pins = <
0193 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0194 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0195 >;
0196 };
0197
0198 pinctrl_i2c3: i2c3-grp {
0199 fsl,pins = <
0200 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0201 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0202 >;
0203 };
0204
0205 pinctrl_lvds: lvds-grp {
0206 fsl,pins = <
0207 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06
0208 >;
0209 };
0210
0211 pinctrl_pcie0: pcie0-grp {
0212 fsl,pins = <
0213 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
0214 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41
0215 >;
0216 };
0217
0218 pinctrl_pmic: pmic-irq {
0219 fsl,pins = <
0220 MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41
0221 >;
0222 };
0223
0224 pinctrl_pwm1: pwm1-grp {
0225 fsl,pins = <
0226 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
0227 >;
0228 };
0229
0230 pinctrl_sai2: sai2-grp {
0231 fsl,pins = <
0232 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
0233 MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
0234 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
0235 MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
0236 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
0237 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
0238 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
0239 >;
0240 };
0241
0242 pinctrl_spdif1: spdif1-grp {
0243 fsl,pins = <
0244 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
0245 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
0246 >;
0247 };
0248
0249 pinctrl_uart1: uart1-grp {
0250 fsl,pins = <
0251 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0252 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0253 >;
0254 };
0255
0256 pinctrl_uart2: uart2-grp {
0257 fsl,pins = <
0258 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0259 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0260
0261 /* rts and cts */
0262 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
0263 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
0264 >;
0265 };
0266
0267 pinctrl_uart3: uart3-grp {
0268 fsl,pins = <
0269 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0270 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0271 >;
0272 };
0273
0274 pinctrl_uart4: uart4-grp {
0275 fsl,pins = <
0276 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0277 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0278 >;
0279 };
0280
0281 pinctrl_usdhc1: usdhc1-grp {
0282 fsl,pins = <
0283 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0284 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0285 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0286 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0287 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0288 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0289 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
0290 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
0291 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
0292 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
0293 >;
0294 };
0295
0296 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
0297 fsl,pins = <
0298 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0299 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0300 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0301 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0302 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0303 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0304 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
0305 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
0306 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
0307 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
0308 >;
0309 };
0310
0311 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
0312 fsl,pins = <
0313 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0314 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0315 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0316 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0317 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0318 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0319 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
0320 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
0321 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
0322 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
0323 >;
0324 };
0325
0326 pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
0327 fsl,pins = <
0328 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41
0329 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4
0330 >;
0331 };
0332
0333 pinctrl_usdhc2: usdhc2-grp {
0334 fsl,pins = <
0335 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0336 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0337 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0338 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0339 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0340 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0341 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0342 >;
0343 };
0344
0345 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
0346 fsl,pins = <
0347 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0348 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0349 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0350 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0351 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0352 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0353 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0354 >;
0355 };
0356
0357 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
0358 fsl,pins = <
0359 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0360 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0361 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0362 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0363 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0364 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0365 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0366 >;
0367 };
0368
0369 /* no reset for sdhc2 interface */
0370 pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
0371 fsl,pins = <
0372 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
0373 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4
0374 >;
0375 };
0376
0377 pinctrl_wdog: wdog-grp {
0378 fsl,pins = <
0379 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0380 >;
0381 };
0382 };
0383
0384 &i2c1 {
0385 clock-frequency = <400000>;
0386 pinctrl-names = "default";
0387 pinctrl-0 = <&pinctrl_i2c1>;
0388 status = "okay";
0389 };
0390
0391 &i2c2 {
0392 clock-frequency = <400000>;
0393 pinctrl-names = "default";
0394 pinctrl-0 = <&pinctrl_i2c2>;
0395 status = "okay";
0396 };
0397
0398 &i2c3 {
0399 clock-frequency = <400000>;
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&pinctrl_i2c3>;
0402 status = "okay";
0403
0404 bd71847: pmic@4b {
0405 compatible = "rohm,bd71847";
0406 reg = <0x4b>;
0407 pinctrl-0 = <&pinctrl_pmic>;
0408 interrupt-parent = <&gpio3>;
0409 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0410 rohm,reset-snvs-powered;
0411
0412 regulators {
0413 buck1_reg: BUCK1 {
0414 regulator-name = "BUCK1";
0415 regulator-min-microvolt = <700000>;
0416 regulator-max-microvolt = <1300000>;
0417 regulator-boot-on;
0418 regulator-always-on;
0419 regulator-ramp-delay = <1250>;
0420 };
0421
0422 buck2_reg: BUCK2 {
0423 regulator-name = "BUCK2";
0424 regulator-min-microvolt = <700000>;
0425 regulator-max-microvolt = <1300000>;
0426 regulator-boot-on;
0427 regulator-always-on;
0428 regulator-ramp-delay = <1250>;
0429 rohm,dvs-run-voltage = <1000000>;
0430 rohm,dvs-idle-voltage = <900000>;
0431 };
0432
0433 buck3_reg: BUCK3 {
0434 // BUCK5 in datasheet
0435 regulator-name = "BUCK3";
0436 regulator-min-microvolt = <700000>;
0437 regulator-max-microvolt = <1350000>;
0438 regulator-boot-on;
0439 regulator-always-on;
0440 };
0441
0442 buck4_reg: BUCK4 {
0443 // BUCK6 in datasheet
0444 regulator-name = "BUCK4";
0445 regulator-min-microvolt = <3000000>;
0446 regulator-max-microvolt = <3300000>;
0447 regulator-boot-on;
0448 regulator-always-on;
0449 };
0450
0451 buck5_reg: BUCK5 {
0452 // BUCK7 in datasheet
0453 regulator-name = "BUCK5";
0454 regulator-min-microvolt = <1605000>;
0455 regulator-max-microvolt = <1995000>;
0456 regulator-boot-on;
0457 regulator-always-on;
0458 };
0459
0460 buck6_reg: BUCK6 {
0461 // BUCK8 in datasheet
0462 regulator-name = "BUCK6";
0463 regulator-min-microvolt = <800000>;
0464 regulator-max-microvolt = <1400000>;
0465 regulator-boot-on;
0466 regulator-always-on;
0467 };
0468
0469 ldo1_reg: LDO1 {
0470 regulator-name = "LDO1";
0471 regulator-min-microvolt = <1600000>;
0472 regulator-max-microvolt = <1900000>;
0473 regulator-boot-on;
0474 regulator-always-on;
0475 };
0476
0477 ldo2_reg: LDO2 {
0478 regulator-name = "LDO2";
0479 regulator-min-microvolt = <800000>;
0480 regulator-max-microvolt = <900000>;
0481 regulator-boot-on;
0482 regulator-always-on;
0483 };
0484
0485 ldo3_reg: LDO3 {
0486 regulator-name = "LDO3";
0487 regulator-min-microvolt = <1800000>;
0488 regulator-max-microvolt = <3300000>;
0489 regulator-boot-on;
0490 regulator-always-on;
0491 };
0492
0493 ldo4_reg: LDO4 {
0494 regulator-name = "LDO4";
0495 regulator-min-microvolt = <900000>;
0496 regulator-max-microvolt = <1800000>;
0497 regulator-boot-on;
0498 regulator-always-on;
0499 };
0500
0501 ldo6_reg: LDO6 {
0502 regulator-name = "LDO6";
0503 regulator-min-microvolt = <900000>;
0504 regulator-max-microvolt = <1800000>;
0505 regulator-boot-on;
0506 regulator-always-on;
0507 };
0508 };
0509 };
0510
0511 rv1805: rtc@69 {
0512 compatible = "abracon,ab1805";
0513 reg = <0x69>;
0514 };
0515 };
0516
0517 &mu {
0518 status = "okay";
0519 };
0520
0521 &pwm1 {
0522 pinctrl-names = "default";
0523 pinctrl-0 = <&pinctrl_pwm1>;
0524 };
0525
0526 &sai2 {
0527 #sound-dai-cells = <0>;
0528 pinctrl-names = "default";
0529 pinctrl-0 = <&pinctrl_sai2>;
0530 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
0531 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0532 assigned-clock-rates = <12000000>;
0533 status = "disabled";
0534 };
0535
0536 &spdif1 {
0537 pinctrl-names = "default";
0538 pinctrl-0 = <&pinctrl_spdif1>;
0539 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
0540 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0541 assigned-clock-rates = <24576000>;
0542 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
0543 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
0544 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
0545 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
0546 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
0547 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
0548 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
0549 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
0550 status = "disabled";
0551 };
0552
0553 &uart1 { /* console */
0554 pinctrl-names = "default";
0555 pinctrl-0 = <&pinctrl_uart1>;
0556 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
0557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0558 status = "okay";
0559 };
0560
0561 &uart2 {
0562 pinctrl-names = "default";
0563 pinctrl-0 = <&pinctrl_uart2>;
0564 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
0565 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0566 status = "okay";
0567 };
0568
0569 &uart3 {
0570 pinctrl-names = "default";
0571 pinctrl-0 = <&pinctrl_uart3>;
0572 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
0573 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0574 status = "okay";
0575 };
0576
0577 &uart4 {
0578 pinctrl-names = "default";
0579 pinctrl-0 = <&pinctrl_uart4>;
0580 assigned-clocks = <&clk IMX8MM_CLK_UART4>;
0581 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0582 status = "okay";
0583 };
0584
0585 &usbotg1 {
0586 dr_mode = "otg";
0587 over-current-active-low;
0588 status = "okay";
0589 };
0590
0591 &usbotg2 {
0592 dr_mode = "host";
0593 disable-over-current;
0594 status = "disabled";
0595 };
0596
0597 &usdhc1 {
0598 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0599 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
0600 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
0601 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
0602 bus-width = <8>;
0603 vmmc-supply = <®_usdhc1_vmmc>;
0604 keep-power-in-suspend;
0605 non-removable;
0606 status = "okay";
0607 };
0608
0609 &usdhc2 {
0610 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0611 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0612 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0613 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0614 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0615 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
0616 bus-width = <4>;
0617 vmmc-supply = <®_usdhc2_vmmc>;
0618 no-1-8-v;
0619 status = "okay";
0620 };
0621
0622 &wdog1 {
0623 pinctrl-names = "default";
0624 pinctrl-0 = <&pinctrl_wdog>;
0625 fsl,ext-reset-output;
0626 status = "okay";
0627 };
