0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Marek Vasut <marex@denx.de>
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/net/qca-ar803x.h>
0009 #include <dt-bindings/phy/phy-imx8-pcie.h>
0010 #include "imx8mm.dtsi"
0011
0012 / {
0013 model = "Data Modul i.MX8M Mini eDM SBC";
0014 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
0015
0016 aliases {
0017 rtc0 = &rtc;
0018 rtc1 = &snvs_rtc;
0019 };
0020
0021 chosen {
0022 stdout-path = &uart3;
0023 };
0024
0025 memory@40000000 {
0026 device_type = "memory";
0027 /* There are 1/2/4 GiB options, adjusted by bootloader. */
0028 reg = <0x0 0x40000000 0 0x40000000>;
0029 };
0030
0031 backlight: backlight {
0032 compatible = "pwm-backlight";
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&pinctrl_panel_backlight>;
0035 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
0036 default-brightness-level = <7>;
0037 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
0038 pwms = <&pwm1 0 5000000 0>;
0039 /* Disabled by default, unless display board plugged in. */
0040 status = "disabled";
0041 };
0042
0043 clk_xtal25: clk-xtal25 {
0044 compatible = "fixed-clock";
0045 #clock-cells = <0>;
0046 clock-frequency = <25000000>;
0047 };
0048
0049 panel: panel {
0050 backlight = <&backlight>;
0051 power-supply = <®_panel_vcc>;
0052 /* Disabled by default, unless display board plugged in. */
0053 status = "disabled";
0054 };
0055
0056 reg_panel_vcc: regulator-panel-vcc {
0057 compatible = "regulator-fixed";
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
0060 regulator-name = "PANEL_VCC";
0061 regulator-min-microvolt = <5000000>;
0062 regulator-max-microvolt = <5000000>;
0063 gpio = <&gpio3 6 0>;
0064 enable-active-high;
0065 /* Disabled by default, unless display board plugged in. */
0066 status = "disabled";
0067 };
0068
0069 reg_usdhc2_vcc: regulator-usdhc2-vcc {
0070 compatible = "regulator-fixed";
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
0073 regulator-name = "V_3V3_SD";
0074 regulator-min-microvolt = <3300000>;
0075 regulator-max-microvolt = <3300000>;
0076 gpio = <&gpio2 19 0>;
0077 enable-active-high;
0078 };
0079
0080 watchdog-gpio {
0081 /* TPS3813 */
0082 pinctrl-names = "default";
0083 pinctrl-0 = <&pinctrl_watchdog_gpio>;
0084 compatible = "linux,wdt-gpio";
0085 always-enabled;
0086 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0087 hw_algo = "level";
0088 /* Reset triggers in 2..3 seconds */
0089 hw_margin_ms = <1500>;
0090 /* Disabled by default */
0091 status = "disabled";
0092 };
0093 };
0094
0095 &A53_0 {
0096 cpu-supply = <&buck2_reg>;
0097 };
0098
0099 &A53_1 {
0100 cpu-supply = <&buck2_reg>;
0101 };
0102
0103 &A53_2 {
0104 cpu-supply = <&buck2_reg>;
0105 };
0106
0107 &A53_3 {
0108 cpu-supply = <&buck2_reg>;
0109 };
0110
0111 &ddrc {
0112 operating-points-v2 = <&ddrc_opp_table>;
0113
0114 ddrc_opp_table: opp-table {
0115 compatible = "operating-points-v2";
0116
0117 opp-25M {
0118 opp-hz = /bits/ 64 <25000000>;
0119 };
0120
0121 opp-100M {
0122 opp-hz = /bits/ 64 <100000000>;
0123 };
0124
0125 opp-750M {
0126 opp-hz = /bits/ 64 <750000000>;
0127 };
0128 };
0129 };
0130
0131 &ecspi1 {
0132 pinctrl-names = "default";
0133 pinctrl-0 = <&pinctrl_ecspi1>;
0134 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0135 status = "okay";
0136
0137 flash@0 { /* W25Q128FVSI */
0138 compatible = "jedec,spi-nor";
0139 m25p,fast-read;
0140 spi-max-frequency = <50000000>;
0141 reg = <0>;
0142 };
0143 };
0144
0145 &ecspi2 { /* Feature connector SPI */
0146 pinctrl-names = "default";
0147 pinctrl-0 = <&pinctrl_ecspi2>;
0148 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0149 /* Disabled by default, unless feature board plugged in. */
0150 status = "disabled";
0151 };
0152
0153 &ecspi3 { /* Display connector SPI */
0154 pinctrl-names = "default";
0155 pinctrl-0 = <&pinctrl_ecspi3>;
0156 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
0157 /* Disabled by default, unless display board plugged in. */
0158 status = "disabled";
0159 };
0160
0161 &fec1 {
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_fec1>;
0164 phy-mode = "rgmii-id";
0165 phy-handle = <&fec1_phy>;
0166 phy-supply = <&buck4_reg>;
0167 fsl,magic-packet;
0168 status = "okay";
0169
0170 mdio {
0171 #address-cells = <1>;
0172 #size-cells = <0>;
0173
0174 /* Atheros AR8031 PHY */
0175 fec1_phy: ethernet-phy@0 {
0176 compatible = "ethernet-phy-ieee802.3-c22";
0177 reg = <0>;
0178 /*
0179 * Dedicated ENET_WOL# signal is unused, the PHY
0180 * can wake the SoC up via INT signal as well.
0181 */
0182 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
0183 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0184 reset-assert-us = <10000>;
0185 reset-deassert-us = <10000>;
0186 qca,clk-out-frequency = <125000000>;
0187 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
0188 qca,keep-pll-enabled;
0189 vddio-supply = <&vddio>;
0190
0191 vddio: vddio-regulator {
0192 regulator-name = "VDDIO";
0193 regulator-min-microvolt = <1800000>;
0194 regulator-max-microvolt = <1800000>;
0195 };
0196
0197 vddh: vddh-regulator {
0198 regulator-name = "VDDH";
0199 };
0200 };
0201 };
0202 };
0203
0204 &gpio1 {
0205 gpio-line-names =
0206 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
0207 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
0208 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
0209 "USB1_OTG_ID_3V3", "ENET_WOL#",
0210 "", "", "", "ENET_INT#",
0211 "", "", "", "", "", "", "", "",
0212 "", "", "", "", "", "", "", "";
0213 };
0214
0215 &gpio2 {
0216 gpio-line-names =
0217 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
0218 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
0219 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
0220 "MEMCFG0", "WDOG_EN",
0221 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
0222 "", "", "", "",
0223 "", "", "", "SD2_RESET#", "", "", "", "",
0224 "", "", "", "", "", "", "", "";
0225 };
0226
0227 &gpio3 {
0228 gpio-line-names =
0229 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
0230 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
0231 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
0232 "", "", "", "",
0233 "", "", "", "M2-B_WAKE_WWAN_1V8#",
0234 "M2-B_RESET_1V8#", "", "", "",
0235 "", "", "", "", "", "", "", "";
0236 };
0237
0238 &gpio4 {
0239 gpio-line-names =
0240 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
0241 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
0242 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
0243 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
0244 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
0245 "NC20", "", "", "",
0246 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
0247 "DIS_USB_DN2", "", "", "";
0248 };
0249
0250 &gpio5 {
0251 gpio-line-names =
0252 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
0253 "GPIO5_IO04", "", "", "",
0254 "", "SPI1_CS#", "", "",
0255 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
0256 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
0257 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
0258 "", "SPI3_CS#", "", "", "", "", "", "";
0259 };
0260
0261 &i2c1 {
0262 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
0263 clock-frequency = <100000>;
0264 pinctrl-names = "default", "gpio";
0265 pinctrl-0 = <&pinctrl_i2c1>;
0266 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0267 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0268 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0269 status = "okay";
0270
0271 pmic: pmic@4b {
0272 compatible = "rohm,bd71847";
0273 reg = <0x4b>;
0274 pinctrl-names = "default";
0275 pinctrl-0 = <&pinctrl_pmic>;
0276 interrupt-parent = <&gpio1>;
0277 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
0278 rohm,reset-snvs-powered;
0279
0280 /*
0281 * i.MX 8M Mini Data Sheet for Consumer Products
0282 * 3.1.3 Operating ranges
0283 * MIMX8MM4DVTLZAA
0284 */
0285 regulators {
0286 /* VDD_SOC */
0287 buck1_reg: BUCK1 {
0288 regulator-name = "buck1";
0289 regulator-min-microvolt = <850000>;
0290 regulator-max-microvolt = <850000>;
0291 regulator-boot-on;
0292 regulator-always-on;
0293 regulator-ramp-delay = <1250>;
0294 };
0295
0296 /* VDD_ARM */
0297 buck2_reg: BUCK2 {
0298 regulator-name = "buck2";
0299 regulator-min-microvolt = <850000>;
0300 regulator-max-microvolt = <1050000>;
0301 regulator-boot-on;
0302 regulator-always-on;
0303 regulator-ramp-delay = <1250>;
0304 rohm,dvs-run-voltage = <1000000>;
0305 rohm,dvs-idle-voltage = <950000>;
0306 };
0307
0308 /* VDD_DRAM, BUCK5 */
0309 buck3_reg: BUCK3 {
0310 regulator-name = "buck3";
0311 /* 1.5 GHz DDR bus clock */
0312 regulator-min-microvolt = <900000>;
0313 regulator-max-microvolt = <1000000>;
0314 regulator-boot-on;
0315 regulator-always-on;
0316 };
0317
0318 /* 3V3_VDD, BUCK6 */
0319 buck4_reg: BUCK4 {
0320 regulator-name = "buck4";
0321 regulator-min-microvolt = <3300000>;
0322 regulator-max-microvolt = <3300000>;
0323 regulator-boot-on;
0324 regulator-always-on;
0325 };
0326
0327 /* 1V8_VDD, BUCK7 */
0328 buck5_reg: BUCK5 {
0329 regulator-name = "buck5";
0330 regulator-min-microvolt = <1800000>;
0331 regulator-max-microvolt = <1800000>;
0332 regulator-boot-on;
0333 regulator-always-on;
0334 };
0335
0336 /* 1V1_NVCC_DRAM, BUCK8 */
0337 buck6_reg: BUCK6 {
0338 regulator-name = "buck6";
0339 regulator-min-microvolt = <1100000>;
0340 regulator-max-microvolt = <1100000>;
0341 regulator-boot-on;
0342 regulator-always-on;
0343 };
0344
0345 /* 1V8_NVCC_SNVS */
0346 ldo1_reg: LDO1 {
0347 regulator-name = "ldo1";
0348 regulator-min-microvolt = <1800000>;
0349 regulator-max-microvolt = <1800000>;
0350 regulator-boot-on;
0351 regulator-always-on;
0352 };
0353
0354 /* 0V8_VDD_SNVS */
0355 ldo2_reg: LDO2 {
0356 regulator-name = "ldo2";
0357 regulator-min-microvolt = <800000>;
0358 regulator-max-microvolt = <800000>;
0359 regulator-boot-on;
0360 regulator-always-on;
0361 };
0362
0363 /* 1V8_VDDA */
0364 ldo3_reg: LDO3 {
0365 regulator-name = "ldo3";
0366 regulator-min-microvolt = <1800000>;
0367 regulator-max-microvolt = <1800000>;
0368 regulator-boot-on;
0369 regulator-always-on;
0370 };
0371
0372 /* 0V9_VDD_PHY */
0373 ldo4_reg: LDO4 {
0374 regulator-name = "ldo4";
0375 regulator-min-microvolt = <900000>;
0376 regulator-max-microvolt = <900000>;
0377 regulator-boot-on;
0378 regulator-always-on;
0379 };
0380
0381 /* 1V2_VDD_PHY */
0382 ldo6_reg: LDO6 {
0383 regulator-name = "ldo6";
0384 regulator-min-microvolt = <1200000>;
0385 regulator-max-microvolt = <1200000>;
0386 regulator-boot-on;
0387 regulator-always-on;
0388 };
0389 };
0390 };
0391 };
0392
0393 &i2c2 {
0394 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
0395 clock-frequency = <100000>;
0396 pinctrl-names = "default", "gpio";
0397 pinctrl-0 = <&pinctrl_i2c2>;
0398 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0399 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0400 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0401 status = "okay";
0402
0403 usb-hub@2c {
0404 pinctrl-names = "default";
0405 pinctrl-0 = <&pinctrl_usb_hub>;
0406 compatible = "microchip,usb2514bi";
0407 reg = <0x2c>;
0408 individual-port-switching;
0409 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
0410 self-powered;
0411 };
0412
0413 eeprom: eeprom@50 {
0414 compatible = "atmel,24c32";
0415 reg = <0x50>;
0416 pagesize = <32>;
0417 };
0418
0419 rtc: rtc@68 {
0420 pinctrl-names = "default";
0421 pinctrl-0 = <&pinctrl_rtc>;
0422 compatible = "st,m41t62";
0423 reg = <0x68>;
0424 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
0425 };
0426
0427 pcieclk: clk@6a {
0428 compatible = "renesas,9fgv0241";
0429 reg = <0x6a>;
0430 clocks = <&clk_xtal25>;
0431 #clock-cells = <1>;
0432 };
0433 };
0434
0435 &i2c3 { /* Display connector I2C */
0436 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
0437 clock-frequency = <320000>;
0438 pinctrl-names = "default", "gpio";
0439 pinctrl-0 = <&pinctrl_i2c3>;
0440 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0441 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0442 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0443 status = "okay";
0444 };
0445
0446 &i2c4 { /* Feature connector I2C */
0447 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
0448 clock-frequency = <320000>;
0449 pinctrl-names = "default", "gpio";
0450 pinctrl-0 = <&pinctrl_i2c4>;
0451 pinctrl-1 = <&pinctrl_i2c4_gpio>;
0452 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0453 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0454 status = "okay";
0455 };
0456
0457 &iomuxc {
0458 pinctrl-names = "default";
0459 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
0460 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
0461 <&pinctrl_panel_expansion>;
0462
0463 pinctrl_ecspi1: ecspi1-grp {
0464 fsl,pins = <
0465 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
0466 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
0467 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
0468 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
0469 >;
0470 };
0471
0472 pinctrl_ecspi2: ecspi2-grp {
0473 fsl,pins = <
0474 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
0475 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
0476 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
0477 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
0478 >;
0479 };
0480
0481 pinctrl_ecspi3: ecspi3-grp {
0482 fsl,pins = <
0483 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
0484 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
0485 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
0486 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
0487 >;
0488 };
0489
0490 pinctrl_fec1: fec1-grp {
0491 fsl,pins = <
0492 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0493 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0494 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0495 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0496 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0497 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0498 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0499 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0500 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0501 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0502 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0503 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0504 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0505 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0506 /* ENET_RST# */
0507 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
0508 /* ENET_WOL# */
0509 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
0510 /* ENET_INT# */
0511 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
0512 >;
0513 };
0514
0515 pinctrl_hog_feature: hog-feature-grp {
0516 fsl,pins = <
0517 /* GPIO4_IO27 */
0518 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
0519 /* GPIO5_IO03 */
0520 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
0521 /* GPIO5_IO04 */
0522 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
0523
0524 /* CAN_INT# */
0525 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
0526 /* CAN_RST# */
0527 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
0528 >;
0529 };
0530
0531 pinctrl_hog_panel: hog-panel-grp {
0532 fsl,pins = <
0533 /* GRAPHICS_GPIO0_1V8 */
0534 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
0535 >;
0536 };
0537
0538 pinctrl_hog_misc: hog-misc-grp {
0539 fsl,pins = <
0540 /* PG_V_IN_VAR# */
0541 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
0542 /* CSI_PD_1V8 */
0543 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
0544 /* CSI_RESET_1V8# */
0545 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
0546
0547 /* DIS_USB_DN1 */
0548 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
0549 /* DIS_USB_DN2 */
0550 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
0551
0552 /* EEPROM_WP_1V8# */
0553 MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
0554 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
0555 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
0556 /* GRAPHICS_PRSNT_1V8# */
0557 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
0558
0559 /* CLK_CCM_CLKO1_3V3 */
0560 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
0561 >;
0562 };
0563
0564 pinctrl_hog_sbc: hog-sbc-grp {
0565 fsl,pins = <
0566 /* MEMCFG[0..2] straps */
0567 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
0568 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
0569 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
0570
0571 /* BOOT_CFG[0..15] straps */
0572 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
0573 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
0574 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
0575 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
0576 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
0577 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
0578 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
0579 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
0580 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
0581 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
0582 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
0583 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
0584 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
0585 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
0586 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
0587 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
0588
0589 /* Not connected pins */
0590 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
0591 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
0592 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
0593 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
0594 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
0595 >;
0596 };
0597
0598 pinctrl_i2c1: i2c1-grp {
0599 fsl,pins = <
0600 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
0601 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
0602 >;
0603 };
0604
0605 pinctrl_i2c1_gpio: i2c1-gpio-grp {
0606 fsl,pins = <
0607 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
0608 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
0609 >;
0610 };
0611
0612 pinctrl_i2c2: i2c2-grp {
0613 fsl,pins = <
0614 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
0615 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
0616 >;
0617 };
0618
0619 pinctrl_i2c2_gpio: i2c2-gpio-grp {
0620 fsl,pins = <
0621 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
0622 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
0623 >;
0624 };
0625
0626 pinctrl_i2c3: i2c3-grp {
0627 fsl,pins = <
0628 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
0629 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
0630 >;
0631 };
0632
0633 pinctrl_i2c3_gpio: i2c3-gpio-grp {
0634 fsl,pins = <
0635 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
0636 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
0637 >;
0638 };
0639
0640 pinctrl_i2c4: i2c4-grp {
0641 fsl,pins = <
0642 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
0643 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
0644 >;
0645 };
0646
0647 pinctrl_i2c4_gpio: i2c4-gpio-grp {
0648 fsl,pins = <
0649 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
0650 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
0651 >;
0652 };
0653
0654 pinctrl_panel_backlight: panel-backlight-grp {
0655 fsl,pins = <
0656 /* BL_ENABLE_1V8 */
0657 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
0658 >;
0659 };
0660
0661 pinctrl_panel_expansion: panel-expansion-grp {
0662 fsl,pins = <
0663 /* DSI_RESET_1V8# */
0664 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
0665 /* DSI_IRQ_1V8# */
0666 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
0667 >;
0668 };
0669
0670 pinctrl_panel_vcc_reg: panel-vcc-grp {
0671 fsl,pins = <
0672 /* TFT_ENABLE_1V8 */
0673 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
0674 >;
0675 };
0676
0677 pinctrl_panel_pwm: panel-pwm-grp {
0678 fsl,pins = <
0679 /* BL_PWM_3V3 */
0680 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
0681 >;
0682 };
0683
0684 pinctrl_pcie0: pcie-grp {
0685 fsl,pins = <
0686 /* M2-B_RESET_1V8# */
0687 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
0688 /* M2-B_PCIE_RST# */
0689 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
0690 /* M2-B_FULL_CARD_PWROFF_1V8# */
0691 MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
0692 /* M2-B_W_DISABLE1_WWAN_1V8# */
0693 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
0694 /* M2-B_W_DISABLE2_GPS_1V8# */
0695 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
0696 /* CLK_M2_32K768 */
0697 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
0698 /* M2-B_WAKE_WWAN_1V8# */
0699 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
0700 /* M2-B_PCIE_WAKE# */
0701 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
0702 /* M2-B_PCIE_CLKREQ# */
0703 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
0704 >;
0705 };
0706
0707 pinctrl_pmic: pmic-grp {
0708 fsl,pins = <
0709 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
0710 >;
0711 };
0712
0713 pinctrl_rtc: rtc-grp {
0714 fsl,pins = <
0715 /* RTC_IRQ# */
0716 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
0717 >;
0718 };
0719
0720 pinctrl_sai5: sai5-grp {
0721 fsl,pins = <
0722 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
0723 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
0724 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
0725 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
0726 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
0727 >;
0728 };
0729
0730 pinctrl_uart1: uart1-grp {
0731 fsl,pins = <
0732 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
0733 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
0734 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
0735 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
0736 >;
0737 };
0738
0739 pinctrl_uart2: uart2-grp {
0740 fsl,pins = <
0741 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
0742 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
0743 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
0744 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
0745 >;
0746 };
0747
0748 pinctrl_uart3: uart3-grp {
0749 fsl,pins = <
0750 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
0751 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
0752 >;
0753 };
0754
0755 pinctrl_uart4: uart4-grp {
0756 fsl,pins = <
0757 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
0758 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
0759 >;
0760 };
0761
0762 pinctrl_usb_hub: usb-hub-grp {
0763 fsl,pins = <
0764 /* USBHUB_RESET# */
0765 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
0766 >;
0767 };
0768
0769 pinctrl_usb_otg1: usb-otg1-grp {
0770 fsl,pins = <
0771 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
0772 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
0773 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
0774 >;
0775 };
0776
0777 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
0778 fsl,pins = <
0779 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
0780 >;
0781 };
0782
0783 pinctrl_usdhc2: usdhc2-grp {
0784 fsl,pins = <
0785 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0786 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0787 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0788 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0789 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0790 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0791 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
0792 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
0793 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0794 >;
0795 };
0796
0797 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
0798 fsl,pins = <
0799 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0800 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0801 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0802 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0803 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0804 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0805 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
0806 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
0807 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0808 >;
0809 };
0810
0811 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
0812 fsl,pins = <
0813 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0814 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0815 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0816 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0817 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0818 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0819 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
0820 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
0821 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0822 >;
0823 };
0824
0825 pinctrl_usdhc3: usdhc3-grp {
0826 fsl,pins = <
0827 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0828 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0829 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0830 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0831 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0832 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0833 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0834 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0835 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0836 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0837 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0838 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
0839 >;
0840 };
0841
0842 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
0843 fsl,pins = <
0844 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0845 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0846 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0847 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0848 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0849 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0850 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0851 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0852 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0853 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0854 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0855 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
0856 >;
0857 };
0858
0859 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
0860 fsl,pins = <
0861 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0862 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0863 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0864 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0865 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0866 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0867 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0868 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0869 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0870 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0871 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0872 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
0873 >;
0874 };
0875
0876 pinctrl_watchdog_gpio: watchdog-gpio-grp {
0877 fsl,pins = <
0878 /* WDOG_B# */
0879 MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
0880 /* WDOG_EN -- ungate WDT RESET# signal propagation */
0881 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
0882 /* WDOG_KICK# / WDI */
0883 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
0884 >;
0885 };
0886 };
0887
0888 &pcie_phy {
0889 fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
0890 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0891 fsl,tx-deemph-gen1 = <0x2d>;
0892 fsl,tx-deemph-gen2 = <0xf>;
0893 clocks = <&pcieclk 0>;
0894 status = "okay";
0895 };
0896
0897 &pcie0 {
0898 pinctrl-names = "default";
0899 pinctrl-0 = <&pinctrl_pcie0>;
0900 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
0901 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0902 <&pcieclk 0>;
0903 clock-names = "pcie", "pcie_aux", "pcie_bus";
0904 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0905 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0906 assigned-clock-rates = <10000000>, <250000000>;
0907 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0908 <&clk IMX8MM_SYS_PLL2_250M>;
0909 status = "okay";
0910 };
0911
0912 &pwm1 {
0913 pinctrl-names = "default";
0914 pinctrl-0 = <&pinctrl_panel_pwm>;
0915 /* Disabled by default, unless display board plugged in. */
0916 status = "disabled";
0917 };
0918
0919 &sai5 {
0920 pinctrl-names = "default";
0921 pinctrl-0 = <&pinctrl_sai5>;
0922 fsl,sai-mclk-direction-output;
0923 /* Input into codec PLL */
0924 assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
0925 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
0926 assigned-clock-rates = <22579200>;
0927 /* Disabled by default, unless display board plugged in. */
0928 status = "disabled";
0929 };
0930
0931 &uart1 {
0932 pinctrl-names = "default";
0933 pinctrl-0 = <&pinctrl_uart1>;
0934 uart-has-rtscts;
0935 status = "disabled";
0936 };
0937
0938 &uart2 {
0939 pinctrl-names = "default";
0940 pinctrl-0 = <&pinctrl_uart2>;
0941 status = "disabled";
0942 };
0943
0944 &uart3 { /* A53 Debug */
0945 pinctrl-names = "default";
0946 pinctrl-0 = <&pinctrl_uart3>;
0947 status = "okay";
0948 };
0949
0950 &uart4 { /* M4 Debug */
0951 pinctrl-names = "default";
0952 pinctrl-0 = <&pinctrl_uart4>;
0953 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
0954 status = "disabled";
0955 };
0956
0957 &usbotg1 {
0958 pinctrl-names = "default";
0959 pinctrl-0 = <&pinctrl_usb_otg1>;
0960 dr_mode = "otg";
0961 status = "okay";
0962 };
0963
0964 &usbotg2 {
0965 disable-over-current;
0966 dr_mode = "host";
0967 status = "okay";
0968 };
0969
0970 &usdhc2 { /* MicroSD */
0971 assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
0972 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0973 pinctrl-0 = <&pinctrl_usdhc2>;
0974 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0975 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0976 bus-width = <4>;
0977 vmmc-supply = <®_usdhc2_vcc>;
0978 status = "okay";
0979 };
0980
0981 &usdhc3 { /* eMMC */
0982 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
0983 assigned-clock-rates = <400000000>;
0984 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0985 pinctrl-0 = <&pinctrl_usdhc3>;
0986 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0987 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0988 bus-width = <8>;
0989 non-removable;
0990 vmmc-supply = <&buck4_reg>;
0991 vqmmc-supply = <&buck5_reg>;
0992 status = "okay";
0993 };
0994
0995 &wdog1 {
0996 status = "okay";
0997 };
