0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2020 Compass Electronics Group, LLC
0004 */
0005
0006 / {
0007 aliases {
0008 rtc0 = &rtc;
0009 rtc1 = &snvs_rtc;
0010 };
0011
0012 usdhc1_pwrseq: usdhc1_pwrseq {
0013 compatible = "mmc-pwrseq-simple";
0014 pinctrl-names = "default";
0015 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
0016 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
0017 clocks = <&osc_32k>;
0018 clock-names = "ext_clock";
0019 post-power-on-delay-ms = <80>;
0020 };
0021
0022 memory@40000000 {
0023 device_type = "memory";
0024 reg = <0x0 0x40000000 0 0x80000000>;
0025 };
0026 };
0027
0028 &A53_0 {
0029 cpu-supply = <&buck2_reg>;
0030 };
0031
0032 &A53_1 {
0033 cpu-supply = <&buck2_reg>;
0034 };
0035
0036 &A53_2 {
0037 cpu-supply = <&buck2_reg>;
0038 };
0039
0040 &A53_3 {
0041 cpu-supply = <&buck2_reg>;
0042 };
0043
0044 &ddrc {
0045 operating-points-v2 = <&ddrc_opp_table>;
0046
0047 ddrc_opp_table: opp-table {
0048 compatible = "operating-points-v2";
0049
0050 opp-25M {
0051 opp-hz = /bits/ 64 <25000000>;
0052 };
0053
0054 opp-100M {
0055 opp-hz = /bits/ 64 <100000000>;
0056 };
0057
0058 opp-750M {
0059 opp-hz = /bits/ 64 <750000000>;
0060 };
0061 };
0062 };
0063
0064 &fec1 {
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_fec1>;
0067 phy-mode = "rgmii-id";
0068 phy-handle = <ðphy0>;
0069 fsl,magic-packet;
0070 status = "okay";
0071
0072 mdio {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 ethphy0: ethernet-phy@0 {
0077 compatible = "ethernet-phy-ieee802.3-c22";
0078 reg = <0>;
0079 };
0080 };
0081 };
0082
0083 &flexspi {
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_flexspi>;
0086 status = "okay";
0087
0088 flash@0 {
0089 reg = <0>;
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 compatible = "jedec,spi-nor";
0093 spi-max-frequency = <80000000>;
0094 spi-tx-bus-width = <1>;
0095 spi-rx-bus-width = <4>;
0096 };
0097 };
0098
0099 &i2c1 {
0100 clock-frequency = <400000>;
0101 pinctrl-names = "default";
0102 pinctrl-0 = <&pinctrl_i2c1>;
0103 status = "okay";
0104
0105 pmic@4b {
0106 compatible = "rohm,bd71847";
0107 reg = <0x4b>;
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&pinctrl_pmic>;
0110 interrupt-parent = <&gpio1>;
0111 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0112 rohm,reset-snvs-powered;
0113
0114 #clock-cells = <0>;
0115 clocks = <&osc_32k 0>;
0116 clock-output-names = "clk-32k-out";
0117
0118 regulators {
0119 buck1_reg: BUCK1 {
0120 regulator-name = "buck1";
0121 regulator-min-microvolt = <700000>;
0122 regulator-max-microvolt = <1300000>;
0123 regulator-boot-on;
0124 regulator-always-on;
0125 regulator-ramp-delay = <1250>;
0126 };
0127
0128 buck2_reg: BUCK2 {
0129 regulator-name = "buck2";
0130 regulator-min-microvolt = <700000>;
0131 regulator-max-microvolt = <1300000>;
0132 regulator-boot-on;
0133 regulator-always-on;
0134 regulator-ramp-delay = <1250>;
0135 rohm,dvs-run-voltage = <1000000>;
0136 rohm,dvs-idle-voltage = <900000>;
0137 };
0138
0139 buck3_reg: BUCK3 {
0140 // BUCK5 in datasheet
0141 regulator-name = "buck3";
0142 regulator-min-microvolt = <700000>;
0143 regulator-max-microvolt = <1350000>;
0144 regulator-boot-on;
0145 regulator-always-on;
0146 };
0147
0148 buck4_reg: BUCK4 {
0149 // BUCK6 in datasheet
0150 regulator-name = "buck4";
0151 regulator-min-microvolt = <3000000>;
0152 regulator-max-microvolt = <3300000>;
0153 regulator-boot-on;
0154 regulator-always-on;
0155 };
0156
0157 buck5_reg: BUCK5 {
0158 // BUCK7 in datasheet
0159 regulator-name = "buck5";
0160 regulator-min-microvolt = <1605000>;
0161 regulator-max-microvolt = <1995000>;
0162 regulator-boot-on;
0163 regulator-always-on;
0164 };
0165
0166 buck6_reg: BUCK6 {
0167 // BUCK8 in datasheet
0168 regulator-name = "buck6";
0169 regulator-min-microvolt = <800000>;
0170 regulator-max-microvolt = <1400000>;
0171 regulator-boot-on;
0172 regulator-always-on;
0173 };
0174
0175 ldo1_reg: LDO1 {
0176 regulator-name = "ldo1";
0177 regulator-min-microvolt = <1600000>;
0178 regulator-max-microvolt = <3300000>;
0179 regulator-boot-on;
0180 regulator-always-on;
0181 };
0182
0183 ldo2_reg: LDO2 {
0184 regulator-name = "ldo2";
0185 regulator-min-microvolt = <800000>;
0186 regulator-max-microvolt = <900000>;
0187 regulator-boot-on;
0188 regulator-always-on;
0189 };
0190
0191 ldo3_reg: LDO3 {
0192 regulator-name = "ldo3";
0193 regulator-min-microvolt = <1800000>;
0194 regulator-max-microvolt = <3300000>;
0195 regulator-boot-on;
0196 regulator-always-on;
0197 };
0198
0199 ldo4_reg: LDO4 {
0200 regulator-name = "ldo4";
0201 regulator-min-microvolt = <900000>;
0202 regulator-max-microvolt = <1800000>;
0203 regulator-boot-on;
0204 regulator-always-on;
0205 };
0206
0207 ldo6_reg: LDO6 {
0208 regulator-name = "ldo6";
0209 regulator-min-microvolt = <900000>;
0210 regulator-max-microvolt = <1800000>;
0211 regulator-boot-on;
0212 regulator-always-on;
0213 };
0214 };
0215 };
0216 };
0217
0218 &i2c3 {
0219 clock-frequency = <400000>;
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_i2c3>;
0222 status = "okay";
0223
0224 eeprom@50 {
0225 compatible = "microchip,24c64", "atmel,24c64";
0226 pagesize = <32>;
0227 read-only; /* Manufacturing EEPROM programmed at factory */
0228 reg = <0x50>;
0229 };
0230
0231 rtc: rtc@51 {
0232 compatible = "nxp,pcf85263";
0233 reg = <0x51>;
0234 };
0235 };
0236
0237 &uart1 {
0238 pinctrl-names = "default";
0239 pinctrl-0 = <&pinctrl_uart1>;
0240 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
0241 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0242 uart-has-rtscts;
0243 status = "okay";
0244
0245 bluetooth {
0246 compatible = "brcm,bcm43438-bt";
0247 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
0248 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
0249 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
0250 clocks = <&osc_32k>;
0251 max-speed = <4000000>;
0252 clock-names = "extclk";
0253 };
0254 };
0255
0256 &usdhc1 {
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0260 pinctrl-0 = <&pinctrl_usdhc1>;
0261 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0262 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0263 bus-width = <4>;
0264 non-removable;
0265 cap-power-off-card;
0266 keep-power-in-suspend;
0267 mmc-pwrseq = <&usdhc1_pwrseq>;
0268 status = "okay";
0269
0270 brcmf: bcrmf@1 {
0271 reg = <1>;
0272 compatible = "brcm,bcm4329-fmac";
0273 pinctrl-names = "default";
0274 pinctrl-0 = <&pinctrl_wlan>;
0275 interrupt-parent = <&gpio2>;
0276 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
0277 interrupt-names = "host-wake";
0278 };
0279 };
0280
0281 &usdhc3 {
0282 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0283 pinctrl-0 = <&pinctrl_usdhc3>;
0284 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0285 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0286 bus-width = <8>;
0287 non-removable;
0288 status = "okay";
0289 };
0290
0291 &wdog1 {
0292 pinctrl-names = "default";
0293 pinctrl-0 = <&pinctrl_wdog>;
0294 fsl,ext-reset-output;
0295 status = "okay";
0296 };
0297
0298 &iomuxc {
0299 pinctrl_fec1: fec1grp {
0300 fsl,pins = <
0301 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0302 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0303 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0304 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0305 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0306 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0307 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0308 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0309 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0310 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0311 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0312 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0313 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0314 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0315 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
0316 >;
0317 };
0318
0319 pinctrl_i2c1: i2c1grp {
0320 fsl,pins = <
0321 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0322 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0323 >;
0324 };
0325
0326 pinctrl_i2c3: i2c3grp {
0327 fsl,pins = <
0328 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0329 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0330 >;
0331 };
0332
0333 pinctrl_flexspi: flexspigrp {
0334 fsl,pins = <
0335 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0336 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0337 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0338 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0339 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0340 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0341 >;
0342 };
0343
0344 pinctrl_pmic: pmicirqgrp {
0345 fsl,pins = <
0346 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
0347 >;
0348 };
0349
0350 pinctrl_uart1: uart1grp {
0351 fsl,pins = <
0352 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0353 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0354 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
0355 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
0356 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
0357 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
0358 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
0359 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
0360 >;
0361 };
0362
0363 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
0364 fsl,pins = <
0365 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
0366 >;
0367 };
0368
0369 pinctrl_usdhc1: usdhc1grp {
0370 fsl,pins = <
0371 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0372 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0373 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0374 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0375 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0376 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0377 >;
0378 };
0379
0380 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0381 fsl,pins = <
0382 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0383 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0384 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0385 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0386 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0387 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0388 >;
0389 };
0390
0391 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0392 fsl,pins = <
0393 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0394 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0395 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0396 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0397 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0398 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0399 >;
0400 };
0401
0402 pinctrl_usdhc3: usdhc3grp {
0403 fsl,pins = <
0404 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0405 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0406 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0407 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0408 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0409 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0410 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0411 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0412 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0413 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0414 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0415 >;
0416 };
0417
0418 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0419 fsl,pins = <
0420 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0421 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0422 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0423 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0424 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0425 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0426 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0427 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0428 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0429 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0430 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0431 >;
0432 };
0433
0434 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0435 fsl,pins = <
0436 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0437 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0438 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0439 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0440 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0441 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0442 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0443 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0444 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0445 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0446 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0447 >;
0448 };
0449
0450 pinctrl_wdog: wdoggrp {
0451 fsl,pins = <
0452 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
0453 >;
0454 };
0455
0456 pinctrl_wlan: wlangrp {
0457 fsl,pins = <
0458 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
0459 >;
0460 };
0461 };
