0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2020 Compass Electronics Group, LLC
0004 */
0005
0006 #include <dt-bindings/phy/phy-imx8-pcie.h>
0007
0008 / {
0009 leds {
0010 compatible = "gpio-leds";
0011
0012 led0 {
0013 label = "gen_led0";
0014 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
0015 default-state = "off";
0016 };
0017
0018 led1 {
0019 label = "gen_led1";
0020 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
0021 default-state = "off";
0022 };
0023
0024 led2 {
0025 label = "gen_led2";
0026 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
0027 default-state = "off";
0028 };
0029
0030 led3 {
0031 pinctrl-names = "default";
0032 pinctrl-0 = <&pinctrl_led3>;
0033 label = "heartbeat";
0034 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0035 linux,default-trigger = "heartbeat";
0036 };
0037 };
0038
0039 pcie0_refclk: pcie0-refclk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <100000000>;
0043 };
0044
0045 pcie0_refclk_gated: pcie0-refclk-gated {
0046 compatible = "gpio-gate-clock";
0047 clocks = <&pcie0_refclk>;
0048 #clock-cells = <0>;
0049 enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
0050 };
0051
0052 reg_audio: regulator-audio {
0053 compatible = "regulator-fixed";
0054 regulator-name = "3v3_aud";
0055 regulator-min-microvolt = <3300000>;
0056 regulator-max-microvolt = <3300000>;
0057 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
0058 enable-active-high;
0059 };
0060
0061 reg_usbotg1: regulator-usbotg1 {
0062 compatible = "regulator-fixed";
0063 pinctrl-names = "default";
0064 pinctrl-0 = <&pinctrl_reg_usb_otg1>;
0065 regulator-name = "usb_otg_vbus";
0066 regulator-min-microvolt = <5000000>;
0067 regulator-max-microvolt = <5000000>;
0068 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
0069 enable-active-high;
0070 };
0071
0072 reg_camera: regulator-camera {
0073 compatible = "regulator-fixed";
0074 regulator-name = "mipi_pwr";
0075 regulator-min-microvolt = <2800000>;
0076 regulator-max-microvolt = <2800000>;
0077 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
0078 enable-active-high;
0079 startup-delay-us = <100000>;
0080 };
0081
0082 reg_pcie0: regulator-pcie {
0083 compatible = "regulator-fixed";
0084 regulator-name = "pci_pwr_en";
0085 regulator-min-microvolt = <3300000>;
0086 regulator-max-microvolt = <3300000>;
0087 enable-active-high;
0088 gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
0089 startup-delay-us = <100000>;
0090 };
0091
0092 reg_usdhc2_vmmc: regulator-usdhc2 {
0093 compatible = "regulator-fixed";
0094 regulator-name = "VSD_3V3";
0095 regulator-min-microvolt = <3300000>;
0096 regulator-max-microvolt = <3300000>;
0097 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0098 enable-active-high;
0099 };
0100
0101 sound {
0102 compatible = "fsl,imx-audio-wm8962";
0103 model = "wm8962-audio";
0104 audio-cpu = <&sai3>;
0105 audio-codec = <&wm8962>;
0106 audio-routing =
0107 "Headphone Jack", "HPOUTL",
0108 "Headphone Jack", "HPOUTR",
0109 "Ext Spk", "SPKOUTL",
0110 "Ext Spk", "SPKOUTR",
0111 "AMIC", "MICBIAS",
0112 "IN3R", "AMIC";
0113 };
0114 };
0115
0116 &csi {
0117 status = "okay";
0118 };
0119
0120 &ecspi2 {
0121 pinctrl-names = "default";
0122 pinctrl-0 = <&pinctrl_espi2>;
0123 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0124 status = "okay";
0125
0126 eeprom@0 {
0127 compatible = "microchip,at25160bn", "atmel,at25";
0128 reg = <0>;
0129 spi-max-frequency = <5000000>;
0130 spi-cpha;
0131 spi-cpol;
0132 pagesize = <32>;
0133 size = <2048>;
0134 address-width = <16>;
0135 };
0136 };
0137
0138 &i2c2 {
0139 clock-frequency = <400000>;
0140 pinctrl-names = "default";
0141 pinctrl-0 = <&pinctrl_i2c2>;
0142 status = "okay";
0143
0144 camera@3c {
0145 compatible = "ovti,ov5640";
0146 pinctrl-names = "default";
0147 pinctrl-0 = <&pinctrl_ov5640>;
0148 reg = <0x3c>;
0149 clocks = <&clk IMX8MM_CLK_CLKO1>;
0150 clock-names = "xclk";
0151 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
0152 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
0153 assigned-clock-rates = <24000000>;
0154 AVDD-supply = <®_camera>; /* 2.8v */
0155 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
0156 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
0157
0158 port {
0159 /* MIPI CSI-2 bus endpoint */
0160 ov5640_to_mipi_csi2: endpoint {
0161 remote-endpoint = <&imx8mm_mipi_csi_in>;
0162 clock-lanes = <0>;
0163 data-lanes = <1 2>;
0164 };
0165 };
0166 };
0167 };
0168
0169 &i2c4 {
0170 clock-frequency = <400000>;
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_i2c4>;
0173 status = "okay";
0174
0175 wm8962: audio-codec@1a {
0176 compatible = "wlf,wm8962";
0177 reg = <0x1a>;
0178 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
0179 DCVDD-supply = <®_audio>;
0180 DBVDD-supply = <®_audio>;
0181 AVDD-supply = <®_audio>;
0182 CPVDD-supply = <®_audio>;
0183 MICVDD-supply = <®_audio>;
0184 PLLVDD-supply = <®_audio>;
0185 SPKVDD1-supply = <®_audio>;
0186 SPKVDD2-supply = <®_audio>;
0187 gpio-cfg = <
0188 0x0000 /* 0:Default */
0189 0x0000 /* 1:Default */
0190 0x0000 /* 2:FN_DMICCLK */
0191 0x0000 /* 3:Default */
0192 0x0000 /* 4:FN_DMICCDAT */
0193 0x0000 /* 5:Default */
0194 >;
0195 };
0196
0197 pca6416_0: gpio@20 {
0198 compatible = "nxp,pcal6416";
0199 reg = <0x20>;
0200 pinctrl-names = "default";
0201 pinctrl-0 = <&pinctrl_pcal6414>;
0202 gpio-controller;
0203 #gpio-cells = <2>;
0204 interrupt-parent = <&gpio4>;
0205 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
0206 };
0207
0208 pca6416_1: gpio@21 {
0209 compatible = "nxp,pcal6416";
0210 reg = <0x21>;
0211 gpio-controller;
0212 #gpio-cells = <2>;
0213 interrupt-parent = <&gpio4>;
0214 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
0215 };
0216 };
0217
0218 &mipi_csi {
0219 status = "okay";
0220 ports {
0221 port@0 {
0222 imx8mm_mipi_csi_in: endpoint {
0223 remote-endpoint = <&ov5640_to_mipi_csi2>;
0224 data-lanes = <1 2>;
0225 };
0226 };
0227 };
0228 };
0229
0230 &pcie_phy {
0231 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0232 fsl,tx-deemph-gen1 = <0x2d>;
0233 fsl,tx-deemph-gen2 = <0xf>;
0234 fsl,clkreq-unsupported;
0235 clocks = <&pcie0_refclk_gated>;
0236 clock-names = "ref";
0237 status = "okay";
0238 };
0239
0240 &pcie0 {
0241 pinctrl-names = "default";
0242 pinctrl-0 = <&pinctrl_pcie0>;
0243 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
0244 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0245 <&pcie0_refclk_gated>;
0246 clock-names = "pcie", "pcie_aux", "pcie_bus";
0247 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0248 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0249 assigned-clock-rates = <10000000>, <250000000>;
0250 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0251 <&clk IMX8MM_SYS_PLL2_250M>;
0252 vpcie-supply = <®_pcie0>;
0253 status = "okay";
0254 };
0255
0256 &sai3 {
0257 pinctrl-names = "default";
0258 pinctrl-0 = <&pinctrl_sai3>;
0259 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
0260 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0261 assigned-clock-rates = <24576000>;
0262 fsl,sai-mclk-direction-output;
0263 status = "okay";
0264 };
0265
0266 &snvs_pwrkey {
0267 status = "okay";
0268 };
0269
0270 &uart2 { /* console */
0271 pinctrl-names = "default";
0272 pinctrl-0 = <&pinctrl_uart2>;
0273 status = "okay";
0274 };
0275
0276 &uart3 {
0277 pinctrl-names = "default";
0278 pinctrl-0 = <&pinctrl_uart3>;
0279 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
0280 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
0281 uart-has-rtscts;
0282 status = "okay";
0283 };
0284
0285 &usbotg1 {
0286 vbus-supply = <®_usbotg1>;
0287 disable-over-current;
0288 dr_mode = "otg";
0289 status = "okay";
0290 };
0291
0292 &usbotg2 {
0293 pinctrl-names = "default";
0294 disable-over-current;
0295 dr_mode = "host";
0296 status = "okay";
0297 };
0298
0299 &usbphynop2 {
0300 reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
0301 };
0302
0303 &usdhc2 {
0304 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0305 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0306 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0307 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0308 bus-width = <4>;
0309 vmmc-supply = <®_usdhc2_vmmc>;
0310 status = "okay";
0311 };
0312
0313 &iomuxc {
0314 pinctrl_espi2: espi2grp {
0315 fsl,pins = <
0316 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
0317 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
0318 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
0319 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
0320 >;
0321 };
0322
0323 pinctrl_i2c2: i2c2grp {
0324 fsl,pins = <
0325 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0326 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0327 >;
0328 };
0329
0330 pinctrl_i2c4: i2c4grp {
0331 fsl,pins = <
0332 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
0333 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
0334 >;
0335 };
0336
0337 pinctrl_led3: led3grp {
0338 fsl,pins = <
0339 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
0340 >;
0341 };
0342
0343 pinctrl_ov5640: ov5640grp {
0344 fsl,pins = <
0345 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
0346 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
0347 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
0348 >;
0349 };
0350
0351 pinctrl_pcal6414: pcal6414-gpiogrp {
0352 fsl,pins = <
0353 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
0354 >;
0355 };
0356
0357 pinctrl_reg_usb_otg1: usbotg1grp {
0358 fsl,pins = <
0359 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
0360 >;
0361 };
0362
0363 pinctrl_pcie0: pcie0grp {
0364 fsl,pins = <
0365 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
0366 >;
0367 };
0368
0369 pinctrl_sai3: sai3grp {
0370 fsl,pins = <
0371 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0372 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0373 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0374 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0375 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0376 >;
0377 };
0378
0379 pinctrl_uart2: uart2grp {
0380 fsl,pins = <
0381 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0382 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0383 >;
0384 };
0385
0386 pinctrl_uart3: uart3grp {
0387 fsl,pins = <
0388 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
0389 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
0390 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
0391 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
0392 >;
0393 };
0394
0395 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0396 fsl,pins = <
0397 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
0398 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0399 >;
0400 };
0401
0402 pinctrl_usdhc2: usdhc2grp {
0403 fsl,pins = <
0404 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0405 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0406 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0407 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0408 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0409 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0410 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0411 >;
0412 };
0413
0414 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0415 fsl,pins = <
0416 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0417 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0418 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0419 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0420 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0421 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0422 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0423 >;
0424 };
0425
0426 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0427 fsl,pins = <
0428 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0429 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0430 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0431 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0432 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0433 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0434 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0435 >;
0436 };
0437 };
