0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2020 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 #include <dt-bindings/clock/imx8-lpcg.h>
0008 #include <dt-bindings/firmware/imx/rsrc.h>
0009
0010 lsio_subsys: bus@5d000000 {
0011 compatible = "simple-bus";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
0015
0016 lsio_mem_clk: clock-lsio-mem {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 clock-frequency = <200000000>;
0020 clock-output-names = "lsio_mem_clk";
0021 };
0022
0023 lsio_bus_clk: clock-lsio-bus {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 clock-frequency = <100000000>;
0027 clock-output-names = "lsio_bus_clk";
0028 };
0029
0030 lsio_gpio0: gpio@5d080000 {
0031 reg = <0x5d080000 0x10000>;
0032 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0033 gpio-controller;
0034 #gpio-cells = <2>;
0035 interrupt-controller;
0036 #interrupt-cells = <2>;
0037 power-domains = <&pd IMX_SC_R_GPIO_0>;
0038 };
0039
0040 lsio_gpio1: gpio@5d090000 {
0041 reg = <0x5d090000 0x10000>;
0042 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
0043 gpio-controller;
0044 #gpio-cells = <2>;
0045 interrupt-controller;
0046 #interrupt-cells = <2>;
0047 power-domains = <&pd IMX_SC_R_GPIO_1>;
0048 };
0049
0050 lsio_gpio2: gpio@5d0a0000 {
0051 reg = <0x5d0a0000 0x10000>;
0052 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0053 gpio-controller;
0054 #gpio-cells = <2>;
0055 interrupt-controller;
0056 #interrupt-cells = <2>;
0057 power-domains = <&pd IMX_SC_R_GPIO_2>;
0058 };
0059
0060 lsio_gpio3: gpio@5d0b0000 {
0061 reg = <0x5d0b0000 0x10000>;
0062 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0063 gpio-controller;
0064 #gpio-cells = <2>;
0065 interrupt-controller;
0066 #interrupt-cells = <2>;
0067 power-domains = <&pd IMX_SC_R_GPIO_3>;
0068 };
0069
0070 lsio_gpio4: gpio@5d0c0000 {
0071 reg = <0x5d0c0000 0x10000>;
0072 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0073 gpio-controller;
0074 #gpio-cells = <2>;
0075 interrupt-controller;
0076 #interrupt-cells = <2>;
0077 power-domains = <&pd IMX_SC_R_GPIO_4>;
0078 };
0079
0080 lsio_gpio5: gpio@5d0d0000 {
0081 reg = <0x5d0d0000 0x10000>;
0082 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0083 gpio-controller;
0084 #gpio-cells = <2>;
0085 interrupt-controller;
0086 #interrupt-cells = <2>;
0087 power-domains = <&pd IMX_SC_R_GPIO_5>;
0088 };
0089
0090 lsio_gpio6: gpio@5d0e0000 {
0091 reg = <0x5d0e0000 0x10000>;
0092 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0093 gpio-controller;
0094 #gpio-cells = <2>;
0095 interrupt-controller;
0096 #interrupt-cells = <2>;
0097 power-domains = <&pd IMX_SC_R_GPIO_6>;
0098 };
0099
0100 lsio_gpio7: gpio@5d0f0000 {
0101 reg = <0x5d0f0000 0x10000>;
0102 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0103 gpio-controller;
0104 #gpio-cells = <2>;
0105 interrupt-controller;
0106 #interrupt-cells = <2>;
0107 power-domains = <&pd IMX_SC_R_GPIO_7>;
0108 };
0109
0110 lsio_mu0: mailbox@5d1b0000 {
0111 reg = <0x5d1b0000 0x10000>;
0112 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0113 #mbox-cells = <2>;
0114 status = "disabled";
0115 };
0116
0117 lsio_mu1: mailbox@5d1c0000 {
0118 reg = <0x5d1c0000 0x10000>;
0119 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
0120 #mbox-cells = <2>;
0121 };
0122
0123 lsio_mu2: mailbox@5d1d0000 {
0124 reg = <0x5d1d0000 0x10000>;
0125 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0126 #mbox-cells = <2>;
0127 status = "disabled";
0128 };
0129
0130 lsio_mu3: mailbox@5d1e0000 {
0131 reg = <0x5d1e0000 0x10000>;
0132 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0133 #mbox-cells = <2>;
0134 status = "disabled";
0135 };
0136
0137 lsio_mu4: mailbox@5d1f0000 {
0138 reg = <0x5d1f0000 0x10000>;
0139 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0140 #mbox-cells = <2>;
0141 status = "disabled";
0142 };
0143
0144 lsio_mu5: mailbox@5d200000 {
0145 reg = <0x5d200000 0x10000>;
0146 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0147 #mbox-cells = <2>;
0148 power-domains = <&pd IMX_SC_R_MU_5A>;
0149 status = "disabled";
0150 };
0151
0152 lsio_mu6: mailbox@5d210000 {
0153 reg = <0x5d210000 0x10000>;
0154 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0155 #mbox-cells = <2>;
0156 power-domains = <&pd IMX_SC_R_MU_6A>;
0157 status = "disabled";
0158 };
0159
0160 lsio_mu13: mailbox@5d280000 {
0161 reg = <0x5d280000 0x10000>;
0162 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0163 #mbox-cells = <2>;
0164 power-domains = <&pd IMX_SC_R_MU_13A>;
0165 };
0166
0167 /* LPCG clocks */
0168 pwm0_lpcg: clock-controller@5d400000 {
0169 compatible = "fsl,imx8qxp-lpcg";
0170 reg = <0x5d400000 0x10000>;
0171 #clock-cells = <1>;
0172 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
0173 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
0174 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
0175 <&lsio_bus_clk>,
0176 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
0177 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0178 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0179 <IMX_LPCG_CLK_6>;
0180 clock-output-names = "pwm0_lpcg_ipg_clk",
0181 "pwm0_lpcg_ipg_hf_clk",
0182 "pwm0_lpcg_ipg_s_clk",
0183 "pwm0_lpcg_ipg_slv_clk",
0184 "pwm0_lpcg_ipg_mstr_clk";
0185 power-domains = <&pd IMX_SC_R_PWM_0>;
0186 };
0187
0188 pwm1_lpcg: clock-controller@5d410000 {
0189 compatible = "fsl,imx8qxp-lpcg";
0190 reg = <0x5d410000 0x10000>;
0191 #clock-cells = <1>;
0192 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
0193 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
0194 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
0195 <&lsio_bus_clk>,
0196 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
0197 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0198 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0199 <IMX_LPCG_CLK_6>;
0200 clock-output-names = "pwm1_lpcg_ipg_clk",
0201 "pwm1_lpcg_ipg_hf_clk",
0202 "pwm1_lpcg_ipg_s_clk",
0203 "pwm1_lpcg_ipg_slv_clk",
0204 "pwm1_lpcg_ipg_mstr_clk";
0205 power-domains = <&pd IMX_SC_R_PWM_1>;
0206 };
0207
0208 pwm2_lpcg: clock-controller@5d420000 {
0209 compatible = "fsl,imx8qxp-lpcg";
0210 reg = <0x5d420000 0x10000>;
0211 #clock-cells = <1>;
0212 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
0213 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
0214 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
0215 <&lsio_bus_clk>,
0216 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
0217 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0218 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0219 <IMX_LPCG_CLK_6>;
0220 clock-output-names = "pwm2_lpcg_ipg_clk",
0221 "pwm2_lpcg_ipg_hf_clk",
0222 "pwm2_lpcg_ipg_s_clk",
0223 "pwm2_lpcg_ipg_slv_clk",
0224 "pwm2_lpcg_ipg_mstr_clk";
0225 power-domains = <&pd IMX_SC_R_PWM_2>;
0226 };
0227
0228 pwm3_lpcg: clock-controller@5d430000 {
0229 compatible = "fsl,imx8qxp-lpcg";
0230 reg = <0x5d430000 0x10000>;
0231 #clock-cells = <1>;
0232 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
0233 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
0234 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
0235 <&lsio_bus_clk>,
0236 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
0237 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0238 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0239 <IMX_LPCG_CLK_6>;
0240 clock-output-names = "pwm3_lpcg_ipg_clk",
0241 "pwm3_lpcg_ipg_hf_clk",
0242 "pwm3_lpcg_ipg_s_clk",
0243 "pwm3_lpcg_ipg_slv_clk",
0244 "pwm3_lpcg_ipg_mstr_clk";
0245 power-domains = <&pd IMX_SC_R_PWM_3>;
0246 };
0247
0248 pwm4_lpcg: clock-controller@5d440000 {
0249 compatible = "fsl,imx8qxp-lpcg";
0250 reg = <0x5d440000 0x10000>;
0251 #clock-cells = <1>;
0252 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
0253 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
0254 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
0255 <&lsio_bus_clk>,
0256 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
0257 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0258 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0259 <IMX_LPCG_CLK_6>;
0260 clock-output-names = "pwm4_lpcg_ipg_clk",
0261 "pwm4_lpcg_ipg_hf_clk",
0262 "pwm4_lpcg_ipg_s_clk",
0263 "pwm4_lpcg_ipg_slv_clk",
0264 "pwm4_lpcg_ipg_mstr_clk";
0265 power-domains = <&pd IMX_SC_R_PWM_4>;
0266 };
0267
0268 pwm5_lpcg: clock-controller@5d450000 {
0269 compatible = "fsl,imx8qxp-lpcg";
0270 reg = <0x5d450000 0x10000>;
0271 #clock-cells = <1>;
0272 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
0273 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
0274 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
0275 <&lsio_bus_clk>,
0276 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
0277 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0278 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0279 <IMX_LPCG_CLK_6>;
0280 clock-output-names = "pwm5_lpcg_ipg_clk",
0281 "pwm5_lpcg_ipg_hf_clk",
0282 "pwm5_lpcg_ipg_s_clk",
0283 "pwm5_lpcg_ipg_slv_clk",
0284 "pwm5_lpcg_ipg_mstr_clk";
0285 power-domains = <&pd IMX_SC_R_PWM_5>;
0286 };
0287
0288 pwm6_lpcg: clock-controller@5d460000 {
0289 compatible = "fsl,imx8qxp-lpcg";
0290 reg = <0x5d460000 0x10000>;
0291 #clock-cells = <1>;
0292 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
0293 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
0294 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
0295 <&lsio_bus_clk>,
0296 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
0297 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0298 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0299 <IMX_LPCG_CLK_6>;
0300 clock-output-names = "pwm6_lpcg_ipg_clk",
0301 "pwm6_lpcg_ipg_hf_clk",
0302 "pwm6_lpcg_ipg_s_clk",
0303 "pwm6_lpcg_ipg_slv_clk",
0304 "pwm6_lpcg_ipg_mstr_clk";
0305 power-domains = <&pd IMX_SC_R_PWM_6>;
0306 };
0307
0308 pwm7_lpcg: clock-controller@5d470000 {
0309 compatible = "fsl,imx8qxp-lpcg";
0310 reg = <0x5d470000 0x10000>;
0311 #clock-cells = <1>;
0312 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
0313 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
0314 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
0315 <&lsio_bus_clk>,
0316 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
0317 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0318 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0319 <IMX_LPCG_CLK_6>;
0320 clock-output-names = "pwm7_lpcg_ipg_clk",
0321 "pwm7_lpcg_ipg_hf_clk",
0322 "pwm7_lpcg_ipg_s_clk",
0323 "pwm7_lpcg_ipg_slv_clk",
0324 "pwm7_lpcg_ipg_mstr_clk";
0325 power-domains = <&pd IMX_SC_R_PWM_7>;
0326 };
0327 };
