0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2019-2021 NXP
0004 * Zhou Guoniu <guoniu.zhou@nxp.com>
0005 */
0006 img_subsys: bus@58000000 {
0007 compatible = "simple-bus";
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
0011
0012 img_ipg_clk: clock-img-ipg {
0013 compatible = "fixed-clock";
0014 #clock-cells = <0>;
0015 clock-frequency = <200000000>;
0016 clock-output-names = "img_ipg_clk";
0017 };
0018
0019 jpegdec: jpegdec@58400000 {
0020 reg = <0x58400000 0x00050000>;
0021 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
0022 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
0023 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
0024 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
0025 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
0026 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
0027 clock-names = "per", "ipg";
0028 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
0029 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
0030 assigned-clock-rates = <200000000>, <200000000>;
0031 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
0032 <&pd IMX_SC_R_MJPEG_DEC_S0>,
0033 <&pd IMX_SC_R_MJPEG_DEC_S1>,
0034 <&pd IMX_SC_R_MJPEG_DEC_S2>,
0035 <&pd IMX_SC_R_MJPEG_DEC_S3>;
0036 };
0037
0038 jpegenc: jpegenc@58450000 {
0039 reg = <0x58450000 0x00050000>;
0040 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
0041 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
0042 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
0043 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
0044 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
0045 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
0046 clock-names = "per", "ipg";
0047 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
0048 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
0049 assigned-clock-rates = <200000000>, <200000000>;
0050 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
0051 <&pd IMX_SC_R_MJPEG_ENC_S0>,
0052 <&pd IMX_SC_R_MJPEG_ENC_S1>,
0053 <&pd IMX_SC_R_MJPEG_ENC_S2>,
0054 <&pd IMX_SC_R_MJPEG_ENC_S3>;
0055 };
0056
0057 img_jpeg_dec_lpcg: clock-controller@585d0000 {
0058 compatible = "fsl,imx8qxp-lpcg";
0059 reg = <0x585d0000 0x10000>;
0060 #clock-cells = <1>;
0061 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
0062 clock-indices = <IMX_LPCG_CLK_0>,
0063 <IMX_LPCG_CLK_4>;
0064 clock-output-names = "img_jpeg_dec_lpcg_clk",
0065 "img_jpeg_dec_lpcg_ipg_clk";
0066 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
0067 };
0068
0069 img_jpeg_enc_lpcg: clock-controller@585f0000 {
0070 compatible = "fsl,imx8qxp-lpcg";
0071 reg = <0x585f0000 0x10000>;
0072 #clock-cells = <1>;
0073 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
0074 clock-indices = <IMX_LPCG_CLK_0>,
0075 <IMX_LPCG_CLK_4>;
0076 clock-output-names = "img_jpeg_enc_lpcg_clk",
0077 "img_jpeg_enc_lpcg_ipg_clk";
0078 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
0079 };
0080 };
