0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 #include <dt-bindings/clock/imx8-lpcg.h>
0008 #include <dt-bindings/firmware/imx/rsrc.h>
0009
0010 dma_subsys: bus@5a000000 {
0011 compatible = "simple-bus";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
0015
0016 dma_ipg_clk: clock-dma-ipg {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 clock-frequency = <120000000>;
0020 clock-output-names = "dma_ipg_clk";
0021 };
0022
0023 lpuart0: serial@5a060000 {
0024 reg = <0x5a060000 0x1000>;
0025 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
0026 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
0027 <&uart0_lpcg IMX_LPCG_CLK_0>;
0028 clock-names = "ipg", "baud";
0029 power-domains = <&pd IMX_SC_R_UART_0>;
0030 status = "disabled";
0031 };
0032
0033 lpuart1: serial@5a070000 {
0034 reg = <0x5a070000 0x1000>;
0035 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
0036 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
0037 <&uart1_lpcg IMX_LPCG_CLK_0>;
0038 clock-names = "ipg", "baud";
0039 power-domains = <&pd IMX_SC_R_UART_1>;
0040 status = "disabled";
0041 };
0042
0043 lpuart2: serial@5a080000 {
0044 reg = <0x5a080000 0x1000>;
0045 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0046 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
0047 <&uart2_lpcg IMX_LPCG_CLK_0>;
0048 clock-names = "ipg", "baud";
0049 power-domains = <&pd IMX_SC_R_UART_2>;
0050 status = "disabled";
0051 };
0052
0053 lpuart3: serial@5a090000 {
0054 reg = <0x5a090000 0x1000>;
0055 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
0056 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
0057 <&uart3_lpcg IMX_LPCG_CLK_0>;
0058 clock-names = "ipg", "baud";
0059 power-domains = <&pd IMX_SC_R_UART_3>;
0060 status = "disabled";
0061 };
0062
0063 uart0_lpcg: clock-controller@5a460000 {
0064 compatible = "fsl,imx8qxp-lpcg";
0065 reg = <0x5a460000 0x10000>;
0066 #clock-cells = <1>;
0067 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
0068 <&dma_ipg_clk>;
0069 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0070 clock-output-names = "uart0_lpcg_baud_clk",
0071 "uart0_lpcg_ipg_clk";
0072 power-domains = <&pd IMX_SC_R_UART_0>;
0073 };
0074
0075 uart1_lpcg: clock-controller@5a470000 {
0076 compatible = "fsl,imx8qxp-lpcg";
0077 reg = <0x5a470000 0x10000>;
0078 #clock-cells = <1>;
0079 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
0080 <&dma_ipg_clk>;
0081 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0082 clock-output-names = "uart1_lpcg_baud_clk",
0083 "uart1_lpcg_ipg_clk";
0084 power-domains = <&pd IMX_SC_R_UART_1>;
0085 };
0086
0087 uart2_lpcg: clock-controller@5a480000 {
0088 compatible = "fsl,imx8qxp-lpcg";
0089 reg = <0x5a480000 0x10000>;
0090 #clock-cells = <1>;
0091 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
0092 <&dma_ipg_clk>;
0093 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0094 clock-output-names = "uart2_lpcg_baud_clk",
0095 "uart2_lpcg_ipg_clk";
0096 power-domains = <&pd IMX_SC_R_UART_2>;
0097 };
0098
0099 uart3_lpcg: clock-controller@5a490000 {
0100 compatible = "fsl,imx8qxp-lpcg";
0101 reg = <0x5a490000 0x10000>;
0102 #clock-cells = <1>;
0103 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
0104 <&dma_ipg_clk>;
0105 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0106 clock-output-names = "uart3_lpcg_baud_clk",
0107 "uart3_lpcg_ipg_clk";
0108 power-domains = <&pd IMX_SC_R_UART_3>;
0109 };
0110
0111 i2c0: i2c@5a800000 {
0112 reg = <0x5a800000 0x4000>;
0113 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
0114 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
0115 clock-names = "per";
0116 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
0117 assigned-clock-rates = <24000000>;
0118 power-domains = <&pd IMX_SC_R_I2C_0>;
0119 status = "disabled";
0120 };
0121
0122 i2c1: i2c@5a810000 {
0123 reg = <0x5a810000 0x4000>;
0124 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0125 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
0126 clock-names = "per";
0127 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
0128 assigned-clock-rates = <24000000>;
0129 power-domains = <&pd IMX_SC_R_I2C_1>;
0130 status = "disabled";
0131 };
0132
0133 i2c2: i2c@5a820000 {
0134 reg = <0x5a820000 0x4000>;
0135 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
0136 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
0137 clock-names = "per";
0138 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
0139 assigned-clock-rates = <24000000>;
0140 power-domains = <&pd IMX_SC_R_I2C_2>;
0141 status = "disabled";
0142 };
0143
0144 i2c3: i2c@5a830000 {
0145 reg = <0x5a830000 0x4000>;
0146 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0147 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
0148 clock-names = "per";
0149 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
0150 assigned-clock-rates = <24000000>;
0151 power-domains = <&pd IMX_SC_R_I2C_3>;
0152 status = "disabled";
0153 };
0154
0155 i2c0_lpcg: clock-controller@5ac00000 {
0156 compatible = "fsl,imx8qxp-lpcg";
0157 reg = <0x5ac00000 0x10000>;
0158 #clock-cells = <1>;
0159 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
0160 <&dma_ipg_clk>;
0161 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0162 clock-output-names = "i2c0_lpcg_clk",
0163 "i2c0_lpcg_ipg_clk";
0164 power-domains = <&pd IMX_SC_R_I2C_0>;
0165 };
0166
0167 i2c1_lpcg: clock-controller@5ac10000 {
0168 compatible = "fsl,imx8qxp-lpcg";
0169 reg = <0x5ac10000 0x10000>;
0170 #clock-cells = <1>;
0171 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
0172 <&dma_ipg_clk>;
0173 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0174 clock-output-names = "i2c1_lpcg_clk",
0175 "i2c1_lpcg_ipg_clk";
0176 power-domains = <&pd IMX_SC_R_I2C_1>;
0177 };
0178
0179 i2c2_lpcg: clock-controller@5ac20000 {
0180 compatible = "fsl,imx8qxp-lpcg";
0181 reg = <0x5ac20000 0x10000>;
0182 #clock-cells = <1>;
0183 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
0184 <&dma_ipg_clk>;
0185 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0186 clock-output-names = "i2c2_lpcg_clk",
0187 "i2c2_lpcg_ipg_clk";
0188 power-domains = <&pd IMX_SC_R_I2C_2>;
0189 };
0190
0191 i2c3_lpcg: clock-controller@5ac30000 {
0192 compatible = "fsl,imx8qxp-lpcg";
0193 reg = <0x5ac30000 0x10000>;
0194 #clock-cells = <1>;
0195 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
0196 <&dma_ipg_clk>;
0197 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0198 clock-output-names = "i2c3_lpcg_clk",
0199 "i2c3_lpcg_ipg_clk";
0200 power-domains = <&pd IMX_SC_R_I2C_3>;
0201 };
0202 };
