0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 #include <dt-bindings/clock/imx8-lpcg.h>
0008 #include <dt-bindings/firmware/imx/rsrc.h>
0009
0010 conn_subsys: bus@5b000000 {
0011 compatible = "simple-bus";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
0015
0016 conn_axi_clk: clock-conn-axi {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 clock-frequency = <333333333>;
0020 clock-output-names = "conn_axi_clk";
0021 };
0022
0023 conn_ahb_clk: clock-conn-ahb {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 clock-frequency = <166666666>;
0027 clock-output-names = "conn_ahb_clk";
0028 };
0029
0030 conn_ipg_clk: clock-conn-ipg {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <83333333>;
0034 clock-output-names = "conn_ipg_clk";
0035 };
0036
0037 usdhc1: mmc@5b010000 {
0038 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
0039 reg = <0x5b010000 0x10000>;
0040 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
0041 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
0042 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
0043 clock-names = "ipg", "per", "ahb";
0044 power-domains = <&pd IMX_SC_R_SDHC_0>;
0045 status = "disabled";
0046 };
0047
0048 usdhc2: mmc@5b020000 {
0049 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
0050 reg = <0x5b020000 0x10000>;
0051 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
0052 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
0053 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
0054 clock-names = "ipg", "per", "ahb";
0055 power-domains = <&pd IMX_SC_R_SDHC_1>;
0056 fsl,tuning-start-tap = <20>;
0057 fsl,tuning-step = <2>;
0058 status = "disabled";
0059 };
0060
0061 usdhc3: mmc@5b030000 {
0062 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
0063 reg = <0x5b030000 0x10000>;
0064 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
0065 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
0066 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
0067 clock-names = "ipg", "per", "ahb";
0068 power-domains = <&pd IMX_SC_R_SDHC_2>;
0069 status = "disabled";
0070 };
0071
0072 fec1: ethernet@5b040000 {
0073 reg = <0x5b040000 0x10000>;
0074 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
0075 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
0076 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
0077 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
0078 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
0079 <&enet0_lpcg IMX_LPCG_CLK_2>,
0080 <&enet0_lpcg IMX_LPCG_CLK_3>,
0081 <&enet0_lpcg IMX_LPCG_CLK_0>;
0082 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
0083 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
0084 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
0085 assigned-clock-rates = <250000000>, <125000000>;
0086 fsl,num-tx-queues = <3>;
0087 fsl,num-rx-queues = <3>;
0088 power-domains = <&pd IMX_SC_R_ENET_0>;
0089 status = "disabled";
0090 };
0091
0092 fec2: ethernet@5b050000 {
0093 reg = <0x5b050000 0x10000>;
0094 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
0098 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
0099 <&enet1_lpcg IMX_LPCG_CLK_2>,
0100 <&enet1_lpcg IMX_LPCG_CLK_3>,
0101 <&enet1_lpcg IMX_LPCG_CLK_0>;
0102 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
0103 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
0104 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
0105 assigned-clock-rates = <250000000>, <125000000>;
0106 fsl,num-tx-queues = <3>;
0107 fsl,num-rx-queues = <3>;
0108 power-domains = <&pd IMX_SC_R_ENET_1>;
0109 status = "disabled";
0110 };
0111
0112 /* LPCG clocks */
0113 sdhc0_lpcg: clock-controller@5b200000 {
0114 compatible = "fsl,imx8qxp-lpcg";
0115 reg = <0x5b200000 0x10000>;
0116 #clock-cells = <1>;
0117 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
0118 <&conn_ipg_clk>, <&conn_axi_clk>;
0119 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
0120 <IMX_LPCG_CLK_5>;
0121 clock-output-names = "sdhc0_lpcg_per_clk",
0122 "sdhc0_lpcg_ipg_clk",
0123 "sdhc0_lpcg_ahb_clk";
0124 power-domains = <&pd IMX_SC_R_SDHC_0>;
0125 };
0126
0127 sdhc1_lpcg: clock-controller@5b210000 {
0128 compatible = "fsl,imx8qxp-lpcg";
0129 reg = <0x5b210000 0x10000>;
0130 #clock-cells = <1>;
0131 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
0132 <&conn_ipg_clk>, <&conn_axi_clk>;
0133 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
0134 <IMX_LPCG_CLK_5>;
0135 clock-output-names = "sdhc1_lpcg_per_clk",
0136 "sdhc1_lpcg_ipg_clk",
0137 "sdhc1_lpcg_ahb_clk";
0138 power-domains = <&pd IMX_SC_R_SDHC_1>;
0139 };
0140
0141 sdhc2_lpcg: clock-controller@5b220000 {
0142 compatible = "fsl,imx8qxp-lpcg";
0143 reg = <0x5b220000 0x10000>;
0144 #clock-cells = <1>;
0145 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
0146 <&conn_ipg_clk>, <&conn_axi_clk>;
0147 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
0148 <IMX_LPCG_CLK_5>;
0149 clock-output-names = "sdhc2_lpcg_per_clk",
0150 "sdhc2_lpcg_ipg_clk",
0151 "sdhc2_lpcg_ahb_clk";
0152 power-domains = <&pd IMX_SC_R_SDHC_2>;
0153 };
0154
0155 enet0_lpcg: clock-controller@5b230000 {
0156 compatible = "fsl,imx8qxp-lpcg";
0157 reg = <0x5b230000 0x10000>;
0158 #clock-cells = <1>;
0159 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
0160 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
0161 <&conn_axi_clk>,
0162 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
0163 <&conn_ipg_clk>,
0164 <&conn_ipg_clk>;
0165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0166 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
0167 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
0168 clock-output-names = "enet0_lpcg_timer_clk",
0169 "enet0_lpcg_txc_sampling_clk",
0170 "enet0_lpcg_ahb_clk",
0171 "enet0_lpcg_rgmii_txc_clk",
0172 "enet0_lpcg_ipg_clk",
0173 "enet0_lpcg_ipg_s_clk";
0174 power-domains = <&pd IMX_SC_R_ENET_0>;
0175 };
0176
0177 enet1_lpcg: clock-controller@5b240000 {
0178 compatible = "fsl,imx8qxp-lpcg";
0179 reg = <0x5b240000 0x10000>;
0180 #clock-cells = <1>;
0181 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
0182 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
0183 <&conn_axi_clk>,
0184 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
0185 <&conn_ipg_clk>,
0186 <&conn_ipg_clk>;
0187 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
0188 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
0189 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
0190 clock-output-names = "enet1_lpcg_timer_clk",
0191 "enet1_lpcg_txc_sampling_clk",
0192 "enet1_lpcg_ahb_clk",
0193 "enet1_lpcg_rgmii_txc_clk",
0194 "enet1_lpcg_ipg_clk",
0195 "enet1_lpcg_ipg_s_clk";
0196 power-domains = <&pd IMX_SC_R_ENET_1>;
0197 };
0198 };
