0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Device Tree Include file for Layerscape-LX2160A family SoC.
0004 //
0005 // Copyright 2018-2020 NXP
0006
0007 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/thermal/thermal.h>
0011
0012 /memreserve/ 0x80000000 0x00010000;
0013
0014 / {
0015 compatible = "fsl,lx2160a";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 rtc1 = &ftm_alarm0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 // 8 clusters having 2 Cortex-A72 cores each
0029 cpu0: cpu@0 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a72";
0032 enable-method = "psci";
0033 reg = <0x0>;
0034 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0035 d-cache-size = <0x8000>;
0036 d-cache-line-size = <64>;
0037 d-cache-sets = <128>;
0038 i-cache-size = <0xC000>;
0039 i-cache-line-size = <64>;
0040 i-cache-sets = <192>;
0041 next-level-cache = <&cluster0_l2>;
0042 cpu-idle-states = <&cpu_pw15>;
0043 #cooling-cells = <2>;
0044 };
0045
0046 cpu1: cpu@1 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a72";
0049 enable-method = "psci";
0050 reg = <0x1>;
0051 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0052 d-cache-size = <0x8000>;
0053 d-cache-line-size = <64>;
0054 d-cache-sets = <128>;
0055 i-cache-size = <0xC000>;
0056 i-cache-line-size = <64>;
0057 i-cache-sets = <192>;
0058 next-level-cache = <&cluster0_l2>;
0059 cpu-idle-states = <&cpu_pw15>;
0060 #cooling-cells = <2>;
0061 };
0062
0063 cpu100: cpu@100 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a72";
0066 enable-method = "psci";
0067 reg = <0x100>;
0068 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0069 d-cache-size = <0x8000>;
0070 d-cache-line-size = <64>;
0071 d-cache-sets = <128>;
0072 i-cache-size = <0xC000>;
0073 i-cache-line-size = <64>;
0074 i-cache-sets = <192>;
0075 next-level-cache = <&cluster1_l2>;
0076 cpu-idle-states = <&cpu_pw15>;
0077 #cooling-cells = <2>;
0078 };
0079
0080 cpu101: cpu@101 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a72";
0083 enable-method = "psci";
0084 reg = <0x101>;
0085 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0086 d-cache-size = <0x8000>;
0087 d-cache-line-size = <64>;
0088 d-cache-sets = <128>;
0089 i-cache-size = <0xC000>;
0090 i-cache-line-size = <64>;
0091 i-cache-sets = <192>;
0092 next-level-cache = <&cluster1_l2>;
0093 cpu-idle-states = <&cpu_pw15>;
0094 #cooling-cells = <2>;
0095 };
0096
0097 cpu200: cpu@200 {
0098 device_type = "cpu";
0099 compatible = "arm,cortex-a72";
0100 enable-method = "psci";
0101 reg = <0x200>;
0102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
0103 d-cache-size = <0x8000>;
0104 d-cache-line-size = <64>;
0105 d-cache-sets = <128>;
0106 i-cache-size = <0xC000>;
0107 i-cache-line-size = <64>;
0108 i-cache-sets = <192>;
0109 next-level-cache = <&cluster2_l2>;
0110 cpu-idle-states = <&cpu_pw15>;
0111 #cooling-cells = <2>;
0112 };
0113
0114 cpu201: cpu@201 {
0115 device_type = "cpu";
0116 compatible = "arm,cortex-a72";
0117 enable-method = "psci";
0118 reg = <0x201>;
0119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
0120 d-cache-size = <0x8000>;
0121 d-cache-line-size = <64>;
0122 d-cache-sets = <128>;
0123 i-cache-size = <0xC000>;
0124 i-cache-line-size = <64>;
0125 i-cache-sets = <192>;
0126 next-level-cache = <&cluster2_l2>;
0127 cpu-idle-states = <&cpu_pw15>;
0128 #cooling-cells = <2>;
0129 };
0130
0131 cpu300: cpu@300 {
0132 device_type = "cpu";
0133 compatible = "arm,cortex-a72";
0134 enable-method = "psci";
0135 reg = <0x300>;
0136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
0137 d-cache-size = <0x8000>;
0138 d-cache-line-size = <64>;
0139 d-cache-sets = <128>;
0140 i-cache-size = <0xC000>;
0141 i-cache-line-size = <64>;
0142 i-cache-sets = <192>;
0143 next-level-cache = <&cluster3_l2>;
0144 cpu-idle-states = <&cpu_pw15>;
0145 #cooling-cells = <2>;
0146 };
0147
0148 cpu301: cpu@301 {
0149 device_type = "cpu";
0150 compatible = "arm,cortex-a72";
0151 enable-method = "psci";
0152 reg = <0x301>;
0153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
0154 d-cache-size = <0x8000>;
0155 d-cache-line-size = <64>;
0156 d-cache-sets = <128>;
0157 i-cache-size = <0xC000>;
0158 i-cache-line-size = <64>;
0159 i-cache-sets = <192>;
0160 next-level-cache = <&cluster3_l2>;
0161 cpu-idle-states = <&cpu_pw15>;
0162 #cooling-cells = <2>;
0163 };
0164
0165 cpu400: cpu@400 {
0166 device_type = "cpu";
0167 compatible = "arm,cortex-a72";
0168 enable-method = "psci";
0169 reg = <0x400>;
0170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
0171 d-cache-size = <0x8000>;
0172 d-cache-line-size = <64>;
0173 d-cache-sets = <128>;
0174 i-cache-size = <0xC000>;
0175 i-cache-line-size = <64>;
0176 i-cache-sets = <192>;
0177 next-level-cache = <&cluster4_l2>;
0178 cpu-idle-states = <&cpu_pw15>;
0179 #cooling-cells = <2>;
0180 };
0181
0182 cpu401: cpu@401 {
0183 device_type = "cpu";
0184 compatible = "arm,cortex-a72";
0185 enable-method = "psci";
0186 reg = <0x401>;
0187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
0188 d-cache-size = <0x8000>;
0189 d-cache-line-size = <64>;
0190 d-cache-sets = <128>;
0191 i-cache-size = <0xC000>;
0192 i-cache-line-size = <64>;
0193 i-cache-sets = <192>;
0194 next-level-cache = <&cluster4_l2>;
0195 cpu-idle-states = <&cpu_pw15>;
0196 #cooling-cells = <2>;
0197 };
0198
0199 cpu500: cpu@500 {
0200 device_type = "cpu";
0201 compatible = "arm,cortex-a72";
0202 enable-method = "psci";
0203 reg = <0x500>;
0204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
0205 d-cache-size = <0x8000>;
0206 d-cache-line-size = <64>;
0207 d-cache-sets = <128>;
0208 i-cache-size = <0xC000>;
0209 i-cache-line-size = <64>;
0210 i-cache-sets = <192>;
0211 next-level-cache = <&cluster5_l2>;
0212 cpu-idle-states = <&cpu_pw15>;
0213 #cooling-cells = <2>;
0214 };
0215
0216 cpu501: cpu@501 {
0217 device_type = "cpu";
0218 compatible = "arm,cortex-a72";
0219 enable-method = "psci";
0220 reg = <0x501>;
0221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
0222 d-cache-size = <0x8000>;
0223 d-cache-line-size = <64>;
0224 d-cache-sets = <128>;
0225 i-cache-size = <0xC000>;
0226 i-cache-line-size = <64>;
0227 i-cache-sets = <192>;
0228 next-level-cache = <&cluster5_l2>;
0229 cpu-idle-states = <&cpu_pw15>;
0230 #cooling-cells = <2>;
0231 };
0232
0233 cpu600: cpu@600 {
0234 device_type = "cpu";
0235 compatible = "arm,cortex-a72";
0236 enable-method = "psci";
0237 reg = <0x600>;
0238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
0239 d-cache-size = <0x8000>;
0240 d-cache-line-size = <64>;
0241 d-cache-sets = <128>;
0242 i-cache-size = <0xC000>;
0243 i-cache-line-size = <64>;
0244 i-cache-sets = <192>;
0245 next-level-cache = <&cluster6_l2>;
0246 cpu-idle-states = <&cpu_pw15>;
0247 #cooling-cells = <2>;
0248 };
0249
0250 cpu601: cpu@601 {
0251 device_type = "cpu";
0252 compatible = "arm,cortex-a72";
0253 enable-method = "psci";
0254 reg = <0x601>;
0255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
0256 d-cache-size = <0x8000>;
0257 d-cache-line-size = <64>;
0258 d-cache-sets = <128>;
0259 i-cache-size = <0xC000>;
0260 i-cache-line-size = <64>;
0261 i-cache-sets = <192>;
0262 next-level-cache = <&cluster6_l2>;
0263 cpu-idle-states = <&cpu_pw15>;
0264 #cooling-cells = <2>;
0265 };
0266
0267 cpu700: cpu@700 {
0268 device_type = "cpu";
0269 compatible = "arm,cortex-a72";
0270 enable-method = "psci";
0271 reg = <0x700>;
0272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
0273 d-cache-size = <0x8000>;
0274 d-cache-line-size = <64>;
0275 d-cache-sets = <128>;
0276 i-cache-size = <0xC000>;
0277 i-cache-line-size = <64>;
0278 i-cache-sets = <192>;
0279 next-level-cache = <&cluster7_l2>;
0280 cpu-idle-states = <&cpu_pw15>;
0281 #cooling-cells = <2>;
0282 };
0283
0284 cpu701: cpu@701 {
0285 device_type = "cpu";
0286 compatible = "arm,cortex-a72";
0287 enable-method = "psci";
0288 reg = <0x701>;
0289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
0290 d-cache-size = <0x8000>;
0291 d-cache-line-size = <64>;
0292 d-cache-sets = <128>;
0293 i-cache-size = <0xC000>;
0294 i-cache-line-size = <64>;
0295 i-cache-sets = <192>;
0296 next-level-cache = <&cluster7_l2>;
0297 cpu-idle-states = <&cpu_pw15>;
0298 #cooling-cells = <2>;
0299 };
0300
0301 cluster0_l2: l2-cache0 {
0302 compatible = "cache";
0303 cache-size = <0x100000>;
0304 cache-line-size = <64>;
0305 cache-sets = <1024>;
0306 cache-level = <2>;
0307 };
0308
0309 cluster1_l2: l2-cache1 {
0310 compatible = "cache";
0311 cache-size = <0x100000>;
0312 cache-line-size = <64>;
0313 cache-sets = <1024>;
0314 cache-level = <2>;
0315 };
0316
0317 cluster2_l2: l2-cache2 {
0318 compatible = "cache";
0319 cache-size = <0x100000>;
0320 cache-line-size = <64>;
0321 cache-sets = <1024>;
0322 cache-level = <2>;
0323 };
0324
0325 cluster3_l2: l2-cache3 {
0326 compatible = "cache";
0327 cache-size = <0x100000>;
0328 cache-line-size = <64>;
0329 cache-sets = <1024>;
0330 cache-level = <2>;
0331 };
0332
0333 cluster4_l2: l2-cache4 {
0334 compatible = "cache";
0335 cache-size = <0x100000>;
0336 cache-line-size = <64>;
0337 cache-sets = <1024>;
0338 cache-level = <2>;
0339 };
0340
0341 cluster5_l2: l2-cache5 {
0342 compatible = "cache";
0343 cache-size = <0x100000>;
0344 cache-line-size = <64>;
0345 cache-sets = <1024>;
0346 cache-level = <2>;
0347 };
0348
0349 cluster6_l2: l2-cache6 {
0350 compatible = "cache";
0351 cache-size = <0x100000>;
0352 cache-line-size = <64>;
0353 cache-sets = <1024>;
0354 cache-level = <2>;
0355 };
0356
0357 cluster7_l2: l2-cache7 {
0358 compatible = "cache";
0359 cache-size = <0x100000>;
0360 cache-line-size = <64>;
0361 cache-sets = <1024>;
0362 cache-level = <2>;
0363 };
0364
0365 cpu_pw15: cpu-pw15 {
0366 compatible = "arm,idle-state";
0367 idle-state-name = "PW15";
0368 arm,psci-suspend-param = <0x0>;
0369 entry-latency-us = <2000>;
0370 exit-latency-us = <2000>;
0371 min-residency-us = <6000>;
0372 };
0373 };
0374
0375 gic: interrupt-controller@6000000 {
0376 compatible = "arm,gic-v3";
0377 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
0378 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
0379 // SGI_base)
0380 <0x0 0x0c0c0000 0 0x2000>, // GICC
0381 <0x0 0x0c0d0000 0 0x1000>, // GICH
0382 <0x0 0x0c0e0000 0 0x20000>; // GICV
0383 #interrupt-cells = <3>;
0384 #address-cells = <2>;
0385 #size-cells = <2>;
0386 ranges;
0387 interrupt-controller;
0388 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0389
0390 its: gic-its@6020000 {
0391 compatible = "arm,gic-v3-its";
0392 msi-controller;
0393 reg = <0x0 0x6020000 0 0x20000>;
0394 };
0395 };
0396
0397 timer {
0398 compatible = "arm,armv8-timer";
0399 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
0400 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
0401 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
0402 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
0403 };
0404
0405 pmu {
0406 compatible = "arm,cortex-a72-pmu";
0407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0408 };
0409
0410 psci {
0411 compatible = "arm,psci-0.2";
0412 method = "smc";
0413 };
0414
0415 memory@80000000 {
0416 // DRAM space - 1, size : 2 GB DRAM
0417 device_type = "memory";
0418 reg = <0x00000000 0x80000000 0 0x80000000>;
0419 };
0420
0421 ddr1: memory-controller@1080000 {
0422 compatible = "fsl,qoriq-memory-controller";
0423 reg = <0x0 0x1080000 0x0 0x1000>;
0424 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0425 little-endian;
0426 };
0427
0428 ddr2: memory-controller@1090000 {
0429 compatible = "fsl,qoriq-memory-controller";
0430 reg = <0x0 0x1090000 0x0 0x1000>;
0431 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0432 little-endian;
0433 };
0434
0435 // One clock unit-sysclk node which bootloader require during DT fix-up
0436 sysclk: sysclk {
0437 compatible = "fixed-clock";
0438 #clock-cells = <0>;
0439 clock-frequency = <100000000>; // fixed up by bootloader
0440 clock-output-names = "sysclk";
0441 };
0442
0443 thermal-zones {
0444 cluster6-7 {
0445 polling-delay-passive = <1000>;
0446 polling-delay = <5000>;
0447 thermal-sensors = <&tmu 0>;
0448
0449 trips {
0450 cluster6_7_alert: cluster6-7-alert {
0451 temperature = <85000>;
0452 hysteresis = <2000>;
0453 type = "passive";
0454 };
0455
0456 cluster6_7_crit: cluster6-7-crit {
0457 temperature = <95000>;
0458 hysteresis = <2000>;
0459 type = "critical";
0460 };
0461 };
0462
0463 cooling-maps {
0464 map0 {
0465 trip = <&cluster6_7_alert>;
0466 cooling-device =
0467 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0468 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0469 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0470 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0471 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0472 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0473 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0474 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0475 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0476 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0477 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0478 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0479 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0480 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0481 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0482 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0483 };
0484 };
0485 };
0486
0487 ddr-cluster5 {
0488 polling-delay-passive = <1000>;
0489 polling-delay = <5000>;
0490 thermal-sensors = <&tmu 1>;
0491
0492 trips {
0493 ddr-cluster5-alert {
0494 temperature = <85000>;
0495 hysteresis = <2000>;
0496 type = "passive";
0497 };
0498
0499 ddr-cluster5-crit {
0500 temperature = <95000>;
0501 hysteresis = <2000>;
0502 type = "critical";
0503 };
0504 };
0505 };
0506
0507 wriop {
0508 polling-delay-passive = <1000>;
0509 polling-delay = <5000>;
0510 thermal-sensors = <&tmu 2>;
0511
0512 trips {
0513 wriop-alert {
0514 temperature = <85000>;
0515 hysteresis = <2000>;
0516 type = "passive";
0517 };
0518
0519 wriop-crit {
0520 temperature = <95000>;
0521 hysteresis = <2000>;
0522 type = "critical";
0523 };
0524 };
0525 };
0526
0527 dce-qbman-hsio2 {
0528 polling-delay-passive = <1000>;
0529 polling-delay = <5000>;
0530 thermal-sensors = <&tmu 3>;
0531
0532 trips {
0533 dce-qbman-alert {
0534 temperature = <85000>;
0535 hysteresis = <2000>;
0536 type = "passive";
0537 };
0538
0539 dce-qbman-crit {
0540 temperature = <95000>;
0541 hysteresis = <2000>;
0542 type = "critical";
0543 };
0544 };
0545 };
0546
0547 ccn-dpaa-tbu {
0548 polling-delay-passive = <1000>;
0549 polling-delay = <5000>;
0550 thermal-sensors = <&tmu 4>;
0551
0552 trips {
0553 ccn-dpaa-alert {
0554 temperature = <85000>;
0555 hysteresis = <2000>;
0556 type = "passive";
0557 };
0558
0559 ccn-dpaa-crit {
0560 temperature = <95000>;
0561 hysteresis = <2000>;
0562 type = "critical";
0563 };
0564 };
0565 };
0566
0567 cluster4-hsio3 {
0568 polling-delay-passive = <1000>;
0569 polling-delay = <5000>;
0570 thermal-sensors = <&tmu 5>;
0571
0572 trips {
0573 clust4-hsio3-alert {
0574 temperature = <85000>;
0575 hysteresis = <2000>;
0576 type = "passive";
0577 };
0578
0579 clust4-hsio3-crit {
0580 temperature = <95000>;
0581 hysteresis = <2000>;
0582 type = "critical";
0583 };
0584 };
0585 };
0586
0587 cluster2-3 {
0588 polling-delay-passive = <1000>;
0589 polling-delay = <5000>;
0590 thermal-sensors = <&tmu 6>;
0591
0592 trips {
0593 cluster2-3-alert {
0594 temperature = <85000>;
0595 hysteresis = <2000>;
0596 type = "passive";
0597 };
0598
0599 cluster2-3-crit {
0600 temperature = <95000>;
0601 hysteresis = <2000>;
0602 type = "critical";
0603 };
0604 };
0605 };
0606 };
0607
0608 soc {
0609 compatible = "simple-bus";
0610 #address-cells = <2>;
0611 #size-cells = <2>;
0612 ranges;
0613 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
0614
0615 serdes_1: phy@1ea0000 {
0616 compatible = "fsl,lynx-28g";
0617 reg = <0x0 0x1ea0000 0x0 0x1e30>;
0618 #phy-cells = <1>;
0619 };
0620
0621 crypto: crypto@8000000 {
0622 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
0623 fsl,sec-era = <10>;
0624 #address-cells = <1>;
0625 #size-cells = <1>;
0626 ranges = <0x0 0x00 0x8000000 0x100000>;
0627 reg = <0x00 0x8000000 0x0 0x100000>;
0628 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0629 dma-coherent;
0630 status = "disabled";
0631
0632 sec_jr0: jr@10000 {
0633 compatible = "fsl,sec-v5.0-job-ring",
0634 "fsl,sec-v4.0-job-ring";
0635 reg = <0x10000 0x10000>;
0636 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0637 };
0638
0639 sec_jr1: jr@20000 {
0640 compatible = "fsl,sec-v5.0-job-ring",
0641 "fsl,sec-v4.0-job-ring";
0642 reg = <0x20000 0x10000>;
0643 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0644 };
0645
0646 sec_jr2: jr@30000 {
0647 compatible = "fsl,sec-v5.0-job-ring",
0648 "fsl,sec-v4.0-job-ring";
0649 reg = <0x30000 0x10000>;
0650 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0651 };
0652
0653 sec_jr3: jr@40000 {
0654 compatible = "fsl,sec-v5.0-job-ring",
0655 "fsl,sec-v4.0-job-ring";
0656 reg = <0x40000 0x10000>;
0657 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0658 };
0659 };
0660
0661 clockgen: clock-controller@1300000 {
0662 compatible = "fsl,lx2160a-clockgen";
0663 reg = <0 0x1300000 0 0xa0000>;
0664 #clock-cells = <2>;
0665 clocks = <&sysclk>;
0666 };
0667
0668 dcfg: syscon@1e00000 {
0669 compatible = "fsl,lx2160a-dcfg", "syscon";
0670 reg = <0x0 0x1e00000 0x0 0x10000>;
0671 little-endian;
0672 };
0673
0674 sfp: efuse@1e80000 {
0675 compatible = "fsl,ls1028a-sfp";
0676 reg = <0x0 0x1e80000 0x0 0x10000>;
0677 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0678 QORIQ_CLK_PLL_DIV(4)>;
0679 clock-names = "sfp";
0680 };
0681
0682 isc: syscon@1f70000 {
0683 compatible = "fsl,lx2160a-isc", "syscon";
0684 reg = <0x0 0x1f70000 0x0 0x10000>;
0685 little-endian;
0686 #address-cells = <1>;
0687 #size-cells = <1>;
0688 ranges = <0x0 0x0 0x1f70000 0x10000>;
0689
0690 extirq: interrupt-controller@14 {
0691 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
0692 #interrupt-cells = <2>;
0693 #address-cells = <0>;
0694 interrupt-controller;
0695 reg = <0x14 4>;
0696 interrupt-map =
0697 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0698 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0699 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0700 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0701 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0702 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0703 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0704 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0705 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0706 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0707 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0708 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0709 interrupt-map-mask = <0xf 0x0>;
0710 };
0711 };
0712
0713 tmu: tmu@1f80000 {
0714 compatible = "fsl,qoriq-tmu";
0715 reg = <0x0 0x1f80000 0x0 0x10000>;
0716 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0717 fsl,tmu-range = <0x800000e6 0x8001017d>;
0718 fsl,tmu-calibration =
0719 /* Calibration data group 1 */
0720 <0x00000000 0x00000035
0721 /* Calibration data group 2 */
0722 0x00000001 0x00000154>;
0723 little-endian;
0724 #thermal-sensor-cells = <1>;
0725 };
0726
0727 i2c0: i2c@2000000 {
0728 compatible = "fsl,vf610-i2c";
0729 #address-cells = <1>;
0730 #size-cells = <0>;
0731 reg = <0x0 0x2000000 0x0 0x10000>;
0732 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0733 clock-names = "i2c";
0734 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0735 QORIQ_CLK_PLL_DIV(16)>;
0736 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
0737 status = "disabled";
0738 };
0739
0740 i2c1: i2c@2010000 {
0741 compatible = "fsl,vf610-i2c";
0742 #address-cells = <1>;
0743 #size-cells = <0>;
0744 reg = <0x0 0x2010000 0x0 0x10000>;
0745 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0746 clock-names = "i2c";
0747 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0748 QORIQ_CLK_PLL_DIV(16)>;
0749 status = "disabled";
0750 };
0751
0752 i2c2: i2c@2020000 {
0753 compatible = "fsl,vf610-i2c";
0754 #address-cells = <1>;
0755 #size-cells = <0>;
0756 reg = <0x0 0x2020000 0x0 0x10000>;
0757 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0758 clock-names = "i2c";
0759 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0760 QORIQ_CLK_PLL_DIV(16)>;
0761 status = "disabled";
0762 };
0763
0764 i2c3: i2c@2030000 {
0765 compatible = "fsl,vf610-i2c";
0766 #address-cells = <1>;
0767 #size-cells = <0>;
0768 reg = <0x0 0x2030000 0x0 0x10000>;
0769 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0770 clock-names = "i2c";
0771 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0772 QORIQ_CLK_PLL_DIV(16)>;
0773 status = "disabled";
0774 };
0775
0776 i2c4: i2c@2040000 {
0777 compatible = "fsl,vf610-i2c";
0778 #address-cells = <1>;
0779 #size-cells = <0>;
0780 reg = <0x0 0x2040000 0x0 0x10000>;
0781 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0782 clock-names = "i2c";
0783 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0784 QORIQ_CLK_PLL_DIV(16)>;
0785 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
0786 status = "disabled";
0787 };
0788
0789 i2c5: i2c@2050000 {
0790 compatible = "fsl,vf610-i2c";
0791 #address-cells = <1>;
0792 #size-cells = <0>;
0793 reg = <0x0 0x2050000 0x0 0x10000>;
0794 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0795 clock-names = "i2c";
0796 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0797 QORIQ_CLK_PLL_DIV(16)>;
0798 status = "disabled";
0799 };
0800
0801 i2c6: i2c@2060000 {
0802 compatible = "fsl,vf610-i2c";
0803 #address-cells = <1>;
0804 #size-cells = <0>;
0805 reg = <0x0 0x2060000 0x0 0x10000>;
0806 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0807 clock-names = "i2c";
0808 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0809 QORIQ_CLK_PLL_DIV(16)>;
0810 status = "disabled";
0811 };
0812
0813 i2c7: i2c@2070000 {
0814 compatible = "fsl,vf610-i2c";
0815 #address-cells = <1>;
0816 #size-cells = <0>;
0817 reg = <0x0 0x2070000 0x0 0x10000>;
0818 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0819 clock-names = "i2c";
0820 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0821 QORIQ_CLK_PLL_DIV(16)>;
0822 status = "disabled";
0823 };
0824
0825 fspi: spi@20c0000 {
0826 compatible = "nxp,lx2160a-fspi";
0827 #address-cells = <1>;
0828 #size-cells = <0>;
0829 reg = <0x0 0x20c0000 0x0 0x10000>,
0830 <0x0 0x20000000 0x0 0x10000000>;
0831 reg-names = "fspi_base", "fspi_mmap";
0832 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0833 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0834 QORIQ_CLK_PLL_DIV(4)>,
0835 <&clockgen QORIQ_CLK_PLATFORM_PLL
0836 QORIQ_CLK_PLL_DIV(4)>;
0837 clock-names = "fspi_en", "fspi";
0838 status = "disabled";
0839 };
0840
0841 dspi0: spi@2100000 {
0842 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
0843 #address-cells = <1>;
0844 #size-cells = <0>;
0845 reg = <0x0 0x2100000 0x0 0x10000>;
0846 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0847 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0848 QORIQ_CLK_PLL_DIV(8)>;
0849 clock-names = "dspi";
0850 spi-num-chipselects = <5>;
0851 bus-num = <0>;
0852 status = "disabled";
0853 };
0854
0855 dspi1: spi@2110000 {
0856 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
0857 #address-cells = <1>;
0858 #size-cells = <0>;
0859 reg = <0x0 0x2110000 0x0 0x10000>;
0860 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0861 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0862 QORIQ_CLK_PLL_DIV(8)>;
0863 clock-names = "dspi";
0864 spi-num-chipselects = <5>;
0865 bus-num = <1>;
0866 status = "disabled";
0867 };
0868
0869 dspi2: spi@2120000 {
0870 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
0871 #address-cells = <1>;
0872 #size-cells = <0>;
0873 reg = <0x0 0x2120000 0x0 0x10000>;
0874 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
0875 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0876 QORIQ_CLK_PLL_DIV(8)>;
0877 clock-names = "dspi";
0878 spi-num-chipselects = <5>;
0879 bus-num = <2>;
0880 status = "disabled";
0881 };
0882
0883 esdhc0: esdhc@2140000 {
0884 compatible = "fsl,esdhc";
0885 reg = <0x0 0x2140000 0x0 0x10000>;
0886 interrupts = <0 28 0x4>; /* Level high type */
0887 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0888 QORIQ_CLK_PLL_DIV(2)>;
0889 dma-coherent;
0890 voltage-ranges = <1800 1800 3300 3300>;
0891 sdhci,auto-cmd12;
0892 little-endian;
0893 bus-width = <4>;
0894 status = "disabled";
0895 };
0896
0897 esdhc1: esdhc@2150000 {
0898 compatible = "fsl,esdhc";
0899 reg = <0x0 0x2150000 0x0 0x10000>;
0900 interrupts = <0 63 0x4>; /* Level high type */
0901 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0902 QORIQ_CLK_PLL_DIV(2)>;
0903 dma-coherent;
0904 voltage-ranges = <1800 1800 3300 3300>;
0905 sdhci,auto-cmd12;
0906 broken-cd;
0907 little-endian;
0908 bus-width = <4>;
0909 status = "disabled";
0910 };
0911
0912 can0: can@2180000 {
0913 compatible = "fsl,lx2160ar1-flexcan";
0914 reg = <0x0 0x2180000 0x0 0x10000>;
0915 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0917 QORIQ_CLK_PLL_DIV(8)>,
0918 <&clockgen QORIQ_CLK_SYSCLK 0>;
0919 clock-names = "ipg", "per";
0920 fsl,clk-source = /bits/ 8 <0>;
0921 status = "disabled";
0922 };
0923
0924 can1: can@2190000 {
0925 compatible = "fsl,lx2160ar1-flexcan";
0926 reg = <0x0 0x2190000 0x0 0x10000>;
0927 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0928 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0929 QORIQ_CLK_PLL_DIV(8)>,
0930 <&clockgen QORIQ_CLK_SYSCLK 0>;
0931 clock-names = "ipg", "per";
0932 fsl,clk-source = /bits/ 8 <0>;
0933 status = "disabled";
0934 };
0935
0936 uart0: serial@21c0000 {
0937 compatible = "arm,sbsa-uart","arm,pl011";
0938 reg = <0x0 0x21c0000 0x0 0x1000>;
0939 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0940 current-speed = <115200>;
0941 status = "disabled";
0942 };
0943
0944 uart1: serial@21d0000 {
0945 compatible = "arm,sbsa-uart","arm,pl011";
0946 reg = <0x0 0x21d0000 0x0 0x1000>;
0947 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0948 current-speed = <115200>;
0949 status = "disabled";
0950 };
0951
0952 uart2: serial@21e0000 {
0953 compatible = "arm,sbsa-uart","arm,pl011";
0954 reg = <0x0 0x21e0000 0x0 0x1000>;
0955 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0956 current-speed = <115200>;
0957 status = "disabled";
0958 };
0959
0960 uart3: serial@21f0000 {
0961 compatible = "arm,sbsa-uart","arm,pl011";
0962 reg = <0x0 0x21f0000 0x0 0x1000>;
0963 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0964 current-speed = <115200>;
0965 status = "disabled";
0966 };
0967
0968 gpio0: gpio@2300000 {
0969 compatible = "fsl,qoriq-gpio";
0970 reg = <0x0 0x2300000 0x0 0x10000>;
0971 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0972 gpio-controller;
0973 little-endian;
0974 #gpio-cells = <2>;
0975 interrupt-controller;
0976 #interrupt-cells = <2>;
0977 };
0978
0979 gpio1: gpio@2310000 {
0980 compatible = "fsl,qoriq-gpio";
0981 reg = <0x0 0x2310000 0x0 0x10000>;
0982 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0983 gpio-controller;
0984 little-endian;
0985 #gpio-cells = <2>;
0986 interrupt-controller;
0987 #interrupt-cells = <2>;
0988 };
0989
0990 gpio2: gpio@2320000 {
0991 compatible = "fsl,qoriq-gpio";
0992 reg = <0x0 0x2320000 0x0 0x10000>;
0993 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0994 gpio-controller;
0995 little-endian;
0996 #gpio-cells = <2>;
0997 interrupt-controller;
0998 #interrupt-cells = <2>;
0999 };
1000
1001 gpio3: gpio@2330000 {
1002 compatible = "fsl,qoriq-gpio";
1003 reg = <0x0 0x2330000 0x0 0x10000>;
1004 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1005 gpio-controller;
1006 little-endian;
1007 #gpio-cells = <2>;
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1010 };
1011
1012 watchdog@23a0000 {
1013 compatible = "arm,sbsa-gwdt";
1014 reg = <0x0 0x23a0000 0 0x1000>,
1015 <0x0 0x2390000 0 0x1000>;
1016 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1017 timeout-sec = <30>;
1018 };
1019
1020 rcpm: power-controller@1e34040 {
1021 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1022 reg = <0x0 0x1e34040 0x0 0x1c>;
1023 #fsl,rcpm-wakeup-cells = <7>;
1024 little-endian;
1025 };
1026
1027 ftm_alarm0: timer@2800000 {
1028 compatible = "fsl,lx2160a-ftm-alarm";
1029 reg = <0x0 0x2800000 0x0 0x10000>;
1030 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1031 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1032 };
1033
1034 usb0: usb@3100000 {
1035 compatible = "snps,dwc3";
1036 reg = <0x0 0x3100000 0x0 0x10000>;
1037 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1038 dr_mode = "host";
1039 snps,quirk-frame-length-adjustment = <0x20>;
1040 usb3-lpm-capable;
1041 snps,dis_rxdet_inp3_quirk;
1042 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1043 status = "disabled";
1044 };
1045
1046 usb1: usb@3110000 {
1047 compatible = "snps,dwc3";
1048 reg = <0x0 0x3110000 0x0 0x10000>;
1049 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1050 dr_mode = "host";
1051 snps,quirk-frame-length-adjustment = <0x20>;
1052 usb3-lpm-capable;
1053 snps,dis_rxdet_inp3_quirk;
1054 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1055 status = "disabled";
1056 };
1057
1058 sata0: sata@3200000 {
1059 compatible = "fsl,lx2160a-ahci";
1060 reg = <0x0 0x3200000 0x0 0x10000>,
1061 <0x7 0x100520 0x0 0x4>;
1062 reg-names = "ahci", "sata-ecc";
1063 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1065 QORIQ_CLK_PLL_DIV(4)>;
1066 dma-coherent;
1067 status = "disabled";
1068 };
1069
1070 sata1: sata@3210000 {
1071 compatible = "fsl,lx2160a-ahci";
1072 reg = <0x0 0x3210000 0x0 0x10000>,
1073 <0x7 0x100520 0x0 0x4>;
1074 reg-names = "ahci", "sata-ecc";
1075 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1077 QORIQ_CLK_PLL_DIV(4)>;
1078 dma-coherent;
1079 status = "disabled";
1080 };
1081
1082 sata2: sata@3220000 {
1083 compatible = "fsl,lx2160a-ahci";
1084 reg = <0x0 0x3220000 0x0 0x10000>,
1085 <0x7 0x100520 0x0 0x4>;
1086 reg-names = "ahci", "sata-ecc";
1087 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1089 QORIQ_CLK_PLL_DIV(4)>;
1090 dma-coherent;
1091 status = "disabled";
1092 };
1093
1094 sata3: sata@3230000 {
1095 compatible = "fsl,lx2160a-ahci";
1096 reg = <0x0 0x3230000 0x0 0x10000>,
1097 <0x7 0x100520 0x0 0x4>;
1098 reg-names = "ahci", "sata-ecc";
1099 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1101 QORIQ_CLK_PLL_DIV(4)>;
1102 dma-coherent;
1103 status = "disabled";
1104 };
1105
1106 pcie1: pcie@3400000 {
1107 compatible = "fsl,lx2160a-pcie";
1108 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1109 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1110 reg-names = "csr_axi_slave", "config_axi_slave";
1111 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1112 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1113 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1114 interrupt-names = "aer", "pme", "intr";
1115 #address-cells = <3>;
1116 #size-cells = <2>;
1117 device_type = "pci";
1118 dma-coherent;
1119 apio-wins = <8>;
1120 ppio-wins = <8>;
1121 bus-range = <0x0 0xff>;
1122 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1123 msi-parent = <&its>;
1124 #interrupt-cells = <1>;
1125 interrupt-map-mask = <0 0 0 7>;
1126 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1127 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1128 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1129 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1130 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1131 status = "disabled";
1132 };
1133
1134 pcie2: pcie@3500000 {
1135 compatible = "fsl,lx2160a-pcie";
1136 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1137 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1138 reg-names = "csr_axi_slave", "config_axi_slave";
1139 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1140 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1142 interrupt-names = "aer", "pme", "intr";
1143 #address-cells = <3>;
1144 #size-cells = <2>;
1145 device_type = "pci";
1146 dma-coherent;
1147 apio-wins = <8>;
1148 ppio-wins = <8>;
1149 bus-range = <0x0 0xff>;
1150 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1151 msi-parent = <&its>;
1152 #interrupt-cells = <1>;
1153 interrupt-map-mask = <0 0 0 7>;
1154 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1155 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1156 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1157 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1158 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1159 status = "disabled";
1160 };
1161
1162 pcie3: pcie@3600000 {
1163 compatible = "fsl,lx2160a-pcie";
1164 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1165 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1166 reg-names = "csr_axi_slave", "config_axi_slave";
1167 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1168 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1169 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1170 interrupt-names = "aer", "pme", "intr";
1171 #address-cells = <3>;
1172 #size-cells = <2>;
1173 device_type = "pci";
1174 dma-coherent;
1175 apio-wins = <256>;
1176 ppio-wins = <24>;
1177 bus-range = <0x0 0xff>;
1178 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1179 msi-parent = <&its>;
1180 #interrupt-cells = <1>;
1181 interrupt-map-mask = <0 0 0 7>;
1182 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1183 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1184 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1185 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1186 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1187 status = "disabled";
1188 };
1189
1190 pcie4: pcie@3700000 {
1191 compatible = "fsl,lx2160a-pcie";
1192 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1193 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1194 reg-names = "csr_axi_slave", "config_axi_slave";
1195 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1196 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1197 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1198 interrupt-names = "aer", "pme", "intr";
1199 #address-cells = <3>;
1200 #size-cells = <2>;
1201 device_type = "pci";
1202 dma-coherent;
1203 apio-wins = <8>;
1204 ppio-wins = <8>;
1205 bus-range = <0x0 0xff>;
1206 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1207 msi-parent = <&its>;
1208 #interrupt-cells = <1>;
1209 interrupt-map-mask = <0 0 0 7>;
1210 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1211 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1212 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1213 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1214 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1215 status = "disabled";
1216 };
1217
1218 pcie5: pcie@3800000 {
1219 compatible = "fsl,lx2160a-pcie";
1220 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1221 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1222 reg-names = "csr_axi_slave", "config_axi_slave";
1223 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1224 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1225 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1226 interrupt-names = "aer", "pme", "intr";
1227 #address-cells = <3>;
1228 #size-cells = <2>;
1229 device_type = "pci";
1230 dma-coherent;
1231 apio-wins = <256>;
1232 ppio-wins = <24>;
1233 bus-range = <0x0 0xff>;
1234 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1235 msi-parent = <&its>;
1236 #interrupt-cells = <1>;
1237 interrupt-map-mask = <0 0 0 7>;
1238 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1239 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1240 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1241 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1242 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1243 status = "disabled";
1244 };
1245
1246 pcie6: pcie@3900000 {
1247 compatible = "fsl,lx2160a-pcie";
1248 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1249 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1250 reg-names = "csr_axi_slave", "config_axi_slave";
1251 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1252 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1253 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1254 interrupt-names = "aer", "pme", "intr";
1255 #address-cells = <3>;
1256 #size-cells = <2>;
1257 device_type = "pci";
1258 dma-coherent;
1259 apio-wins = <8>;
1260 ppio-wins = <8>;
1261 bus-range = <0x0 0xff>;
1262 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1263 msi-parent = <&its>;
1264 #interrupt-cells = <1>;
1265 interrupt-map-mask = <0 0 0 7>;
1266 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1267 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1268 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1269 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1270 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1271 status = "disabled";
1272 };
1273
1274 smmu: iommu@5000000 {
1275 compatible = "arm,mmu-500";
1276 reg = <0 0x5000000 0 0x800000>;
1277 #iommu-cells = <1>;
1278 #global-interrupts = <14>;
1279 // global secure fault
1280 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1281 // combined secure
1282 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1283 // global non-secure fault
1284 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1285 // combined non-secure
1286 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1287 // performance counter interrupts 0-9
1288 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1298 // per context interrupt, 64 interrupts
1299 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1312 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1313 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1363 dma-coherent;
1364 };
1365
1366 console@8340020 {
1367 compatible = "fsl,dpaa2-console";
1368 reg = <0x00000000 0x08340020 0 0x2>;
1369 };
1370
1371 ptp-timer@8b95000 {
1372 compatible = "fsl,dpaa2-ptp";
1373 reg = <0x0 0x8b95000 0x0 0x100>;
1374 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1375 QORIQ_CLK_PLL_DIV(2)>;
1376 little-endian;
1377 fsl,extts-fifo;
1378 };
1379
1380 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1381 emdio1: mdio@8b96000 {
1382 compatible = "fsl,fman-memac-mdio";
1383 reg = <0x0 0x8b96000 0x0 0x1000>;
1384 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 little-endian;
1388 status = "disabled";
1389 };
1390
1391 emdio2: mdio@8b97000 {
1392 compatible = "fsl,fman-memac-mdio";
1393 reg = <0x0 0x8b97000 0x0 0x1000>;
1394 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1395 little-endian;
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1398 status = "disabled";
1399 };
1400
1401 pcs_mdio1: mdio@8c07000 {
1402 compatible = "fsl,fman-memac-mdio";
1403 reg = <0x0 0x8c07000 0x0 0x1000>;
1404 little-endian;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 status = "disabled";
1408
1409 pcs1: ethernet-phy@0 {
1410 reg = <0>;
1411 };
1412 };
1413
1414 pcs_mdio2: mdio@8c0b000 {
1415 compatible = "fsl,fman-memac-mdio";
1416 reg = <0x0 0x8c0b000 0x0 0x1000>;
1417 little-endian;
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 status = "disabled";
1421
1422 pcs2: ethernet-phy@0 {
1423 reg = <0>;
1424 };
1425 };
1426
1427 pcs_mdio3: mdio@8c0f000 {
1428 compatible = "fsl,fman-memac-mdio";
1429 reg = <0x0 0x8c0f000 0x0 0x1000>;
1430 little-endian;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433 status = "disabled";
1434
1435 pcs3: ethernet-phy@0 {
1436 reg = <0>;
1437 };
1438 };
1439
1440 pcs_mdio4: mdio@8c13000 {
1441 compatible = "fsl,fman-memac-mdio";
1442 reg = <0x0 0x8c13000 0x0 0x1000>;
1443 little-endian;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 status = "disabled";
1447
1448 pcs4: ethernet-phy@0 {
1449 reg = <0>;
1450 };
1451 };
1452
1453 pcs_mdio5: mdio@8c17000 {
1454 compatible = "fsl,fman-memac-mdio";
1455 reg = <0x0 0x8c17000 0x0 0x1000>;
1456 little-endian;
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459 status = "disabled";
1460
1461 pcs5: ethernet-phy@0 {
1462 reg = <0>;
1463 };
1464 };
1465
1466 pcs_mdio6: mdio@8c1b000 {
1467 compatible = "fsl,fman-memac-mdio";
1468 reg = <0x0 0x8c1b000 0x0 0x1000>;
1469 little-endian;
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 status = "disabled";
1473
1474 pcs6: ethernet-phy@0 {
1475 reg = <0>;
1476 };
1477 };
1478
1479 pcs_mdio7: mdio@8c1f000 {
1480 compatible = "fsl,fman-memac-mdio";
1481 reg = <0x0 0x8c1f000 0x0 0x1000>;
1482 little-endian;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 status = "disabled";
1486
1487 pcs7: ethernet-phy@0 {
1488 reg = <0>;
1489 };
1490 };
1491
1492 pcs_mdio8: mdio@8c23000 {
1493 compatible = "fsl,fman-memac-mdio";
1494 reg = <0x0 0x8c23000 0x0 0x1000>;
1495 little-endian;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 status = "disabled";
1499
1500 pcs8: ethernet-phy@0 {
1501 reg = <0>;
1502 };
1503 };
1504
1505 pcs_mdio9: mdio@8c27000 {
1506 compatible = "fsl,fman-memac-mdio";
1507 reg = <0x0 0x8c27000 0x0 0x1000>;
1508 little-endian;
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1511 status = "disabled";
1512
1513 pcs9: ethernet-phy@0 {
1514 reg = <0>;
1515 };
1516 };
1517
1518 pcs_mdio10: mdio@8c2b000 {
1519 compatible = "fsl,fman-memac-mdio";
1520 reg = <0x0 0x8c2b000 0x0 0x1000>;
1521 little-endian;
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1524 status = "disabled";
1525
1526 pcs10: ethernet-phy@0 {
1527 reg = <0>;
1528 };
1529 };
1530
1531 pcs_mdio11: mdio@8c2f000 {
1532 compatible = "fsl,fman-memac-mdio";
1533 reg = <0x0 0x8c2f000 0x0 0x1000>;
1534 little-endian;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537 status = "disabled";
1538
1539 pcs11: ethernet-phy@0 {
1540 reg = <0>;
1541 };
1542 };
1543
1544 pcs_mdio12: mdio@8c33000 {
1545 compatible = "fsl,fman-memac-mdio";
1546 reg = <0x0 0x8c33000 0x0 0x1000>;
1547 little-endian;
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 status = "disabled";
1551
1552 pcs12: ethernet-phy@0 {
1553 reg = <0>;
1554 };
1555 };
1556
1557 pcs_mdio13: mdio@8c37000 {
1558 compatible = "fsl,fman-memac-mdio";
1559 reg = <0x0 0x8c37000 0x0 0x1000>;
1560 little-endian;
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1563 status = "disabled";
1564
1565 pcs13: ethernet-phy@0 {
1566 reg = <0>;
1567 };
1568 };
1569
1570 pcs_mdio14: mdio@8c3b000 {
1571 compatible = "fsl,fman-memac-mdio";
1572 reg = <0x0 0x8c3b000 0x0 0x1000>;
1573 little-endian;
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1576 status = "disabled";
1577
1578 pcs14: ethernet-phy@0 {
1579 reg = <0>;
1580 };
1581 };
1582
1583 pcs_mdio15: mdio@8c3f000 {
1584 compatible = "fsl,fman-memac-mdio";
1585 reg = <0x0 0x8c3f000 0x0 0x1000>;
1586 little-endian;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 status = "disabled";
1590
1591 pcs15: ethernet-phy@0 {
1592 reg = <0>;
1593 };
1594 };
1595
1596 pcs_mdio16: mdio@8c43000 {
1597 compatible = "fsl,fman-memac-mdio";
1598 reg = <0x0 0x8c43000 0x0 0x1000>;
1599 little-endian;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 status = "disabled";
1603
1604 pcs16: ethernet-phy@0 {
1605 reg = <0>;
1606 };
1607 };
1608
1609 pcs_mdio17: mdio@8c47000 {
1610 compatible = "fsl,fman-memac-mdio";
1611 reg = <0x0 0x8c47000 0x0 0x1000>;
1612 little-endian;
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 status = "disabled";
1616
1617 pcs17: ethernet-phy@0 {
1618 reg = <0>;
1619 };
1620 };
1621
1622 pcs_mdio18: mdio@8c4b000 {
1623 compatible = "fsl,fman-memac-mdio";
1624 reg = <0x0 0x8c4b000 0x0 0x1000>;
1625 little-endian;
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1628 status = "disabled";
1629
1630 pcs18: ethernet-phy@0 {
1631 reg = <0>;
1632 };
1633 };
1634
1635 fsl_mc: fsl-mc@80c000000 {
1636 compatible = "fsl,qoriq-mc";
1637 reg = <0x00000008 0x0c000000 0 0x40>,
1638 <0x00000000 0x08340000 0 0x40000>;
1639 msi-parent = <&its>;
1640 /* iommu-map property is fixed up by u-boot */
1641 iommu-map = <0 &smmu 0 0>;
1642 dma-coherent;
1643 #address-cells = <3>;
1644 #size-cells = <1>;
1645
1646 /*
1647 * Region type 0x0 - MC portals
1648 * Region type 0x1 - QBMAN portals
1649 */
1650 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1651 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1652
1653 /*
1654 * Define the maximum number of MACs present on the SoC.
1655 */
1656 dpmacs {
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659
1660 dpmac1: ethernet@1 {
1661 compatible = "fsl,qoriq-mc-dpmac";
1662 reg = <0x1>;
1663 pcs-handle = <&pcs1>;
1664 };
1665
1666 dpmac2: ethernet@2 {
1667 compatible = "fsl,qoriq-mc-dpmac";
1668 reg = <0x2>;
1669 pcs-handle = <&pcs2>;
1670 };
1671
1672 dpmac3: ethernet@3 {
1673 compatible = "fsl,qoriq-mc-dpmac";
1674 reg = <0x3>;
1675 pcs-handle = <&pcs3>;
1676 };
1677
1678 dpmac4: ethernet@4 {
1679 compatible = "fsl,qoriq-mc-dpmac";
1680 reg = <0x4>;
1681 pcs-handle = <&pcs4>;
1682 };
1683
1684 dpmac5: ethernet@5 {
1685 compatible = "fsl,qoriq-mc-dpmac";
1686 reg = <0x5>;
1687 pcs-handle = <&pcs5>;
1688 };
1689
1690 dpmac6: ethernet@6 {
1691 compatible = "fsl,qoriq-mc-dpmac";
1692 reg = <0x6>;
1693 pcs-handle = <&pcs6>;
1694 };
1695
1696 dpmac7: ethernet@7 {
1697 compatible = "fsl,qoriq-mc-dpmac";
1698 reg = <0x7>;
1699 pcs-handle = <&pcs7>;
1700 };
1701
1702 dpmac8: ethernet@8 {
1703 compatible = "fsl,qoriq-mc-dpmac";
1704 reg = <0x8>;
1705 pcs-handle = <&pcs8>;
1706 };
1707
1708 dpmac9: ethernet@9 {
1709 compatible = "fsl,qoriq-mc-dpmac";
1710 reg = <0x9>;
1711 pcs-handle = <&pcs9>;
1712 };
1713
1714 dpmac10: ethernet@a {
1715 compatible = "fsl,qoriq-mc-dpmac";
1716 reg = <0xa>;
1717 pcs-handle = <&pcs10>;
1718 };
1719
1720 dpmac11: ethernet@b {
1721 compatible = "fsl,qoriq-mc-dpmac";
1722 reg = <0xb>;
1723 pcs-handle = <&pcs11>;
1724 };
1725
1726 dpmac12: ethernet@c {
1727 compatible = "fsl,qoriq-mc-dpmac";
1728 reg = <0xc>;
1729 pcs-handle = <&pcs12>;
1730 };
1731
1732 dpmac13: ethernet@d {
1733 compatible = "fsl,qoriq-mc-dpmac";
1734 reg = <0xd>;
1735 pcs-handle = <&pcs13>;
1736 };
1737
1738 dpmac14: ethernet@e {
1739 compatible = "fsl,qoriq-mc-dpmac";
1740 reg = <0xe>;
1741 pcs-handle = <&pcs14>;
1742 };
1743
1744 dpmac15: ethernet@f {
1745 compatible = "fsl,qoriq-mc-dpmac";
1746 reg = <0xf>;
1747 pcs-handle = <&pcs15>;
1748 };
1749
1750 dpmac16: ethernet@10 {
1751 compatible = "fsl,qoriq-mc-dpmac";
1752 reg = <0x10>;
1753 pcs-handle = <&pcs16>;
1754 };
1755
1756 dpmac17: ethernet@11 {
1757 compatible = "fsl,qoriq-mc-dpmac";
1758 reg = <0x11>;
1759 pcs-handle = <&pcs17>;
1760 };
1761
1762 dpmac18: ethernet@12 {
1763 compatible = "fsl,qoriq-mc-dpmac";
1764 reg = <0x12>;
1765 pcs-handle = <&pcs18>;
1766 };
1767 };
1768 };
1769 };
1770
1771 firmware {
1772 optee: optee {
1773 compatible = "linaro,optee-tz";
1774 method = "smc";
1775 status = "disabled";
1776 };
1777 };
1778 };
