0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
0004 *
0005 * Copyright 2016 Freescale Semiconductor, Inc.
0006 * Copyright 2017-2020 NXP
0007 *
0008 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
0009 *
0010 */
0011
0012 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014 #include <dt-bindings/interrupt-controller/arm-gic.h>
0015
0016 / {
0017 compatible = "fsl,ls2080a";
0018 interrupt-parent = <&gic>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 aliases {
0023 crypto = &crypto;
0024 rtc1 = &ftm_alarm0;
0025 serial0 = &serial0;
0026 serial1 = &serial1;
0027 serial2 = &serial2;
0028 serial3 = &serial3;
0029 };
0030
0031 cpu: cpus {
0032 #address-cells = <1>;
0033 #size-cells = <0>;
0034 };
0035
0036 memory@80000000 {
0037 device_type = "memory";
0038 reg = <0x00000000 0x80000000 0 0x80000000>;
0039 /* DRAM space - 1, size : 2 GB DRAM */
0040 };
0041
0042 sysclk: sysclk {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <100000000>;
0046 clock-output-names = "sysclk";
0047 };
0048
0049 gic: interrupt-controller@6000000 {
0050 compatible = "arm,gic-v3";
0051 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
0052 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
0053 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
0054 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
0055 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
0056 #interrupt-cells = <3>;
0057 #address-cells = <2>;
0058 #size-cells = <2>;
0059 ranges;
0060 interrupt-controller;
0061 interrupts = <1 9 0x4>;
0062
0063 its: gic-its@6020000 {
0064 compatible = "arm,gic-v3-its";
0065 msi-controller;
0066 reg = <0x0 0x6020000 0 0x20000>;
0067 };
0068 };
0069
0070 rstcr: syscon@1e60000 {
0071 compatible = "fsl,ls2080a-rstcr", "syscon";
0072 reg = <0x0 0x1e60000 0x0 0x4>;
0073 };
0074
0075 reboot {
0076 compatible = "syscon-reboot";
0077 regmap = <&rstcr>;
0078 offset = <0x0>;
0079 mask = <0x2>;
0080 };
0081
0082 thermal-zones {
0083 ddr-controller1 {
0084 polling-delay-passive = <1000>;
0085 polling-delay = <5000>;
0086 thermal-sensors = <&tmu 1>;
0087
0088 trips {
0089 ddr-ctrler1-crit {
0090 temperature = <95000>;
0091 hysteresis = <2000>;
0092 type = "critical";
0093 };
0094 };
0095 };
0096
0097 ddr-controller2 {
0098 polling-delay-passive = <1000>;
0099 polling-delay = <5000>;
0100 thermal-sensors = <&tmu 2>;
0101
0102 trips {
0103 ddr-ctrler2-crit {
0104 temperature = <95000>;
0105 hysteresis = <2000>;
0106 type = "critical";
0107 };
0108 };
0109 };
0110
0111 ddr-controller3 {
0112 polling-delay-passive = <1000>;
0113 polling-delay = <5000>;
0114 thermal-sensors = <&tmu 3>;
0115
0116 trips {
0117 ddr-ctrler3-crit {
0118 temperature = <95000>;
0119 hysteresis = <2000>;
0120 type = "critical";
0121 };
0122 };
0123 };
0124
0125 core-cluster1 {
0126 polling-delay-passive = <1000>;
0127 polling-delay = <5000>;
0128 thermal-sensors = <&tmu 4>;
0129
0130 trips {
0131 core_cluster1_alert: core-cluster1-alert {
0132 temperature = <85000>;
0133 hysteresis = <2000>;
0134 type = "passive";
0135 };
0136
0137 core-cluster1-crit {
0138 temperature = <95000>;
0139 hysteresis = <2000>;
0140 type = "critical";
0141 };
0142 };
0143
0144 cooling-maps {
0145 map0 {
0146 trip = <&core_cluster1_alert>;
0147 cooling-device =
0148 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0149 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0150 };
0151 };
0152 };
0153
0154 core-cluster2 {
0155 polling-delay-passive = <1000>;
0156 polling-delay = <5000>;
0157 thermal-sensors = <&tmu 5>;
0158
0159 trips {
0160 core_cluster2_alert: core-cluster2-alert {
0161 temperature = <85000>;
0162 hysteresis = <2000>;
0163 type = "passive";
0164 };
0165
0166 core-cluster2-crit {
0167 temperature = <95000>;
0168 hysteresis = <2000>;
0169 type = "critical";
0170 };
0171 };
0172
0173 cooling-maps {
0174 map0 {
0175 trip = <&core_cluster2_alert>;
0176 cooling-device =
0177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0179 };
0180 };
0181 };
0182
0183 core-cluster3 {
0184 polling-delay-passive = <1000>;
0185 polling-delay = <5000>;
0186 thermal-sensors = <&tmu 6>;
0187
0188 trips {
0189 core_cluster3_alert: core-cluster3-alert {
0190 temperature = <85000>;
0191 hysteresis = <2000>;
0192 type = "passive";
0193 };
0194
0195 core-cluster3-crit {
0196 temperature = <95000>;
0197 hysteresis = <2000>;
0198 type = "critical";
0199 };
0200 };
0201
0202 cooling-maps {
0203 map0 {
0204 trip = <&core_cluster3_alert>;
0205 cooling-device =
0206 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0207 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0208 };
0209 };
0210 };
0211
0212 core-cluster4 {
0213 polling-delay-passive = <1000>;
0214 polling-delay = <5000>;
0215 thermal-sensors = <&tmu 7>;
0216
0217 trips {
0218 core_cluster4_alert: core-cluster4-alert {
0219 temperature = <85000>;
0220 hysteresis = <2000>;
0221 type = "passive";
0222 };
0223
0224 core-cluster4-crit {
0225 temperature = <95000>;
0226 hysteresis = <2000>;
0227 type = "critical";
0228 };
0229 };
0230
0231 cooling-maps {
0232 map0 {
0233 trip = <&core_cluster4_alert>;
0234 cooling-device =
0235 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0236 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0237 };
0238 };
0239 };
0240 };
0241
0242 timer {
0243 compatible = "arm,armv8-timer";
0244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
0245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
0246 <1 11 4>, /* Virtual PPI, active-low */
0247 <1 10 4>; /* Hypervisor PPI, active-low */
0248 fsl,erratum-a008585;
0249 };
0250
0251 pmu {
0252 compatible = "arm,armv8-pmuv3";
0253 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
0254 };
0255
0256 psci {
0257 compatible = "arm,psci-0.2";
0258 method = "smc";
0259 };
0260
0261 soc {
0262 compatible = "simple-bus";
0263 #address-cells = <2>;
0264 #size-cells = <2>;
0265 ranges;
0266 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
0267
0268 clockgen: clocking@1300000 {
0269 compatible = "fsl,ls2080a-clockgen";
0270 reg = <0 0x1300000 0 0xa0000>;
0271 #clock-cells = <2>;
0272 clocks = <&sysclk>;
0273 };
0274
0275 dcfg: dcfg@1e00000 {
0276 compatible = "fsl,ls2080a-dcfg", "syscon";
0277 reg = <0x0 0x1e00000 0x0 0x10000>;
0278 little-endian;
0279 };
0280
0281 sfp: efuse@1e80000 {
0282 compatible = "fsl,ls1028a-sfp";
0283 reg = <0x0 0x1e80000 0x0 0x10000>;
0284 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0285 QORIQ_CLK_PLL_DIV(4)>;
0286 clock-names = "sfp";
0287 };
0288
0289 isc: syscon@1f70000 {
0290 compatible = "fsl,ls2080a-isc", "syscon";
0291 reg = <0x0 0x1f70000 0x0 0x10000>;
0292 little-endian;
0293 #address-cells = <1>;
0294 #size-cells = <1>;
0295 ranges = <0x0 0x0 0x1f70000 0x10000>;
0296
0297 extirq: interrupt-controller@14 {
0298 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
0299 #interrupt-cells = <2>;
0300 #address-cells = <0>;
0301 interrupt-controller;
0302 reg = <0x14 4>;
0303 interrupt-map =
0304 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0305 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0306 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0307 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0308 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0309 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0310 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0311 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0312 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0313 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0314 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0315 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0316 interrupt-map-mask = <0xf 0x0>;
0317 };
0318 };
0319
0320 tmu: tmu@1f80000 {
0321 compatible = "fsl,qoriq-tmu";
0322 reg = <0x0 0x1f80000 0x0 0x10000>;
0323 interrupts = <0 23 0x4>;
0324 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
0325 fsl,tmu-calibration = <0x00000000 0x00000026
0326 0x00000001 0x0000002d
0327 0x00000002 0x00000032
0328 0x00000003 0x00000039
0329 0x00000004 0x0000003f
0330 0x00000005 0x00000046
0331 0x00000006 0x0000004d
0332 0x00000007 0x00000054
0333 0x00000008 0x0000005a
0334 0x00000009 0x00000061
0335 0x0000000a 0x0000006a
0336 0x0000000b 0x00000071
0337
0338 0x00010000 0x00000025
0339 0x00010001 0x0000002c
0340 0x00010002 0x00000035
0341 0x00010003 0x0000003d
0342 0x00010004 0x00000045
0343 0x00010005 0x0000004e
0344 0x00010006 0x00000057
0345 0x00010007 0x00000061
0346 0x00010008 0x0000006b
0347 0x00010009 0x00000076
0348
0349 0x00020000 0x00000029
0350 0x00020001 0x00000033
0351 0x00020002 0x0000003d
0352 0x00020003 0x00000049
0353 0x00020004 0x00000056
0354 0x00020005 0x00000061
0355 0x00020006 0x0000006d
0356
0357 0x00030000 0x00000021
0358 0x00030001 0x0000002a
0359 0x00030002 0x0000003c
0360 0x00030003 0x0000004e>;
0361 little-endian;
0362 #thermal-sensor-cells = <1>;
0363 };
0364
0365 serial0: serial@21c0500 {
0366 compatible = "fsl,ns16550", "ns16550a";
0367 reg = <0x0 0x21c0500 0x0 0x100>;
0368 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0369 QORIQ_CLK_PLL_DIV(4)>;
0370 interrupts = <0 32 0x4>; /* Level high type */
0371 };
0372
0373 serial1: serial@21c0600 {
0374 compatible = "fsl,ns16550", "ns16550a";
0375 reg = <0x0 0x21c0600 0x0 0x100>;
0376 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0377 QORIQ_CLK_PLL_DIV(4)>;
0378 interrupts = <0 32 0x4>; /* Level high type */
0379 };
0380
0381 serial2: serial@21d0500 {
0382 compatible = "fsl,ns16550", "ns16550a";
0383 reg = <0x0 0x21d0500 0x0 0x100>;
0384 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0385 QORIQ_CLK_PLL_DIV(4)>;
0386 interrupts = <0 33 0x4>; /* Level high type */
0387 };
0388
0389 serial3: serial@21d0600 {
0390 compatible = "fsl,ns16550", "ns16550a";
0391 reg = <0x0 0x21d0600 0x0 0x100>;
0392 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0393 QORIQ_CLK_PLL_DIV(4)>;
0394 interrupts = <0 33 0x4>; /* Level high type */
0395 };
0396
0397 cluster1_core0_watchdog: wdt@c000000 {
0398 compatible = "arm,sp805", "arm,primecell";
0399 reg = <0x0 0xc000000 0x0 0x1000>;
0400 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0401 QORIQ_CLK_PLL_DIV(4)>,
0402 <&clockgen QORIQ_CLK_PLATFORM_PLL
0403 QORIQ_CLK_PLL_DIV(4)>;
0404 clock-names = "wdog_clk", "apb_pclk";
0405 };
0406
0407 cluster1_core1_watchdog: wdt@c010000 {
0408 compatible = "arm,sp805", "arm,primecell";
0409 reg = <0x0 0xc010000 0x0 0x1000>;
0410 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0411 QORIQ_CLK_PLL_DIV(4)>,
0412 <&clockgen QORIQ_CLK_PLATFORM_PLL
0413 QORIQ_CLK_PLL_DIV(4)>;
0414 clock-names = "wdog_clk", "apb_pclk";
0415 };
0416
0417 cluster2_core0_watchdog: wdt@c100000 {
0418 compatible = "arm,sp805", "arm,primecell";
0419 reg = <0x0 0xc100000 0x0 0x1000>;
0420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0421 QORIQ_CLK_PLL_DIV(4)>,
0422 <&clockgen QORIQ_CLK_PLATFORM_PLL
0423 QORIQ_CLK_PLL_DIV(4)>;
0424 clock-names = "wdog_clk", "apb_pclk";
0425 };
0426
0427 cluster2_core1_watchdog: wdt@c110000 {
0428 compatible = "arm,sp805", "arm,primecell";
0429 reg = <0x0 0xc110000 0x0 0x1000>;
0430 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0431 QORIQ_CLK_PLL_DIV(4)>,
0432 <&clockgen QORIQ_CLK_PLATFORM_PLL
0433 QORIQ_CLK_PLL_DIV(4)>;
0434 clock-names = "wdog_clk", "apb_pclk";
0435 };
0436
0437 cluster3_core0_watchdog: wdt@c200000 {
0438 compatible = "arm,sp805", "arm,primecell";
0439 reg = <0x0 0xc200000 0x0 0x1000>;
0440 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0441 QORIQ_CLK_PLL_DIV(4)>,
0442 <&clockgen QORIQ_CLK_PLATFORM_PLL
0443 QORIQ_CLK_PLL_DIV(4)>;
0444 clock-names = "wdog_clk", "apb_pclk";
0445 };
0446
0447 cluster3_core1_watchdog: wdt@c210000 {
0448 compatible = "arm,sp805", "arm,primecell";
0449 reg = <0x0 0xc210000 0x0 0x1000>;
0450 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0451 QORIQ_CLK_PLL_DIV(4)>,
0452 <&clockgen QORIQ_CLK_PLATFORM_PLL
0453 QORIQ_CLK_PLL_DIV(4)>;
0454 clock-names = "wdog_clk", "apb_pclk";
0455 };
0456
0457 cluster4_core0_watchdog: wdt@c300000 {
0458 compatible = "arm,sp805", "arm,primecell";
0459 reg = <0x0 0xc300000 0x0 0x1000>;
0460 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0461 QORIQ_CLK_PLL_DIV(4)>,
0462 <&clockgen QORIQ_CLK_PLATFORM_PLL
0463 QORIQ_CLK_PLL_DIV(4)>;
0464 clock-names = "wdog_clk", "apb_pclk";
0465 };
0466
0467 cluster4_core1_watchdog: wdt@c310000 {
0468 compatible = "arm,sp805", "arm,primecell";
0469 reg = <0x0 0xc310000 0x0 0x1000>;
0470 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0471 QORIQ_CLK_PLL_DIV(4)>,
0472 <&clockgen QORIQ_CLK_PLATFORM_PLL
0473 QORIQ_CLK_PLL_DIV(4)>;
0474 clock-names = "wdog_clk", "apb_pclk";
0475 };
0476
0477 crypto: crypto@8000000 {
0478 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
0479 fsl,sec-era = <8>;
0480 #address-cells = <1>;
0481 #size-cells = <1>;
0482 ranges = <0x0 0x00 0x8000000 0x100000>;
0483 reg = <0x00 0x8000000 0x0 0x100000>;
0484 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0485 dma-coherent;
0486
0487 sec_jr0: jr@10000 {
0488 compatible = "fsl,sec-v5.0-job-ring",
0489 "fsl,sec-v4.0-job-ring";
0490 reg = <0x10000 0x10000>;
0491 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0492 };
0493
0494 sec_jr1: jr@20000 {
0495 compatible = "fsl,sec-v5.0-job-ring",
0496 "fsl,sec-v4.0-job-ring";
0497 reg = <0x20000 0x10000>;
0498 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0499 };
0500
0501 sec_jr2: jr@30000 {
0502 compatible = "fsl,sec-v5.0-job-ring",
0503 "fsl,sec-v4.0-job-ring";
0504 reg = <0x30000 0x10000>;
0505 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0506 };
0507
0508 sec_jr3: jr@40000 {
0509 compatible = "fsl,sec-v5.0-job-ring",
0510 "fsl,sec-v4.0-job-ring";
0511 reg = <0x40000 0x10000>;
0512 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0513 };
0514 };
0515
0516 console@8340020 {
0517 compatible = "fsl,dpaa2-console";
0518 reg = <0x00000000 0x08340020 0 0x2>;
0519 };
0520
0521 ptp-timer@8b95000 {
0522 compatible = "fsl,dpaa2-ptp";
0523 reg = <0x0 0x8b95000 0x0 0x100>;
0524 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0525 QORIQ_CLK_PLL_DIV(2)>;
0526 little-endian;
0527 fsl,extts-fifo;
0528 };
0529
0530 emdio1: mdio@8b96000 {
0531 compatible = "fsl,fman-memac-mdio";
0532 reg = <0x0 0x8b96000 0x0 0x1000>;
0533 little-endian;
0534 #address-cells = <1>;
0535 #size-cells = <0>;
0536 status = "disabled";
0537 };
0538
0539 emdio2: mdio@8b97000 {
0540 compatible = "fsl,fman-memac-mdio";
0541 reg = <0x0 0x8b97000 0x0 0x1000>;
0542 little-endian;
0543 #address-cells = <1>;
0544 #size-cells = <0>;
0545 status = "disabled";
0546 };
0547
0548 pcs_mdio1: mdio@8c07000 {
0549 compatible = "fsl,fman-memac-mdio";
0550 reg = <0x0 0x8c07000 0x0 0x1000>;
0551 little-endian;
0552 #address-cells = <1>;
0553 #size-cells = <0>;
0554 status = "disabled";
0555
0556 pcs1: ethernet-phy@0 {
0557 reg = <0>;
0558 };
0559 };
0560
0561 pcs_mdio2: mdio@8c0b000 {
0562 compatible = "fsl,fman-memac-mdio";
0563 reg = <0x0 0x8c0b000 0x0 0x1000>;
0564 little-endian;
0565 #address-cells = <1>;
0566 #size-cells = <0>;
0567 status = "disabled";
0568
0569 pcs2: ethernet-phy@0 {
0570 reg = <0>;
0571 };
0572 };
0573
0574 pcs_mdio3: mdio@8c0f000 {
0575 compatible = "fsl,fman-memac-mdio";
0576 reg = <0x0 0x8c0f000 0x0 0x1000>;
0577 little-endian;
0578 #address-cells = <1>;
0579 #size-cells = <0>;
0580 status = "disabled";
0581
0582 pcs3: ethernet-phy@0 {
0583 reg = <0>;
0584 };
0585 };
0586
0587 pcs_mdio4: mdio@8c13000 {
0588 compatible = "fsl,fman-memac-mdio";
0589 reg = <0x0 0x8c13000 0x0 0x1000>;
0590 little-endian;
0591 #address-cells = <1>;
0592 #size-cells = <0>;
0593 status = "disabled";
0594
0595 pcs4: ethernet-phy@0 {
0596 reg = <0>;
0597 };
0598 };
0599
0600 pcs_mdio5: mdio@8c17000 {
0601 compatible = "fsl,fman-memac-mdio";
0602 reg = <0x0 0x8c17000 0x0 0x1000>;
0603 little-endian;
0604 #address-cells = <1>;
0605 #size-cells = <0>;
0606 status = "disabled";
0607
0608 pcs5: ethernet-phy@0 {
0609 reg = <0>;
0610 };
0611 };
0612
0613 pcs_mdio6: mdio@8c1b000 {
0614 compatible = "fsl,fman-memac-mdio";
0615 reg = <0x0 0x8c1b000 0x0 0x1000>;
0616 little-endian;
0617 #address-cells = <1>;
0618 #size-cells = <0>;
0619 status = "disabled";
0620
0621 pcs6: ethernet-phy@0 {
0622 reg = <0>;
0623 };
0624 };
0625
0626 pcs_mdio7: mdio@8c1f000 {
0627 compatible = "fsl,fman-memac-mdio";
0628 reg = <0x0 0x8c1f000 0x0 0x1000>;
0629 little-endian;
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632 status = "disabled";
0633
0634 pcs7: ethernet-phy@0 {
0635 reg = <0>;
0636 };
0637 };
0638
0639 pcs_mdio8: mdio@8c23000 {
0640 compatible = "fsl,fman-memac-mdio";
0641 reg = <0x0 0x8c23000 0x0 0x1000>;
0642 little-endian;
0643 #address-cells = <1>;
0644 #size-cells = <0>;
0645 status = "disabled";
0646
0647 pcs8: ethernet-phy@0 {
0648 reg = <0>;
0649 };
0650 };
0651
0652 pcs_mdio9: mdio@8c27000 {
0653 compatible = "fsl,fman-memac-mdio";
0654 reg = <0x0 0x8c27000 0x0 0x1000>;
0655 little-endian;
0656 #address-cells = <1>;
0657 #size-cells = <0>;
0658 status = "disabled";
0659
0660 pcs9: ethernet-phy@0 {
0661 reg = <0>;
0662 };
0663 };
0664
0665 pcs_mdio10: mdio@8c2b000 {
0666 compatible = "fsl,fman-memac-mdio";
0667 reg = <0x0 0x8c2b000 0x0 0x1000>;
0668 little-endian;
0669 #address-cells = <1>;
0670 #size-cells = <0>;
0671 status = "disabled";
0672
0673 pcs10: ethernet-phy@0 {
0674 reg = <0>;
0675 };
0676 };
0677
0678 pcs_mdio11: mdio@8c2f000 {
0679 compatible = "fsl,fman-memac-mdio";
0680 reg = <0x0 0x8c2f000 0x0 0x1000>;
0681 little-endian;
0682 #address-cells = <1>;
0683 #size-cells = <0>;
0684 status = "disabled";
0685
0686 pcs11: ethernet-phy@0 {
0687 reg = <0>;
0688 };
0689 };
0690
0691 pcs_mdio12: mdio@8c33000 {
0692 compatible = "fsl,fman-memac-mdio";
0693 reg = <0x0 0x8c33000 0x0 0x1000>;
0694 little-endian;
0695 #address-cells = <1>;
0696 #size-cells = <0>;
0697 status = "disabled";
0698
0699 pcs12: ethernet-phy@0 {
0700 reg = <0>;
0701 };
0702 };
0703
0704 pcs_mdio13: mdio@8c37000 {
0705 compatible = "fsl,fman-memac-mdio";
0706 reg = <0x0 0x8c37000 0x0 0x1000>;
0707 little-endian;
0708 #address-cells = <1>;
0709 #size-cells = <0>;
0710 status = "disabled";
0711
0712 pcs13: ethernet-phy@0 {
0713 reg = <0>;
0714 };
0715 };
0716
0717 pcs_mdio14: mdio@8c3b000 {
0718 compatible = "fsl,fman-memac-mdio";
0719 reg = <0x0 0x8c3b000 0x0 0x1000>;
0720 little-endian;
0721 #address-cells = <1>;
0722 #size-cells = <0>;
0723 status = "disabled";
0724
0725 pcs14: ethernet-phy@0 {
0726 reg = <0>;
0727 };
0728 };
0729
0730 pcs_mdio15: mdio@8c3f000 {
0731 compatible = "fsl,fman-memac-mdio";
0732 reg = <0x0 0x8c3f000 0x0 0x1000>;
0733 little-endian;
0734 #address-cells = <1>;
0735 #size-cells = <0>;
0736 status = "disabled";
0737
0738 pcs15: ethernet-phy@0 {
0739 reg = <0>;
0740 };
0741 };
0742
0743 pcs_mdio16: mdio@8c43000 {
0744 compatible = "fsl,fman-memac-mdio";
0745 reg = <0x0 0x8c43000 0x0 0x1000>;
0746 little-endian;
0747 #address-cells = <1>;
0748 #size-cells = <0>;
0749 status = "disabled";
0750
0751 pcs16: ethernet-phy@0 {
0752 reg = <0>;
0753 };
0754 };
0755
0756 fsl_mc: fsl-mc@80c000000 {
0757 compatible = "fsl,qoriq-mc";
0758 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
0759 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
0760 msi-parent = <&its>;
0761 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
0762 dma-coherent;
0763 #address-cells = <3>;
0764 #size-cells = <1>;
0765
0766 /*
0767 * Region type 0x0 - MC portals
0768 * Region type 0x1 - QBMAN portals
0769 */
0770 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0771 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
0772
0773 /*
0774 * Define the maximum number of MACs present on the SoC.
0775 */
0776 dpmacs {
0777 #address-cells = <1>;
0778 #size-cells = <0>;
0779
0780 dpmac1: ethernet@1 {
0781 compatible = "fsl,qoriq-mc-dpmac";
0782 reg = <0x1>;
0783 pcs-handle = <&pcs1>;
0784 };
0785
0786 dpmac2: ethernet@2 {
0787 compatible = "fsl,qoriq-mc-dpmac";
0788 reg = <0x2>;
0789 pcs-handle = <&pcs2>;
0790 };
0791
0792 dpmac3: ethernet@3 {
0793 compatible = "fsl,qoriq-mc-dpmac";
0794 reg = <0x3>;
0795 pcs-handle = <&pcs3>;
0796 };
0797
0798 dpmac4: ethernet@4 {
0799 compatible = "fsl,qoriq-mc-dpmac";
0800 reg = <0x4>;
0801 pcs-handle = <&pcs4>;
0802 };
0803
0804 dpmac5: ethernet@5 {
0805 compatible = "fsl,qoriq-mc-dpmac";
0806 reg = <0x5>;
0807 pcs-handle = <&pcs5>;
0808 };
0809
0810 dpmac6: ethernet@6 {
0811 compatible = "fsl,qoriq-mc-dpmac";
0812 reg = <0x6>;
0813 pcs-handle = <&pcs6>;
0814 };
0815
0816 dpmac7: ethernet@7 {
0817 compatible = "fsl,qoriq-mc-dpmac";
0818 reg = <0x7>;
0819 pcs-handle = <&pcs7>;
0820 };
0821
0822 dpmac8: ethernet@8 {
0823 compatible = "fsl,qoriq-mc-dpmac";
0824 reg = <0x8>;
0825 pcs-handle = <&pcs8>;
0826 };
0827
0828 dpmac9: ethernet@9 {
0829 compatible = "fsl,qoriq-mc-dpmac";
0830 reg = <0x9>;
0831 pcs-handle = <&pcs9>;
0832 };
0833
0834 dpmac10: ethernet@a {
0835 compatible = "fsl,qoriq-mc-dpmac";
0836 reg = <0xa>;
0837 pcs-handle = <&pcs10>;
0838 };
0839
0840 dpmac11: ethernet@b {
0841 compatible = "fsl,qoriq-mc-dpmac";
0842 reg = <0xb>;
0843 pcs-handle = <&pcs11>;
0844 };
0845
0846 dpmac12: ethernet@c {
0847 compatible = "fsl,qoriq-mc-dpmac";
0848 reg = <0xc>;
0849 pcs-handle = <&pcs12>;
0850 };
0851
0852 dpmac13: ethernet@d {
0853 compatible = "fsl,qoriq-mc-dpmac";
0854 reg = <0xd>;
0855 pcs-handle = <&pcs13>;
0856 };
0857
0858 dpmac14: ethernet@e {
0859 compatible = "fsl,qoriq-mc-dpmac";
0860 reg = <0xe>;
0861 pcs-handle = <&pcs14>;
0862 };
0863
0864 dpmac15: ethernet@f {
0865 compatible = "fsl,qoriq-mc-dpmac";
0866 reg = <0xf>;
0867 pcs-handle = <&pcs15>;
0868 };
0869
0870 dpmac16: ethernet@10 {
0871 compatible = "fsl,qoriq-mc-dpmac";
0872 reg = <0x10>;
0873 pcs-handle = <&pcs16>;
0874 };
0875 };
0876 };
0877
0878 smmu: iommu@5000000 {
0879 compatible = "arm,mmu-500";
0880 reg = <0 0x5000000 0 0x800000>;
0881 #global-interrupts = <12>;
0882 #iommu-cells = <1>;
0883 stream-match-mask = <0x7C00>;
0884 dma-coherent;
0885 interrupts = <0 13 4>, /* global secure fault */
0886 <0 14 4>, /* combined secure interrupt */
0887 <0 15 4>, /* global non-secure fault */
0888 <0 16 4>, /* combined non-secure interrupt */
0889 /* performance counter interrupts 0-7 */
0890 <0 211 4>, <0 212 4>,
0891 <0 213 4>, <0 214 4>,
0892 <0 215 4>, <0 216 4>,
0893 <0 217 4>, <0 218 4>,
0894 /* per context interrupt, 64 interrupts */
0895 <0 146 4>, <0 147 4>,
0896 <0 148 4>, <0 149 4>,
0897 <0 150 4>, <0 151 4>,
0898 <0 152 4>, <0 153 4>,
0899 <0 154 4>, <0 155 4>,
0900 <0 156 4>, <0 157 4>,
0901 <0 158 4>, <0 159 4>,
0902 <0 160 4>, <0 161 4>,
0903 <0 162 4>, <0 163 4>,
0904 <0 164 4>, <0 165 4>,
0905 <0 166 4>, <0 167 4>,
0906 <0 168 4>, <0 169 4>,
0907 <0 170 4>, <0 171 4>,
0908 <0 172 4>, <0 173 4>,
0909 <0 174 4>, <0 175 4>,
0910 <0 176 4>, <0 177 4>,
0911 <0 178 4>, <0 179 4>,
0912 <0 180 4>, <0 181 4>,
0913 <0 182 4>, <0 183 4>,
0914 <0 184 4>, <0 185 4>,
0915 <0 186 4>, <0 187 4>,
0916 <0 188 4>, <0 189 4>,
0917 <0 190 4>, <0 191 4>,
0918 <0 192 4>, <0 193 4>,
0919 <0 194 4>, <0 195 4>,
0920 <0 196 4>, <0 197 4>,
0921 <0 198 4>, <0 199 4>,
0922 <0 200 4>, <0 201 4>,
0923 <0 202 4>, <0 203 4>,
0924 <0 204 4>, <0 205 4>,
0925 <0 206 4>, <0 207 4>,
0926 <0 208 4>, <0 209 4>;
0927 };
0928
0929 dspi: spi@2100000 {
0930 status = "disabled";
0931 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
0932 #address-cells = <1>;
0933 #size-cells = <0>;
0934 reg = <0x0 0x2100000 0x0 0x10000>;
0935 interrupts = <0 26 0x4>; /* Level high type */
0936 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0937 QORIQ_CLK_PLL_DIV(4)>;
0938 clock-names = "dspi";
0939 spi-num-chipselects = <5>;
0940 };
0941
0942 esdhc: esdhc@2140000 {
0943 status = "disabled";
0944 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
0945 reg = <0x0 0x2140000 0x0 0x10000>;
0946 interrupts = <0 28 0x4>; /* Level high type */
0947 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0948 QORIQ_CLK_PLL_DIV(2)>;
0949 voltage-ranges = <1800 1800 3300 3300>;
0950 sdhci,auto-cmd12;
0951 little-endian;
0952 bus-width = <4>;
0953 };
0954
0955 gpio0: gpio@2300000 {
0956 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
0957 reg = <0x0 0x2300000 0x0 0x10000>;
0958 interrupts = <0 36 0x4>; /* Level high type */
0959 gpio-controller;
0960 little-endian;
0961 #gpio-cells = <2>;
0962 interrupt-controller;
0963 #interrupt-cells = <2>;
0964 };
0965
0966 gpio1: gpio@2310000 {
0967 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
0968 reg = <0x0 0x2310000 0x0 0x10000>;
0969 interrupts = <0 36 0x4>; /* Level high type */
0970 gpio-controller;
0971 little-endian;
0972 #gpio-cells = <2>;
0973 interrupt-controller;
0974 #interrupt-cells = <2>;
0975 };
0976
0977 gpio2: gpio@2320000 {
0978 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
0979 reg = <0x0 0x2320000 0x0 0x10000>;
0980 interrupts = <0 37 0x4>; /* Level high type */
0981 gpio-controller;
0982 little-endian;
0983 #gpio-cells = <2>;
0984 interrupt-controller;
0985 #interrupt-cells = <2>;
0986 };
0987
0988 gpio3: gpio@2330000 {
0989 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
0990 reg = <0x0 0x2330000 0x0 0x10000>;
0991 interrupts = <0 37 0x4>; /* Level high type */
0992 gpio-controller;
0993 little-endian;
0994 #gpio-cells = <2>;
0995 interrupt-controller;
0996 #interrupt-cells = <2>;
0997 };
0998
0999 i2c0: i2c@2000000 {
1000 status = "disabled";
1001 compatible = "fsl,vf610-i2c";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 reg = <0x0 0x2000000 0x0 0x10000>;
1005 interrupts = <0 34 0x4>; /* Level high type */
1006 clock-names = "i2c";
1007 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1008 QORIQ_CLK_PLL_DIV(4)>;
1009 };
1010
1011 i2c1: i2c@2010000 {
1012 status = "disabled";
1013 compatible = "fsl,vf610-i2c";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 reg = <0x0 0x2010000 0x0 0x10000>;
1017 interrupts = <0 34 0x4>; /* Level high type */
1018 clock-names = "i2c";
1019 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1020 QORIQ_CLK_PLL_DIV(4)>;
1021 };
1022
1023 i2c2: i2c@2020000 {
1024 status = "disabled";
1025 compatible = "fsl,vf610-i2c";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 reg = <0x0 0x2020000 0x0 0x10000>;
1029 interrupts = <0 35 0x4>; /* Level high type */
1030 clock-names = "i2c";
1031 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1032 QORIQ_CLK_PLL_DIV(4)>;
1033 };
1034
1035 i2c3: i2c@2030000 {
1036 status = "disabled";
1037 compatible = "fsl,vf610-i2c";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 reg = <0x0 0x2030000 0x0 0x10000>;
1041 interrupts = <0 35 0x4>; /* Level high type */
1042 clock-names = "i2c";
1043 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1044 QORIQ_CLK_PLL_DIV(4)>;
1045 };
1046
1047 ifc: memory-controller@2240000 {
1048 compatible = "fsl,ifc";
1049 reg = <0x0 0x2240000 0x0 0x20000>;
1050 interrupts = <0 21 0x4>; /* Level high type */
1051 little-endian;
1052 #address-cells = <2>;
1053 #size-cells = <1>;
1054
1055 ranges = <0 0 0x5 0x80000000 0x08000000
1056 2 0 0x5 0x30000000 0x00010000
1057 3 0 0x5 0x20000000 0x00010000>;
1058 };
1059
1060 qspi: spi@20c0000 {
1061 compatible = "fsl,ls2080a-qspi";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 reg = <0x0 0x20c0000 0x0 0x10000>,
1065 <0x0 0x20000000 0x0 0x10000000>;
1066 reg-names = "QuadSPI", "QuadSPI-memory";
1067 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1069 QORIQ_CLK_PLL_DIV(4)>,
1070 <&clockgen QORIQ_CLK_PLATFORM_PLL
1071 QORIQ_CLK_PLL_DIV(4)>;
1072 clock-names = "qspi_en", "qspi";
1073 status = "disabled";
1074 };
1075
1076 pcie1: pcie@3400000 {
1077 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1078 reg-names = "regs", "config";
1079 interrupts = <0 108 0x4>; /* Level high type */
1080 interrupt-names = "intr";
1081 #address-cells = <3>;
1082 #size-cells = <2>;
1083 device_type = "pci";
1084 dma-coherent;
1085 num-viewport = <6>;
1086 bus-range = <0x0 0xff>;
1087 msi-parent = <&its>;
1088 #interrupt-cells = <1>;
1089 interrupt-map-mask = <0 0 0 7>;
1090 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1091 <0000 0 0 2 &gic 0 0 0 110 4>,
1092 <0000 0 0 3 &gic 0 0 0 111 4>,
1093 <0000 0 0 4 &gic 0 0 0 112 4>;
1094 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1095 status = "disabled";
1096 };
1097
1098 pcie2: pcie@3500000 {
1099 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1100 reg-names = "regs", "config";
1101 interrupts = <0 113 0x4>; /* Level high type */
1102 interrupt-names = "intr";
1103 #address-cells = <3>;
1104 #size-cells = <2>;
1105 device_type = "pci";
1106 dma-coherent;
1107 num-viewport = <6>;
1108 bus-range = <0x0 0xff>;
1109 msi-parent = <&its>;
1110 #interrupt-cells = <1>;
1111 interrupt-map-mask = <0 0 0 7>;
1112 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1113 <0000 0 0 2 &gic 0 0 0 115 4>,
1114 <0000 0 0 3 &gic 0 0 0 116 4>,
1115 <0000 0 0 4 &gic 0 0 0 117 4>;
1116 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1117 status = "disabled";
1118 };
1119
1120 pcie3: pcie@3600000 {
1121 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1122 reg-names = "regs", "config";
1123 interrupts = <0 118 0x4>; /* Level high type */
1124 interrupt-names = "intr";
1125 #address-cells = <3>;
1126 #size-cells = <2>;
1127 device_type = "pci";
1128 dma-coherent;
1129 num-viewport = <256>;
1130 bus-range = <0x0 0xff>;
1131 msi-parent = <&its>;
1132 #interrupt-cells = <1>;
1133 interrupt-map-mask = <0 0 0 7>;
1134 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1135 <0000 0 0 2 &gic 0 0 0 120 4>,
1136 <0000 0 0 3 &gic 0 0 0 121 4>,
1137 <0000 0 0 4 &gic 0 0 0 122 4>;
1138 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1139 status = "disabled";
1140 };
1141
1142 pcie4: pcie@3700000 {
1143 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1144 reg-names = "regs", "config";
1145 interrupts = <0 123 0x4>; /* Level high type */
1146 interrupt-names = "intr";
1147 #address-cells = <3>;
1148 #size-cells = <2>;
1149 device_type = "pci";
1150 dma-coherent;
1151 num-viewport = <6>;
1152 bus-range = <0x0 0xff>;
1153 msi-parent = <&its>;
1154 #interrupt-cells = <1>;
1155 interrupt-map-mask = <0 0 0 7>;
1156 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1157 <0000 0 0 2 &gic 0 0 0 125 4>,
1158 <0000 0 0 3 &gic 0 0 0 126 4>,
1159 <0000 0 0 4 &gic 0 0 0 127 4>;
1160 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1161 status = "disabled";
1162 };
1163
1164 sata0: sata@3200000 {
1165 status = "disabled";
1166 compatible = "fsl,ls2080a-ahci";
1167 reg = <0x0 0x3200000 0x0 0x10000>;
1168 interrupts = <0 133 0x4>; /* Level high type */
1169 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1170 QORIQ_CLK_PLL_DIV(4)>;
1171 dma-coherent;
1172 };
1173
1174 sata1: sata@3210000 {
1175 status = "disabled";
1176 compatible = "fsl,ls2080a-ahci";
1177 reg = <0x0 0x3210000 0x0 0x10000>;
1178 interrupts = <0 136 0x4>; /* Level high type */
1179 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1180 QORIQ_CLK_PLL_DIV(4)>;
1181 dma-coherent;
1182 };
1183
1184 usb0: usb@3100000 {
1185 status = "disabled";
1186 compatible = "snps,dwc3";
1187 reg = <0x0 0x3100000 0x0 0x10000>;
1188 interrupts = <0 80 0x4>; /* Level high type */
1189 dr_mode = "host";
1190 snps,quirk-frame-length-adjustment = <0x20>;
1191 snps,dis_rxdet_inp3_quirk;
1192 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1193 };
1194
1195 usb1: usb@3110000 {
1196 status = "disabled";
1197 compatible = "snps,dwc3";
1198 reg = <0x0 0x3110000 0x0 0x10000>;
1199 interrupts = <0 81 0x4>; /* Level high type */
1200 dr_mode = "host";
1201 snps,quirk-frame-length-adjustment = <0x20>;
1202 snps,dis_rxdet_inp3_quirk;
1203 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1204 };
1205
1206 ccn@4000000 {
1207 compatible = "arm,ccn-504";
1208 reg = <0x0 0x04000000 0x0 0x01000000>;
1209 interrupts = <0 12 4>;
1210 };
1211
1212 rcpm: power-controller@1e34040 {
1213 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1214 reg = <0x0 0x1e34040 0x0 0x18>;
1215 #fsl,rcpm-wakeup-cells = <6>;
1216 little-endian;
1217 };
1218
1219 ftm_alarm0: timer@2800000 {
1220 compatible = "fsl,ls208xa-ftm-alarm";
1221 reg = <0x0 0x2800000 0x0 0x10000>;
1222 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1223 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1224 };
1225 };
1226
1227 ddr1: memory-controller@1080000 {
1228 compatible = "fsl,qoriq-memory-controller";
1229 reg = <0x0 0x1080000 0x0 0x1000>;
1230 interrupts = <0 17 0x4>;
1231 little-endian;
1232 };
1233
1234 ddr2: memory-controller@1090000 {
1235 compatible = "fsl,qoriq-memory-controller";
1236 reg = <0x0 0x1090000 0x0 0x1000>;
1237 interrupts = <0 18 0x4>;
1238 little-endian;
1239 };
1240
1241 firmware {
1242 optee {
1243 compatible = "linaro,optee-tz";
1244 method = "smc";
1245 };
1246 };
1247 };
