0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
0004 *
0005 * Copyright 2014-2016 Freescale Semiconductor, Inc.
0006 *
0007 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
0008 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
0009 *
0010 */
0011
0012 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0013 #include "fsl-ls208xa.dtsi"
0014
0015 &cpu {
0016 cpu0: cpu@0 {
0017 device_type = "cpu";
0018 compatible = "arm,cortex-a57";
0019 reg = <0x0>;
0020 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0021 cpu-idle-states = <&CPU_PW20>;
0022 next-level-cache = <&cluster0_l2>;
0023 #cooling-cells = <2>;
0024 };
0025
0026 cpu1: cpu@1 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a57";
0029 reg = <0x1>;
0030 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0031 cpu-idle-states = <&CPU_PW20>;
0032 next-level-cache = <&cluster0_l2>;
0033 #cooling-cells = <2>;
0034 };
0035
0036 cpu2: cpu@100 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a57";
0039 reg = <0x100>;
0040 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0041 cpu-idle-states = <&CPU_PW20>;
0042 next-level-cache = <&cluster1_l2>;
0043 #cooling-cells = <2>;
0044 };
0045
0046 cpu3: cpu@101 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a57";
0049 reg = <0x101>;
0050 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0051 cpu-idle-states = <&CPU_PW20>;
0052 next-level-cache = <&cluster1_l2>;
0053 #cooling-cells = <2>;
0054 };
0055
0056 cpu4: cpu@200 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a57";
0059 reg = <0x200>;
0060 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
0061 cpu-idle-states = <&CPU_PW20>;
0062 next-level-cache = <&cluster2_l2>;
0063 #cooling-cells = <2>;
0064 };
0065
0066 cpu5: cpu@201 {
0067 device_type = "cpu";
0068 compatible = "arm,cortex-a57";
0069 reg = <0x201>;
0070 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
0071 cpu-idle-states = <&CPU_PW20>;
0072 next-level-cache = <&cluster2_l2>;
0073 #cooling-cells = <2>;
0074 };
0075
0076 cpu6: cpu@300 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a57";
0079 reg = <0x300>;
0080 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
0081 next-level-cache = <&cluster3_l2>;
0082 cpu-idle-states = <&CPU_PW20>;
0083 #cooling-cells = <2>;
0084 };
0085
0086 cpu7: cpu@301 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a57";
0089 reg = <0x301>;
0090 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
0091 cpu-idle-states = <&CPU_PW20>;
0092 next-level-cache = <&cluster3_l2>;
0093 #cooling-cells = <2>;
0094 };
0095
0096 cluster0_l2: l2-cache0 {
0097 compatible = "cache";
0098 };
0099
0100 cluster1_l2: l2-cache1 {
0101 compatible = "cache";
0102 };
0103
0104 cluster2_l2: l2-cache2 {
0105 compatible = "cache";
0106 };
0107
0108 cluster3_l2: l2-cache3 {
0109 compatible = "cache";
0110 };
0111
0112 CPU_PW20: cpu-pw20 {
0113 compatible = "arm,idle-state";
0114 idle-state-name = "PW20";
0115 arm,psci-suspend-param = <0x00010000>;
0116 entry-latency-us = <2000>;
0117 exit-latency-us = <2000>;
0118 min-residency-us = <6000>;
0119 };
0120 };
0121
0122 &pcie1 {
0123 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0124 <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
0125
0126 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0127 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0128 };
0129
0130 &pcie2 {
0131 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
0132 <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
0133
0134 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0135 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0136 };
0137
0138 &pcie3 {
0139 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
0140 <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
0141
0142 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0143 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0144 };
0145
0146 &pcie4 {
0147 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
0148 <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
0149
0150 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0151 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0152 };
