0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for NXP Layerscape-1088A family SoC.
0004 *
0005 * Copyright 2017-2020 NXP
0006 *
0007 * Harninder Rai <harninder.rai@nxp.com>
0008 *
0009 */
0010 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013
0014 / {
0015 compatible = "fsl,ls1088a";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 crypto = &crypto;
0022 rtc1 = &ftm_alarm0;
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 /* We have 2 clusters having 4 Cortex-A53 cores each */
0030 cpu0: cpu@0 {
0031 device_type = "cpu";
0032 compatible = "arm,cortex-a53";
0033 reg = <0x0>;
0034 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0035 cpu-idle-states = <&CPU_PH20>;
0036 #cooling-cells = <2>;
0037 };
0038
0039 cpu1: cpu@1 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a53";
0042 reg = <0x1>;
0043 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0044 cpu-idle-states = <&CPU_PH20>;
0045 #cooling-cells = <2>;
0046 };
0047
0048 cpu2: cpu@2 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a53";
0051 reg = <0x2>;
0052 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0053 cpu-idle-states = <&CPU_PH20>;
0054 #cooling-cells = <2>;
0055 };
0056
0057 cpu3: cpu@3 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a53";
0060 reg = <0x3>;
0061 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0062 cpu-idle-states = <&CPU_PH20>;
0063 #cooling-cells = <2>;
0064 };
0065
0066 cpu4: cpu@100 {
0067 device_type = "cpu";
0068 compatible = "arm,cortex-a53";
0069 reg = <0x100>;
0070 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0071 cpu-idle-states = <&CPU_PH20>;
0072 #cooling-cells = <2>;
0073 };
0074
0075 cpu5: cpu@101 {
0076 device_type = "cpu";
0077 compatible = "arm,cortex-a53";
0078 reg = <0x101>;
0079 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0080 cpu-idle-states = <&CPU_PH20>;
0081 #cooling-cells = <2>;
0082 };
0083
0084 cpu6: cpu@102 {
0085 device_type = "cpu";
0086 compatible = "arm,cortex-a53";
0087 reg = <0x102>;
0088 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0089 cpu-idle-states = <&CPU_PH20>;
0090 #cooling-cells = <2>;
0091 };
0092
0093 cpu7: cpu@103 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a53";
0096 reg = <0x103>;
0097 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
0098 cpu-idle-states = <&CPU_PH20>;
0099 #cooling-cells = <2>;
0100 };
0101
0102 CPU_PH20: cpu-ph20 {
0103 compatible = "arm,idle-state";
0104 idle-state-name = "PH20";
0105 arm,psci-suspend-param = <0x0>;
0106 entry-latency-us = <1000>;
0107 exit-latency-us = <1000>;
0108 min-residency-us = <3000>;
0109 };
0110 };
0111
0112 gic: interrupt-controller@6000000 {
0113 compatible = "arm,gic-v3";
0114 #interrupt-cells = <3>;
0115 interrupt-controller;
0116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
0117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
0118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
0119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
0120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
0121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
0122 #address-cells = <2>;
0123 #size-cells = <2>;
0124 ranges;
0125
0126 its: gic-its@6020000 {
0127 compatible = "arm,gic-v3-its";
0128 msi-controller;
0129 reg = <0x0 0x6020000 0 0x20000>;
0130 };
0131 };
0132
0133 thermal-zones {
0134 core-cluster {
0135 polling-delay-passive = <1000>;
0136 polling-delay = <5000>;
0137 thermal-sensors = <&tmu 0>;
0138
0139 trips {
0140 core_cluster_alert: core-cluster-alert {
0141 temperature = <85000>;
0142 hysteresis = <2000>;
0143 type = "passive";
0144 };
0145
0146 core-cluster-crit {
0147 temperature = <95000>;
0148 hysteresis = <2000>;
0149 type = "critical";
0150 };
0151 };
0152
0153 cooling-maps {
0154 map0 {
0155 trip = <&core_cluster_alert>;
0156 cooling-device =
0157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0165 };
0166 };
0167 };
0168
0169 soc {
0170 polling-delay-passive = <1000>;
0171 polling-delay = <5000>;
0172 thermal-sensors = <&tmu 1>;
0173
0174 trips {
0175 soc-crit {
0176 temperature = <95000>;
0177 hysteresis = <2000>;
0178 type = "critical";
0179 };
0180 };
0181 };
0182 };
0183
0184 timer {
0185 compatible = "arm,armv8-timer";
0186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
0187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
0188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
0189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
0190 };
0191
0192 pmu {
0193 compatible = "arm,cortex-a53-pmu";
0194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0195 };
0196
0197 psci {
0198 compatible = "arm,psci-0.2";
0199 method = "smc";
0200 };
0201
0202 sysclk: sysclk {
0203 compatible = "fixed-clock";
0204 #clock-cells = <0>;
0205 clock-frequency = <100000000>;
0206 clock-output-names = "sysclk";
0207 };
0208
0209 reboot {
0210 compatible = "syscon-reboot";
0211 regmap = <&reset>;
0212 offset = <0x0>;
0213 mask = <0x02>;
0214 };
0215
0216 soc {
0217 compatible = "simple-bus";
0218 #address-cells = <2>;
0219 #size-cells = <2>;
0220 ranges;
0221 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
0222
0223 clockgen: clocking@1300000 {
0224 compatible = "fsl,ls1088a-clockgen";
0225 reg = <0 0x1300000 0 0xa0000>;
0226 #clock-cells = <2>;
0227 clocks = <&sysclk>;
0228 };
0229
0230 dcfg: dcfg@1e00000 {
0231 compatible = "fsl,ls1088a-dcfg", "syscon";
0232 reg = <0x0 0x1e00000 0x0 0x10000>;
0233 little-endian;
0234 };
0235
0236 reset: syscon@1e60000 {
0237 compatible = "fsl,ls1088a-reset", "syscon";
0238 reg = <0x0 0x1e60000 0x0 0x10000>;
0239 };
0240
0241 isc: syscon@1f70000 {
0242 compatible = "fsl,ls1088a-isc", "syscon";
0243 reg = <0x0 0x1f70000 0x0 0x10000>;
0244 little-endian;
0245 #address-cells = <1>;
0246 #size-cells = <1>;
0247 ranges = <0x0 0x0 0x1f70000 0x10000>;
0248
0249 extirq: interrupt-controller@14 {
0250 compatible = "fsl,ls1088a-extirq";
0251 #interrupt-cells = <2>;
0252 #address-cells = <0>;
0253 interrupt-controller;
0254 reg = <0x14 4>;
0255 interrupt-map =
0256 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0257 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0258 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0259 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0260 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0261 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0262 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0263 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0264 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0265 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0266 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0267 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0268 interrupt-map-mask = <0xf 0x0>;
0269 };
0270 };
0271
0272 sfp: efuse@1e80000 {
0273 compatible = "fsl,ls1028a-sfp";
0274 reg = <0x0 0x1e80000 0x0 0x10000>;
0275 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0276 QORIQ_CLK_PLL_DIV(4)>;
0277 clock-names = "sfp";
0278 };
0279
0280 tmu: tmu@1f80000 {
0281 compatible = "fsl,qoriq-tmu";
0282 reg = <0x0 0x1f80000 0x0 0x10000>;
0283 interrupts = <0 23 0x4>;
0284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
0285 fsl,tmu-calibration =
0286 /* Calibration data group 1 */
0287 <0x00000000 0x00000023
0288 0x00000001 0x0000002a
0289 0x00000002 0x00000030
0290 0x00000003 0x00000037
0291 0x00000004 0x0000003d
0292 0x00000005 0x00000044
0293 0x00000006 0x0000004a
0294 0x00000007 0x00000051
0295 0x00000008 0x00000057
0296 0x00000009 0x0000005e
0297 0x0000000a 0x00000064
0298 0x0000000b 0x0000006b
0299 /* Calibration data group 2 */
0300 0x00010000 0x00000022
0301 0x00010001 0x0000002a
0302 0x00010002 0x00000032
0303 0x00010003 0x0000003a
0304 0x00010004 0x00000042
0305 0x00010005 0x0000004a
0306 0x00010006 0x00000052
0307 0x00010007 0x0000005a
0308 0x00010008 0x00000062
0309 0x00010009 0x0000006a
0310 /* Calibration data group 3 */
0311 0x00020000 0x00000021
0312 0x00020001 0x0000002b
0313 0x00020002 0x00000035
0314 0x00020003 0x00000040
0315 0x00020004 0x0000004a
0316 0x00020005 0x00000054
0317 0x00020006 0x0000005e
0318 /* Calibration data group 4 */
0319 0x00030000 0x00000010
0320 0x00030001 0x0000001c
0321 0x00030002 0x00000027
0322 0x00030003 0x00000032
0323 0x00030004 0x0000003e
0324 0x00030005 0x00000049
0325 0x00030006 0x00000054
0326 0x00030007 0x00000060>;
0327 little-endian;
0328 #thermal-sensor-cells = <1>;
0329 };
0330
0331 dspi: spi@2100000 {
0332 compatible = "fsl,ls1088a-dspi",
0333 "fsl,ls1021a-v1.0-dspi";
0334 #address-cells = <1>;
0335 #size-cells = <0>;
0336 reg = <0x0 0x2100000 0x0 0x10000>;
0337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0338 clock-names = "dspi";
0339 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0340 QORIQ_CLK_PLL_DIV(2)>;
0341 spi-num-chipselects = <6>;
0342 status = "disabled";
0343 };
0344
0345 duart0: serial@21c0500 {
0346 compatible = "fsl,ns16550", "ns16550a";
0347 reg = <0x0 0x21c0500 0x0 0x100>;
0348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0349 QORIQ_CLK_PLL_DIV(4)>;
0350 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0351 status = "disabled";
0352 };
0353
0354 duart1: serial@21c0600 {
0355 compatible = "fsl,ns16550", "ns16550a";
0356 reg = <0x0 0x21c0600 0x0 0x100>;
0357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0358 QORIQ_CLK_PLL_DIV(4)>;
0359 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
0360 status = "disabled";
0361 };
0362
0363 gpio0: gpio@2300000 {
0364 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
0365 reg = <0x0 0x2300000 0x0 0x10000>;
0366 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
0367 little-endian;
0368 gpio-controller;
0369 #gpio-cells = <2>;
0370 interrupt-controller;
0371 #interrupt-cells = <2>;
0372 };
0373
0374 gpio1: gpio@2310000 {
0375 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
0376 reg = <0x0 0x2310000 0x0 0x10000>;
0377 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
0378 little-endian;
0379 gpio-controller;
0380 #gpio-cells = <2>;
0381 interrupt-controller;
0382 #interrupt-cells = <2>;
0383 };
0384
0385 gpio2: gpio@2320000 {
0386 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
0387 reg = <0x0 0x2320000 0x0 0x10000>;
0388 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
0389 little-endian;
0390 gpio-controller;
0391 #gpio-cells = <2>;
0392 interrupt-controller;
0393 #interrupt-cells = <2>;
0394 };
0395
0396 gpio3: gpio@2330000 {
0397 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
0398 reg = <0x0 0x2330000 0x0 0x10000>;
0399 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
0400 little-endian;
0401 gpio-controller;
0402 #gpio-cells = <2>;
0403 interrupt-controller;
0404 #interrupt-cells = <2>;
0405 };
0406
0407 ifc: memory-controller@2240000 {
0408 compatible = "fsl,ifc";
0409 reg = <0x0 0x2240000 0x0 0x20000>;
0410 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
0411 little-endian;
0412 #address-cells = <2>;
0413 #size-cells = <1>;
0414 status = "disabled";
0415 };
0416
0417 i2c0: i2c@2000000 {
0418 compatible = "fsl,vf610-i2c";
0419 #address-cells = <1>;
0420 #size-cells = <0>;
0421 reg = <0x0 0x2000000 0x0 0x10000>;
0422 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0424 QORIQ_CLK_PLL_DIV(8)>;
0425 status = "disabled";
0426 };
0427
0428 i2c1: i2c@2010000 {
0429 compatible = "fsl,vf610-i2c";
0430 #address-cells = <1>;
0431 #size-cells = <0>;
0432 reg = <0x0 0x2010000 0x0 0x10000>;
0433 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
0434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0435 QORIQ_CLK_PLL_DIV(8)>;
0436 status = "disabled";
0437 };
0438
0439 i2c2: i2c@2020000 {
0440 compatible = "fsl,vf610-i2c";
0441 #address-cells = <1>;
0442 #size-cells = <0>;
0443 reg = <0x0 0x2020000 0x0 0x10000>;
0444 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
0445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0446 QORIQ_CLK_PLL_DIV(8)>;
0447 status = "disabled";
0448 };
0449
0450 i2c3: i2c@2030000 {
0451 compatible = "fsl,vf610-i2c";
0452 #address-cells = <1>;
0453 #size-cells = <0>;
0454 reg = <0x0 0x2030000 0x0 0x10000>;
0455 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0457 QORIQ_CLK_PLL_DIV(8)>;
0458 status = "disabled";
0459 };
0460
0461 qspi: spi@20c0000 {
0462 compatible = "fsl,ls2080a-qspi";
0463 #address-cells = <1>;
0464 #size-cells = <0>;
0465 reg = <0x0 0x20c0000 0x0 0x10000>,
0466 <0x0 0x20000000 0x0 0x10000000>;
0467 reg-names = "QuadSPI", "QuadSPI-memory";
0468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0469 clock-names = "qspi_en", "qspi";
0470 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0471 QORIQ_CLK_PLL_DIV(4)>,
0472 <&clockgen QORIQ_CLK_PLATFORM_PLL
0473 QORIQ_CLK_PLL_DIV(4)>;
0474 status = "disabled";
0475 };
0476
0477 esdhc: esdhc@2140000 {
0478 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
0479 reg = <0x0 0x2140000 0x0 0x10000>;
0480 interrupts = <0 28 0x4>; /* Level high type */
0481 clock-frequency = <0>;
0482 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
0483 voltage-ranges = <1800 1800 3300 3300>;
0484 sdhci,auto-cmd12;
0485 little-endian;
0486 bus-width = <4>;
0487 status = "disabled";
0488 };
0489
0490 usb0: usb@3100000 {
0491 compatible = "snps,dwc3";
0492 reg = <0x0 0x3100000 0x0 0x10000>;
0493 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
0494 dr_mode = "host";
0495 snps,quirk-frame-length-adjustment = <0x20>;
0496 snps,dis_rxdet_inp3_quirk;
0497 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0498 status = "disabled";
0499 };
0500
0501 usb1: usb@3110000 {
0502 compatible = "snps,dwc3";
0503 reg = <0x0 0x3110000 0x0 0x10000>;
0504 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
0505 dr_mode = "host";
0506 snps,quirk-frame-length-adjustment = <0x20>;
0507 snps,dis_rxdet_inp3_quirk;
0508 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0509 status = "disabled";
0510 };
0511
0512 sata: sata@3200000 {
0513 compatible = "fsl,ls1088a-ahci";
0514 reg = <0x0 0x3200000 0x0 0x10000>,
0515 <0x7 0x100520 0x0 0x4>;
0516 reg-names = "ahci", "sata-ecc";
0517 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
0518 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0519 QORIQ_CLK_PLL_DIV(4)>;
0520 dma-coherent;
0521 status = "disabled";
0522 };
0523
0524 crypto: crypto@8000000 {
0525 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
0526 fsl,sec-era = <8>;
0527 #address-cells = <1>;
0528 #size-cells = <1>;
0529 ranges = <0x0 0x00 0x8000000 0x100000>;
0530 reg = <0x00 0x8000000 0x0 0x100000>;
0531 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0532 dma-coherent;
0533
0534 sec_jr0: jr@10000 {
0535 compatible = "fsl,sec-v5.0-job-ring",
0536 "fsl,sec-v4.0-job-ring";
0537 reg = <0x10000 0x10000>;
0538 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0539 };
0540
0541 sec_jr1: jr@20000 {
0542 compatible = "fsl,sec-v5.0-job-ring",
0543 "fsl,sec-v4.0-job-ring";
0544 reg = <0x20000 0x10000>;
0545 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0546 };
0547
0548 sec_jr2: jr@30000 {
0549 compatible = "fsl,sec-v5.0-job-ring",
0550 "fsl,sec-v4.0-job-ring";
0551 reg = <0x30000 0x10000>;
0552 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0553 };
0554
0555 sec_jr3: jr@40000 {
0556 compatible = "fsl,sec-v5.0-job-ring",
0557 "fsl,sec-v4.0-job-ring";
0558 reg = <0x40000 0x10000>;
0559 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0560 };
0561 };
0562
0563 pcie1: pcie@3400000 {
0564 compatible = "fsl,ls1088a-pcie";
0565 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0566 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
0567 reg-names = "regs", "config";
0568 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
0569 interrupt-names = "aer";
0570 #address-cells = <3>;
0571 #size-cells = <2>;
0572 device_type = "pci";
0573 dma-coherent;
0574 num-viewport = <256>;
0575 bus-range = <0x0 0xff>;
0576 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0577 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0578 msi-parent = <&its>;
0579 #interrupt-cells = <1>;
0580 interrupt-map-mask = <0 0 0 7>;
0581 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
0582 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
0583 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
0584 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
0585 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0586 status = "disabled";
0587 };
0588
0589 pcie_ep1: pcie-ep@3400000 {
0590 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
0591 reg = <0x00 0x03400000 0x0 0x00100000>,
0592 <0x20 0x00000000 0x8 0x00000000>;
0593 reg-names = "regs", "addr_space";
0594 num-ib-windows = <24>;
0595 num-ob-windows = <256>;
0596 max-functions = /bits/ 8 <2>;
0597 status = "disabled";
0598 };
0599
0600 pcie2: pcie@3500000 {
0601 compatible = "fsl,ls1088a-pcie";
0602 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
0603 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
0604 reg-names = "regs", "config";
0605 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
0606 interrupt-names = "aer";
0607 #address-cells = <3>;
0608 #size-cells = <2>;
0609 device_type = "pci";
0610 dma-coherent;
0611 num-viewport = <6>;
0612 bus-range = <0x0 0xff>;
0613 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0614 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0615 msi-parent = <&its>;
0616 #interrupt-cells = <1>;
0617 interrupt-map-mask = <0 0 0 7>;
0618 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
0619 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
0620 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
0621 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
0622 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0623 status = "disabled";
0624 };
0625
0626 pcie_ep2: pcie-ep@3500000 {
0627 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
0628 reg = <0x00 0x03500000 0x0 0x00100000>,
0629 <0x28 0x00000000 0x8 0x00000000>;
0630 reg-names = "regs", "addr_space";
0631 num-ib-windows = <6>;
0632 num-ob-windows = <6>;
0633 status = "disabled";
0634 };
0635
0636 pcie3: pcie@3600000 {
0637 compatible = "fsl,ls1088a-pcie";
0638 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
0639 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
0640 reg-names = "regs", "config";
0641 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
0642 interrupt-names = "aer";
0643 #address-cells = <3>;
0644 #size-cells = <2>;
0645 device_type = "pci";
0646 dma-coherent;
0647 num-viewport = <6>;
0648 bus-range = <0x0 0xff>;
0649 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0650 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0651 msi-parent = <&its>;
0652 #interrupt-cells = <1>;
0653 interrupt-map-mask = <0 0 0 7>;
0654 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
0655 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
0656 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
0657 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
0658 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0659 status = "disabled";
0660 };
0661
0662 pcie_ep3: pcie-ep@3600000 {
0663 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
0664 reg = <0x00 0x03600000 0x0 0x00100000>,
0665 <0x30 0x00000000 0x8 0x00000000>;
0666 reg-names = "regs", "addr_space";
0667 num-ib-windows = <6>;
0668 num-ob-windows = <6>;
0669 status = "disabled";
0670 };
0671
0672 smmu: iommu@5000000 {
0673 compatible = "arm,mmu-500";
0674 reg = <0 0x5000000 0 0x800000>;
0675 #iommu-cells = <1>;
0676 stream-match-mask = <0x7C00>;
0677 #global-interrupts = <12>;
0678 // global secure fault
0679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0680 // combined secure
0681 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0682 // global non-secure fault
0683 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0684 // combined non-secure
0685 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0686 // performance counter interrupts 0-7
0687 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0688 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0689 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0690 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
0691 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
0692 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
0693 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
0694 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0695 // per context interrupt, 64 interrupts
0696 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0697 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0698 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0699 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0700 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0701 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0702 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0703 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0704 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0705 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0706 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
0707 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0708 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
0709 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
0710 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0711 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0712 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0713 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0714 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0715 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0716 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
0717 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0718 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0719 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0720 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0721 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0722 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
0723 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
0724 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
0725 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
0726 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
0727 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
0728 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
0729 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
0730 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
0731 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
0732 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0735 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0736 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
0737 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
0738 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
0739 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0740 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
0741 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
0742 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
0743 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
0744 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
0745 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
0746 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
0747 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0748 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0749 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0750 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0751 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0752 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0753 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0754 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0755 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0756 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0757 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0758 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0759 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0760 };
0761
0762 console@8340020 {
0763 compatible = "fsl,dpaa2-console";
0764 reg = <0x00000000 0x08340020 0 0x2>;
0765 };
0766
0767 ptp-timer@8b95000 {
0768 compatible = "fsl,dpaa2-ptp";
0769 reg = <0x0 0x8b95000 0x0 0x100>;
0770 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0771 QORIQ_CLK_PLL_DIV(1)>;
0772 little-endian;
0773 fsl,extts-fifo;
0774 };
0775
0776 emdio1: mdio@8b96000 {
0777 compatible = "fsl,fman-memac-mdio";
0778 reg = <0x0 0x8b96000 0x0 0x1000>;
0779 little-endian;
0780 #address-cells = <1>;
0781 #size-cells = <0>;
0782 status = "disabled";
0783 };
0784
0785 emdio2: mdio@8b97000 {
0786 compatible = "fsl,fman-memac-mdio";
0787 reg = <0x0 0x8b97000 0x0 0x1000>;
0788 little-endian;
0789 #address-cells = <1>;
0790 #size-cells = <0>;
0791 status = "disabled";
0792 };
0793
0794 pcs_mdio1: mdio@8c07000 {
0795 compatible = "fsl,fman-memac-mdio";
0796 reg = <0x0 0x8c07000 0x0 0x1000>;
0797 little-endian;
0798 #address-cells = <1>;
0799 #size-cells = <0>;
0800 status = "disabled";
0801
0802 pcs1: ethernet-phy@0 {
0803 reg = <0>;
0804 };
0805 };
0806
0807 pcs_mdio2: mdio@8c0b000 {
0808 compatible = "fsl,fman-memac-mdio";
0809 reg = <0x0 0x8c0b000 0x0 0x1000>;
0810 little-endian;
0811 #address-cells = <1>;
0812 #size-cells = <0>;
0813 status = "disabled";
0814
0815 pcs2: ethernet-phy@0 {
0816 reg = <0>;
0817 };
0818 };
0819
0820 pcs_mdio3: mdio@8c0f000 {
0821 compatible = "fsl,fman-memac-mdio";
0822 reg = <0x0 0x8c0f000 0x0 0x1000>;
0823 little-endian;
0824 #address-cells = <1>;
0825 #size-cells = <0>;
0826 status = "disabled";
0827
0828 pcs3_0: ethernet-phy@0 {
0829 reg = <0>;
0830 };
0831
0832 pcs3_1: ethernet-phy@1 {
0833 reg = <1>;
0834 };
0835
0836 pcs3_2: ethernet-phy@2 {
0837 reg = <2>;
0838 };
0839
0840 pcs3_3: ethernet-phy@3 {
0841 reg = <3>;
0842 };
0843 };
0844
0845 pcs_mdio7: mdio@8c1f000 {
0846 compatible = "fsl,fman-memac-mdio";
0847 reg = <0x0 0x8c1f000 0x0 0x1000>;
0848 little-endian;
0849 #address-cells = <1>;
0850 #size-cells = <0>;
0851 status = "disabled";
0852
0853 pcs7_0: ethernet-phy@0 {
0854 reg = <0>;
0855 };
0856
0857 pcs7_1: ethernet-phy@1 {
0858 reg = <1>;
0859 };
0860
0861 pcs7_2: ethernet-phy@2 {
0862 reg = <2>;
0863 };
0864
0865 pcs7_3: ethernet-phy@3 {
0866 reg = <3>;
0867 };
0868 };
0869
0870 cluster1_core0_watchdog: wdt@c000000 {
0871 compatible = "arm,sp805", "arm,primecell";
0872 reg = <0x0 0xc000000 0x0 0x1000>;
0873 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0874 QORIQ_CLK_PLL_DIV(16)>,
0875 <&clockgen QORIQ_CLK_PLATFORM_PLL
0876 QORIQ_CLK_PLL_DIV(16)>;
0877 clock-names = "wdog_clk", "apb_pclk";
0878 };
0879
0880 cluster1_core1_watchdog: wdt@c010000 {
0881 compatible = "arm,sp805", "arm,primecell";
0882 reg = <0x0 0xc010000 0x0 0x1000>;
0883 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0884 QORIQ_CLK_PLL_DIV(16)>,
0885 <&clockgen QORIQ_CLK_PLATFORM_PLL
0886 QORIQ_CLK_PLL_DIV(16)>;
0887 clock-names = "wdog_clk", "apb_pclk";
0888 };
0889
0890 cluster1_core2_watchdog: wdt@c020000 {
0891 compatible = "arm,sp805", "arm,primecell";
0892 reg = <0x0 0xc020000 0x0 0x1000>;
0893 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0894 QORIQ_CLK_PLL_DIV(16)>,
0895 <&clockgen QORIQ_CLK_PLATFORM_PLL
0896 QORIQ_CLK_PLL_DIV(16)>;
0897 clock-names = "wdog_clk", "apb_pclk";
0898 };
0899
0900 cluster1_core3_watchdog: wdt@c030000 {
0901 compatible = "arm,sp805", "arm,primecell";
0902 reg = <0x0 0xc030000 0x0 0x1000>;
0903 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0904 QORIQ_CLK_PLL_DIV(16)>,
0905 <&clockgen QORIQ_CLK_PLATFORM_PLL
0906 QORIQ_CLK_PLL_DIV(16)>;
0907 clock-names = "wdog_clk", "apb_pclk";
0908 };
0909
0910 cluster2_core0_watchdog: wdt@c100000 {
0911 compatible = "arm,sp805", "arm,primecell";
0912 reg = <0x0 0xc100000 0x0 0x1000>;
0913 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0914 QORIQ_CLK_PLL_DIV(16)>,
0915 <&clockgen QORIQ_CLK_PLATFORM_PLL
0916 QORIQ_CLK_PLL_DIV(16)>;
0917 clock-names = "wdog_clk", "apb_pclk";
0918 };
0919
0920 cluster2_core1_watchdog: wdt@c110000 {
0921 compatible = "arm,sp805", "arm,primecell";
0922 reg = <0x0 0xc110000 0x0 0x1000>;
0923 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0924 QORIQ_CLK_PLL_DIV(16)>,
0925 <&clockgen QORIQ_CLK_PLATFORM_PLL
0926 QORIQ_CLK_PLL_DIV(16)>;
0927 clock-names = "wdog_clk", "apb_pclk";
0928 };
0929
0930 cluster2_core2_watchdog: wdt@c120000 {
0931 compatible = "arm,sp805", "arm,primecell";
0932 reg = <0x0 0xc120000 0x0 0x1000>;
0933 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0934 QORIQ_CLK_PLL_DIV(16)>,
0935 <&clockgen QORIQ_CLK_PLATFORM_PLL
0936 QORIQ_CLK_PLL_DIV(16)>;
0937 clock-names = "wdog_clk", "apb_pclk";
0938 };
0939
0940 cluster2_core3_watchdog: wdt@c130000 {
0941 compatible = "arm,sp805", "arm,primecell";
0942 reg = <0x0 0xc130000 0x0 0x1000>;
0943 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0944 QORIQ_CLK_PLL_DIV(16)>,
0945 <&clockgen QORIQ_CLK_PLATFORM_PLL
0946 QORIQ_CLK_PLL_DIV(16)>;
0947 clock-names = "wdog_clk", "apb_pclk";
0948 };
0949
0950 fsl_mc: fsl-mc@80c000000 {
0951 compatible = "fsl,qoriq-mc";
0952 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
0953 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
0954 msi-parent = <&its>;
0955 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
0956 dma-coherent;
0957 #address-cells = <3>;
0958 #size-cells = <1>;
0959
0960 /*
0961 * Region type 0x0 - MC portals
0962 * Region type 0x1 - QBMAN portals
0963 */
0964 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0965 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
0966
0967 dpmacs {
0968 #address-cells = <1>;
0969 #size-cells = <0>;
0970
0971 dpmac1: ethernet@1 {
0972 compatible = "fsl,qoriq-mc-dpmac";
0973 reg = <1>;
0974 };
0975
0976 dpmac2: ethernet@2 {
0977 compatible = "fsl,qoriq-mc-dpmac";
0978 reg = <2>;
0979 };
0980
0981 dpmac3: ethernet@3 {
0982 compatible = "fsl,qoriq-mc-dpmac";
0983 reg = <3>;
0984 };
0985
0986 dpmac4: ethernet@4 {
0987 compatible = "fsl,qoriq-mc-dpmac";
0988 reg = <4>;
0989 };
0990
0991 dpmac5: ethernet@5 {
0992 compatible = "fsl,qoriq-mc-dpmac";
0993 reg = <5>;
0994 };
0995
0996 dpmac6: ethernet@6 {
0997 compatible = "fsl,qoriq-mc-dpmac";
0998 reg = <6>;
0999 };
1000
1001 dpmac7: ethernet@7 {
1002 compatible = "fsl,qoriq-mc-dpmac";
1003 reg = <7>;
1004 };
1005
1006 dpmac8: ethernet@8 {
1007 compatible = "fsl,qoriq-mc-dpmac";
1008 reg = <8>;
1009 };
1010
1011 dpmac9: ethernet@9 {
1012 compatible = "fsl,qoriq-mc-dpmac";
1013 reg = <9>;
1014 };
1015
1016 dpmac10: ethernet@a {
1017 compatible = "fsl,qoriq-mc-dpmac";
1018 reg = <0xa>;
1019 };
1020 };
1021 };
1022
1023 rcpm: power-controller@1e34040 {
1024 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1025 reg = <0x0 0x1e34040 0x0 0x18>;
1026 #fsl,rcpm-wakeup-cells = <6>;
1027 little-endian;
1028 };
1029
1030 ftm_alarm0: timer@2800000 {
1031 compatible = "fsl,ls1088a-ftm-alarm";
1032 reg = <0x0 0x2800000 0x0 0x10000>;
1033 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1034 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1035 };
1036 };
1037
1038 firmware {
1039 optee {
1040 compatible = "linaro,optee-tz";
1041 method = "smc";
1042 };
1043 };
1044 };
