0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for Travese Ten64 (LS1088) board
0004 * Based on fsl-ls1088a-rdb.dts
0005 * Copyright 2017-2020 NXP
0006 * Copyright 2019-2021 Traverse Technologies
0007 *
0008 * Author: Mathew McBride <matt@traverse.com.au>
0009 */
0010
0011 /dts-v1/;
0012
0013 #include "fsl-ls1088a.dtsi"
0014
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/input/input.h>
0017
0018 / {
0019 model = "Traverse Ten64";
0020 compatible = "traverse,ten64", "fsl,ls1088a";
0021
0022 aliases {
0023 serial0 = &duart0;
0024 serial1 = &duart1;
0025 };
0026
0027 chosen {
0028 stdout-path = "serial0:115200n8";
0029 };
0030
0031 buttons {
0032 compatible = "gpio-keys";
0033
0034 /* Fired by system controller when
0035 * external power off (e.g ATX Power Button)
0036 * asserted
0037 */
0038 button-powerdn {
0039 label = "External Power Down";
0040 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
0041 linux,code = <KEY_POWER>;
0042 };
0043
0044 /* Rear Panel 'ADMIN' button (GPIO_H) */
0045 button-admin {
0046 label = "ADMIN button";
0047 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
0048 linux,code = <KEY_WPS_BUTTON>;
0049 };
0050 };
0051
0052 leds {
0053 compatible = "gpio-leds";
0054
0055 led-0 {
0056 label = "ten64:green:sfp1:down";
0057 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
0058 };
0059
0060 led-1 {
0061 label = "ten64:green:sfp2:up";
0062 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
0063 };
0064
0065 led-2 {
0066 label = "ten64:admin";
0067 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
0068 };
0069 };
0070
0071 sfp_xg0: dpmac2-sfp {
0072 compatible = "sff,sfp";
0073 i2c-bus = <&sfplower_i2c>;
0074 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
0075 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
0076 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
0077 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
0078 maximum-power-milliwatt = <2000>;
0079 };
0080
0081 sfp_xg1: dpmac1-sfp {
0082 compatible = "sff,sfp";
0083 i2c-bus = <&sfpupper_i2c>;
0084 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
0085 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
0086 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
0087 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
0088 maximum-power-milliwatt = <2000>;
0089 };
0090 };
0091
0092 /* XG1 - Upper SFP */
0093 &dpmac1 {
0094 sfp = <&sfp_xg1>;
0095 pcs-handle = <&pcs1>;
0096 phy-connection-type = "10gbase-r";
0097 managed = "in-band-status";
0098 };
0099
0100 /* XG0 - Lower SFP */
0101 &dpmac2 {
0102 sfp = <&sfp_xg0>;
0103 pcs-handle = <&pcs2>;
0104 phy-connection-type = "10gbase-r";
0105 managed = "in-band-status";
0106 };
0107
0108 /* DPMAC3..6 is GE4 to GE8 */
0109 &dpmac3 {
0110 phy-handle = <&mdio1_phy5>;
0111 phy-connection-type = "qsgmii";
0112 managed = "in-band-status";
0113 pcs-handle = <&pcs3_0>;
0114 };
0115
0116 &dpmac4 {
0117 phy-handle = <&mdio1_phy6>;
0118 phy-connection-type = "qsgmii";
0119 managed = "in-band-status";
0120 pcs-handle = <&pcs3_1>;
0121 };
0122
0123 &dpmac5 {
0124 phy-handle = <&mdio1_phy7>;
0125 phy-connection-type = "qsgmii";
0126 managed = "in-band-status";
0127 pcs-handle = <&pcs3_2>;
0128 };
0129
0130 &dpmac6 {
0131 phy-handle = <&mdio1_phy8>;
0132 phy-connection-type = "qsgmii";
0133 managed = "in-band-status";
0134 pcs-handle = <&pcs3_3>;
0135 };
0136
0137 /* DPMAC7..10 is GE0 to GE3 */
0138 &dpmac7 {
0139 phy-handle = <&mdio1_phy1>;
0140 phy-connection-type = "qsgmii";
0141 managed = "in-band-status";
0142 pcs-handle = <&pcs7_0>;
0143 };
0144
0145 &dpmac8 {
0146 phy-handle = <&mdio1_phy2>;
0147 phy-connection-type = "qsgmii";
0148 managed = "in-band-status";
0149 pcs-handle = <&pcs7_1>;
0150 };
0151
0152 &dpmac9 {
0153 phy-handle = <&mdio1_phy3>;
0154 phy-connection-type = "qsgmii";
0155 managed = "in-band-status";
0156 pcs-handle = <&pcs7_2>;
0157 };
0158
0159 &dpmac10 {
0160 phy-handle = <&mdio1_phy4>;
0161 phy-connection-type = "qsgmii";
0162 managed = "in-band-status";
0163 pcs-handle = <&pcs7_3>;
0164 };
0165
0166 &duart0 {
0167 status = "okay";
0168 };
0169
0170 &duart1 {
0171 status = "okay";
0172 };
0173
0174 &emdio1 {
0175 status = "okay";
0176
0177 mdio1_phy5: ethernet-phy@c {
0178 reg = <0xc>;
0179 };
0180
0181 mdio1_phy6: ethernet-phy@d {
0182 reg = <0xd>;
0183 };
0184
0185 mdio1_phy7: ethernet-phy@e {
0186 reg = <0xe>;
0187 };
0188
0189 mdio1_phy8: ethernet-phy@f {
0190 reg = <0xf>;
0191 };
0192
0193 mdio1_phy1: ethernet-phy@1c {
0194 reg = <0x1c>;
0195 };
0196
0197 mdio1_phy2: ethernet-phy@1d {
0198 reg = <0x1d>;
0199 };
0200
0201 mdio1_phy3: ethernet-phy@1e {
0202 reg = <0x1e>;
0203 };
0204
0205 mdio1_phy4: ethernet-phy@1f {
0206 reg = <0x1f>;
0207 };
0208 };
0209
0210 &esdhc {
0211 status = "okay";
0212 };
0213
0214 &i2c0 {
0215 status = "okay";
0216
0217 sfpgpio: gpio@76 {
0218 compatible = "ti,tca9539";
0219 reg = <0x76>;
0220 #gpio-cells = <2>;
0221 gpio-controller;
0222
0223 admin_led_lower {
0224 gpio-hog;
0225 gpios = <13 GPIO_ACTIVE_HIGH>;
0226 output-low;
0227 };
0228 };
0229
0230 at97sc: tpm@29 {
0231 compatible = "atmel,at97sc3204t";
0232 reg = <0x29>;
0233 };
0234 };
0235
0236 &i2c2 {
0237 status = "okay";
0238
0239 rx8035: rtc@32 {
0240 compatible = "epson,rx8035";
0241 reg = <0x32>;
0242 };
0243 };
0244
0245 &i2c3 {
0246 status = "okay";
0247
0248 i2c-switch@70 {
0249 compatible = "nxp,pca9540";
0250 #address-cells = <1>;
0251 #size-cells = <0>;
0252 reg = <0x70>;
0253
0254 sfpupper_i2c: i2c@0 {
0255 #address-cells = <1>;
0256 #size-cells = <0>;
0257 reg = <0>;
0258 };
0259
0260 sfplower_i2c: i2c@1 {
0261 #address-cells = <1>;
0262 #size-cells = <0>;
0263 reg = <1>;
0264 };
0265 };
0266 };
0267
0268 &pcs_mdio1 {
0269 status = "okay";
0270 };
0271
0272 &pcs_mdio2 {
0273 status = "okay";
0274 };
0275
0276 &pcs_mdio3 {
0277 status = "okay";
0278 };
0279
0280 &pcs_mdio7 {
0281 status = "okay";
0282 };
0283
0284 &qspi {
0285 status = "okay";
0286
0287 en25s64: flash@0 {
0288 compatible = "jedec,spi-nor";
0289 #address-cells = <1>;
0290 #size-cells = <1>;
0291 reg = <0>;
0292 spi-max-frequency = <20000000>;
0293 spi-rx-bus-width = <4>;
0294 spi-tx-bus-width = <4>;
0295
0296 partitions {
0297 compatible = "fixed-partitions";
0298 #address-cells = <1>;
0299 #size-cells = <1>;
0300
0301 partition@0 {
0302 label = "bl2";
0303 reg = <0 0x100000>;
0304 };
0305
0306 partition@100000 {
0307 label = "bl3";
0308 reg = <0x100000 0x200000>;
0309 };
0310
0311 partition@300000 {
0312 label = "mcfirmware";
0313 reg = <0x300000 0x200000>;
0314 };
0315
0316 partition@500000 {
0317 label = "ubootenv";
0318 reg = <0x500000 0x80000>;
0319 };
0320
0321 partition@580000 {
0322 label = "dpl";
0323 reg = <0x580000 0x40000>;
0324 };
0325
0326 partition@5C0000 {
0327 label = "dpc";
0328 reg = <0x5C0000 0x40000>;
0329 };
0330
0331 partition@600000 {
0332 label = "devicetree";
0333 reg = <0x600000 0x40000>;
0334 };
0335 };
0336 };
0337
0338 nand: flash@1 {
0339 compatible = "spi-nand";
0340 #address-cells = <1>;
0341 #size-cells = <1>;
0342 reg = <1>;
0343 spi-max-frequency = <20000000>;
0344 spi-rx-bus-width = <4>;
0345 spi-tx-bus-width = <4>;
0346
0347 partitions {
0348 compatible = "fixed-partitions";
0349 #address-cells = <1>;
0350 #size-cells = <1>;
0351
0352 /* reserved for future boot direct from NAND flash
0353 * (this would use the same layout as the 8MiB NOR flash)
0354 */
0355 partition@0 {
0356 label = "nand-boot-reserved";
0357 reg = <0 0x800000>;
0358 };
0359
0360 /* recovery / install environment */
0361 partition@800000 {
0362 label = "recovery";
0363 reg = <0x800000 0x2000000>;
0364 };
0365
0366 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
0367 partition@2800000 {
0368 label = "ubia";
0369 reg = <0x2800000 0x6C00000>;
0370 };
0371
0372 /* ubib (second OpenWrt) */
0373 partition@9400000 {
0374 label = "ubib";
0375 reg = <0x9400000 0x6C00000>;
0376 };
0377 };
0378 };
0379 };
0380
0381 &usb0 {
0382 status = "okay";
0383 };
0384
0385 &usb1 {
0386 status = "okay";
0387 };
