0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for NXP LS1088A RDB Board.
0004 *
0005 * Copyright 2017-2020 NXP
0006 *
0007 * Harninder Rai <harninder.rai@nxp.com>
0008 *
0009 */
0010
0011 /dts-v1/;
0012
0013 #include "fsl-ls1088a.dtsi"
0014
0015 / {
0016 model = "LS1088A RDB Board";
0017 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
0018 };
0019
0020 &dpmac2 {
0021 phy-handle = <&mdio2_aquantia_phy>;
0022 phy-connection-type = "10gbase-r";
0023 pcs-handle = <&pcs2>;
0024 };
0025
0026 &dpmac3 {
0027 phy-handle = <&mdio1_phy5>;
0028 phy-connection-type = "qsgmii";
0029 managed = "in-band-status";
0030 pcs-handle = <&pcs3_0>;
0031 };
0032
0033 &dpmac4 {
0034 phy-handle = <&mdio1_phy6>;
0035 phy-connection-type = "qsgmii";
0036 managed = "in-band-status";
0037 pcs-handle = <&pcs3_1>;
0038 };
0039
0040 &dpmac5 {
0041 phy-handle = <&mdio1_phy7>;
0042 phy-connection-type = "qsgmii";
0043 managed = "in-band-status";
0044 pcs-handle = <&pcs3_2>;
0045 };
0046
0047 &dpmac6 {
0048 phy-handle = <&mdio1_phy8>;
0049 phy-connection-type = "qsgmii";
0050 managed = "in-band-status";
0051 pcs-handle = <&pcs3_3>;
0052 };
0053
0054 &dpmac7 {
0055 phy-handle = <&mdio1_phy1>;
0056 phy-connection-type = "qsgmii";
0057 managed = "in-band-status";
0058 pcs-handle = <&pcs7_0>;
0059 };
0060
0061 &dpmac8 {
0062 phy-handle = <&mdio1_phy2>;
0063 phy-connection-type = "qsgmii";
0064 managed = "in-band-status";
0065 pcs-handle = <&pcs7_1>;
0066 };
0067
0068 &dpmac9 {
0069 phy-handle = <&mdio1_phy3>;
0070 phy-connection-type = "qsgmii";
0071 managed = "in-band-status";
0072 pcs-handle = <&pcs7_2>;
0073 };
0074
0075 &dpmac10 {
0076 phy-handle = <&mdio1_phy4>;
0077 phy-connection-type = "qsgmii";
0078 managed = "in-band-status";
0079 pcs-handle = <&pcs7_3>;
0080 };
0081
0082 &emdio1 {
0083 status = "okay";
0084
0085 mdio1_phy5: ethernet-phy@c {
0086 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0087 reg = <0xc>;
0088 };
0089
0090 mdio1_phy6: ethernet-phy@d {
0091 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0092 reg = <0xd>;
0093 };
0094
0095 mdio1_phy7: ethernet-phy@e {
0096 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0097 reg = <0xe>;
0098 };
0099
0100 mdio1_phy8: ethernet-phy@f {
0101 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0102 reg = <0xf>;
0103 };
0104
0105 mdio1_phy1: ethernet-phy@1c {
0106 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0107 reg = <0x1c>;
0108 };
0109
0110 mdio1_phy2: ethernet-phy@1d {
0111 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0112 reg = <0x1d>;
0113 };
0114
0115 mdio1_phy3: ethernet-phy@1e {
0116 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0117 reg = <0x1e>;
0118 };
0119
0120 mdio1_phy4: ethernet-phy@1f {
0121 interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
0122 reg = <0x1f>;
0123 };
0124 };
0125
0126 &emdio2 {
0127 status = "okay";
0128
0129 mdio2_aquantia_phy: ethernet-phy@0 {
0130 compatible = "ethernet-phy-ieee802.3-c45";
0131 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
0132 reg = <0x0>;
0133 };
0134 };
0135
0136 &i2c0 {
0137 status = "okay";
0138
0139 i2c-switch@77 {
0140 compatible = "nxp,pca9547";
0141 reg = <0x77>;
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144
0145 i2c@2 {
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 reg = <0x2>;
0149
0150 ina220@40 {
0151 compatible = "ti,ina220";
0152 reg = <0x40>;
0153 shunt-resistor = <1000>;
0154 };
0155 };
0156
0157 i2c@3 {
0158 #address-cells = <1>;
0159 #size-cells = <0>;
0160 reg = <0x3>;
0161
0162 temp-sensor@4c {
0163 compatible = "adi,adt7461a";
0164 reg = <0x4c>;
0165 };
0166
0167 rtc@51 {
0168 compatible = "nxp,pcf2129";
0169 reg = <0x51>;
0170 /* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */
0171 interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>;
0172 };
0173 };
0174 };
0175 };
0176
0177 &ifc {
0178 ranges = <0 0 0x5 0x30000000 0x00010000
0179 2 0 0x5 0x20000000 0x00010000>;
0180 status = "okay";
0181
0182 nand@0,0 {
0183 compatible = "fsl,ifc-nand";
0184 reg = <0x0 0x0 0x10000>;
0185 };
0186
0187 fpga: board-control@2,0 {
0188 compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
0189 reg = <0x2 0x0 0x0000100>;
0190 };
0191 };
0192
0193 &duart0 {
0194 status = "okay";
0195 };
0196
0197 &duart1 {
0198 status = "okay";
0199 };
0200
0201 &esdhc {
0202 mmc-hs200-1_8v;
0203 status = "okay";
0204 };
0205
0206 &pcs_mdio2 {
0207 status = "okay";
0208 };
0209
0210 &pcs_mdio3 {
0211 status = "okay";
0212 };
0213
0214 &pcs_mdio7 {
0215 status = "okay";
0216 };
0217
0218 &qspi {
0219 status = "okay";
0220
0221 s25fs512s0: flash@0 {
0222 compatible = "jedec,spi-nor";
0223 #address-cells = <1>;
0224 #size-cells = <1>;
0225 spi-max-frequency = <50000000>;
0226 spi-rx-bus-width = <4>;
0227 spi-tx-bus-width = <1>;
0228 reg = <0>;
0229 };
0230
0231 s25fs512s1: flash@1 {
0232 compatible = "jedec,spi-nor";
0233 #address-cells = <1>;
0234 #size-cells = <1>;
0235 spi-max-frequency = <50000000>;
0236 spi-rx-bus-width = <4>;
0237 spi-tx-bus-width = <1>;
0238 reg = <1>;
0239 };
0240 };
0241
0242 &sata {
0243 status = "okay";
0244 };
0245
0246 &usb0 {
0247 status = "okay";
0248 };
0249
0250 &usb1 {
0251 dr_mode = "otg";
0252 status = "okay";
0253 };
