0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
0004 *
0005 * Copyright 2016 Freescale Semiconductor, Inc.
0006 * Copyright 2018 NXP
0007 *
0008 * Shaohui Xie <Shaohui.Xie@nxp.com>
0009 */
0010
0011 /dts-v1/;
0012
0013 #include "fsl-ls1046a.dtsi"
0014
0015 / {
0016 model = "LS1046A QDS Board";
0017 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
0018
0019 aliases {
0020 gpio0 = &gpio0;
0021 gpio1 = &gpio1;
0022 gpio2 = &gpio2;
0023 gpio3 = &gpio3;
0024 serial0 = &duart0;
0025 serial1 = &duart1;
0026 serial2 = &duart2;
0027 serial3 = &duart3;
0028 };
0029
0030 chosen {
0031 stdout-path = "serial0:115200n8";
0032 };
0033 };
0034
0035 &dspi {
0036 bus-num = <0>;
0037 status = "okay";
0038
0039 flash@0 {
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 compatible = "n25q128a11", "jedec,spi-nor";
0043 reg = <0>;
0044 spi-max-frequency = <10000000>;
0045 };
0046
0047 flash@1 {
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 compatible = "sst25wf040b", "jedec,spi-nor";
0051 spi-cpol;
0052 spi-cpha;
0053 reg = <1>;
0054 spi-max-frequency = <10000000>;
0055 };
0056
0057 flash@2 {
0058 #address-cells = <1>;
0059 #size-cells = <1>;
0060 compatible = "en25s64", "jedec,spi-nor";
0061 spi-cpol;
0062 spi-cpha;
0063 reg = <2>;
0064 spi-max-frequency = <10000000>;
0065 };
0066 };
0067
0068 &duart0 {
0069 status = "okay";
0070 };
0071
0072 &duart1 {
0073 status = "okay";
0074 };
0075
0076 &i2c0 {
0077 status = "okay";
0078
0079 pca9547@77 {
0080 compatible = "nxp,pca9547";
0081 reg = <0x77>;
0082 #address-cells = <1>;
0083 #size-cells = <0>;
0084
0085 i2c@2 {
0086 #address-cells = <1>;
0087 #size-cells = <0>;
0088 reg = <0x2>;
0089
0090 ina220@40 {
0091 compatible = "ti,ina220";
0092 reg = <0x40>;
0093 shunt-resistor = <1000>;
0094 };
0095
0096 ina220@41 {
0097 compatible = "ti,ina220";
0098 reg = <0x41>;
0099 shunt-resistor = <1000>;
0100 };
0101 };
0102
0103 i2c@3 {
0104 #address-cells = <1>;
0105 #size-cells = <0>;
0106 reg = <0x3>;
0107
0108 rtc@51 {
0109 compatible = "nxp,pcf2129";
0110 reg = <0x51>;
0111 /* IRQ10_B */
0112 interrupts = <0 150 0x4>;
0113 };
0114
0115 eeprom@56 {
0116 compatible = "atmel,24c512";
0117 reg = <0x56>;
0118 };
0119
0120 eeprom@57 {
0121 compatible = "atmel,24c512";
0122 reg = <0x57>;
0123 };
0124
0125 temp-sensor@4c {
0126 compatible = "adi,adt7461a";
0127 reg = <0x4c>;
0128 };
0129 };
0130 };
0131 };
0132
0133 &ifc {
0134 #address-cells = <2>;
0135 #size-cells = <1>;
0136 /* NOR, NAND Flashes and FPGA on board */
0137 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0138 0x1 0x0 0x0 0x7e800000 0x00010000
0139 0x2 0x0 0x0 0x7fb00000 0x00000100>;
0140 status = "okay";
0141
0142 nor@0,0 {
0143 compatible = "cfi-flash";
0144 reg = <0x0 0x0 0x8000000>;
0145 big-endian;
0146 bank-width = <2>;
0147 device-width = <1>;
0148 };
0149
0150 nand@1,0 {
0151 compatible = "fsl,ifc-nand";
0152 reg = <0x1 0x0 0x10000>;
0153 };
0154
0155 fpga: board-control@2,0 {
0156 compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
0157 reg = <0x2 0x0 0x0000100>;
0158 };
0159 };
0160
0161 &lpuart0 {
0162 status = "okay";
0163 };
0164
0165 &qspi {
0166 status = "okay";
0167
0168 qflash0: flash@0 {
0169 compatible = "spansion,m25p80";
0170 #address-cells = <1>;
0171 #size-cells = <1>;
0172 spi-max-frequency = <20000000>;
0173 spi-rx-bus-width = <4>;
0174 spi-tx-bus-width = <4>;
0175 reg = <0>;
0176 };
0177 };
0178
0179 #include "fsl-ls1046-post.dtsi"
