0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for NXP Layerscape-1043A family SoC.
0004 *
0005 * Copyright 2014-2015 Freescale Semiconductor, Inc.
0006 * Copyright 2018, 2020 NXP
0007 *
0008 * Mingkai Hu <Mingkai.hu@freescale.com>
0009 */
0010
0011 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014
0015 / {
0016 compatible = "fsl,ls1043a";
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 crypto = &crypto;
0023 fman0 = &fman0;
0024 ethernet0 = &enet0;
0025 ethernet1 = &enet1;
0026 ethernet2 = &enet2;
0027 ethernet3 = &enet3;
0028 ethernet4 = &enet4;
0029 ethernet5 = &enet5;
0030 ethernet6 = &enet6;
0031 rtc1 = &ftm_alarm0;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 /*
0039 * We expect the enable-method for cpu's to be "psci", but this
0040 * is dependent on the SoC FW, which will fill this in.
0041 *
0042 * Currently supported enable-method is psci v0.2
0043 */
0044 cpu0: cpu@0 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a53";
0047 reg = <0x0>;
0048 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0049 next-level-cache = <&l2>;
0050 cpu-idle-states = <&CPU_PH20>;
0051 #cooling-cells = <2>;
0052 };
0053
0054 cpu1: cpu@1 {
0055 device_type = "cpu";
0056 compatible = "arm,cortex-a53";
0057 reg = <0x1>;
0058 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0059 next-level-cache = <&l2>;
0060 cpu-idle-states = <&CPU_PH20>;
0061 #cooling-cells = <2>;
0062 };
0063
0064 cpu2: cpu@2 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a53";
0067 reg = <0x2>;
0068 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0069 next-level-cache = <&l2>;
0070 cpu-idle-states = <&CPU_PH20>;
0071 #cooling-cells = <2>;
0072 };
0073
0074 cpu3: cpu@3 {
0075 device_type = "cpu";
0076 compatible = "arm,cortex-a53";
0077 reg = <0x3>;
0078 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0079 next-level-cache = <&l2>;
0080 cpu-idle-states = <&CPU_PH20>;
0081 #cooling-cells = <2>;
0082 };
0083
0084 l2: l2-cache {
0085 compatible = "cache";
0086 };
0087 };
0088
0089 idle-states {
0090 /*
0091 * PSCI node is not added default, U-boot will add missing
0092 * parts if it determines to use PSCI.
0093 */
0094 entry-method = "psci";
0095
0096 CPU_PH20: cpu-ph20 {
0097 compatible = "arm,idle-state";
0098 idle-state-name = "PH20";
0099 arm,psci-suspend-param = <0x0>;
0100 entry-latency-us = <1000>;
0101 exit-latency-us = <1000>;
0102 min-residency-us = <3000>;
0103 };
0104 };
0105
0106 memory@80000000 {
0107 device_type = "memory";
0108 reg = <0x0 0x80000000 0 0x80000000>;
0109 /* DRAM space 1, size: 2GiB DRAM */
0110 };
0111
0112 reserved-memory {
0113 #address-cells = <2>;
0114 #size-cells = <2>;
0115 ranges;
0116
0117 bman_fbpr: bman-fbpr {
0118 compatible = "shared-dma-pool";
0119 size = <0 0x1000000>;
0120 alignment = <0 0x1000000>;
0121 no-map;
0122 };
0123
0124 qman_fqd: qman-fqd {
0125 compatible = "shared-dma-pool";
0126 size = <0 0x400000>;
0127 alignment = <0 0x400000>;
0128 no-map;
0129 };
0130
0131 qman_pfdr: qman-pfdr {
0132 compatible = "shared-dma-pool";
0133 size = <0 0x2000000>;
0134 alignment = <0 0x2000000>;
0135 no-map;
0136 };
0137 };
0138
0139 sysclk: sysclk {
0140 compatible = "fixed-clock";
0141 #clock-cells = <0>;
0142 clock-frequency = <100000000>;
0143 clock-output-names = "sysclk";
0144 };
0145
0146 reboot {
0147 compatible = "syscon-reboot";
0148 regmap = <&dcfg>;
0149 offset = <0xb0>;
0150 mask = <0x02>;
0151 };
0152
0153 thermal-zones {
0154 ddr-controller {
0155 polling-delay-passive = <1000>;
0156 polling-delay = <5000>;
0157 thermal-sensors = <&tmu 0>;
0158
0159 trips {
0160 ddr-ctrler-alert {
0161 temperature = <85000>;
0162 hysteresis = <2000>;
0163 type = "passive";
0164 };
0165
0166 ddr-ctrler-crit {
0167 temperature = <95000>;
0168 hysteresis = <2000>;
0169 type = "critical";
0170 };
0171 };
0172 };
0173
0174 serdes {
0175 polling-delay-passive = <1000>;
0176 polling-delay = <5000>;
0177 thermal-sensors = <&tmu 1>;
0178
0179 trips {
0180 serdes-alert {
0181 temperature = <85000>;
0182 hysteresis = <2000>;
0183 type = "passive";
0184 };
0185
0186 serdes-crit {
0187 temperature = <95000>;
0188 hysteresis = <2000>;
0189 type = "critical";
0190 };
0191 };
0192 };
0193
0194 fman {
0195 polling-delay-passive = <1000>;
0196 polling-delay = <5000>;
0197 thermal-sensors = <&tmu 2>;
0198
0199 trips {
0200 fman-alert {
0201 temperature = <85000>;
0202 hysteresis = <2000>;
0203 type = "passive";
0204 };
0205
0206 fman-crit {
0207 temperature = <95000>;
0208 hysteresis = <2000>;
0209 type = "critical";
0210 };
0211 };
0212 };
0213
0214 core-cluster {
0215 polling-delay-passive = <1000>;
0216 polling-delay = <5000>;
0217 thermal-sensors = <&tmu 3>;
0218
0219 trips {
0220 core_cluster_alert: core-cluster-alert {
0221 temperature = <85000>;
0222 hysteresis = <2000>;
0223 type = "passive";
0224 };
0225
0226 core_cluster_crit: core-cluster-crit {
0227 temperature = <95000>;
0228 hysteresis = <2000>;
0229 type = "critical";
0230 };
0231 };
0232
0233 cooling-maps {
0234 map0 {
0235 trip = <&core_cluster_alert>;
0236 cooling-device =
0237 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0238 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0239 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0240 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0241 };
0242 };
0243 };
0244
0245 sec {
0246 polling-delay-passive = <1000>;
0247 polling-delay = <5000>;
0248 thermal-sensors = <&tmu 4>;
0249
0250 trips {
0251 sec-alert {
0252 temperature = <85000>;
0253 hysteresis = <2000>;
0254 type = "passive";
0255 };
0256
0257 sec-crit {
0258 temperature = <95000>;
0259 hysteresis = <2000>;
0260 type = "critical";
0261 };
0262 };
0263 };
0264 };
0265
0266 timer {
0267 compatible = "arm,armv8-timer";
0268 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
0269 <1 14 0xf08>, /* Physical Non-Secure PPI */
0270 <1 11 0xf08>, /* Virtual PPI */
0271 <1 10 0xf08>; /* Hypervisor PPI */
0272 fsl,erratum-a008585;
0273 };
0274
0275 pmu {
0276 compatible = "arm,armv8-pmuv3";
0277 interrupts = <0 106 0x4>,
0278 <0 107 0x4>,
0279 <0 95 0x4>,
0280 <0 97 0x4>;
0281 interrupt-affinity = <&cpu0>,
0282 <&cpu1>,
0283 <&cpu2>,
0284 <&cpu3>;
0285 };
0286
0287 gic: interrupt-controller@1400000 {
0288 compatible = "arm,gic-400";
0289 #interrupt-cells = <3>;
0290 interrupt-controller;
0291 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
0292 <0x0 0x1402000 0 0x2000>, /* GICC */
0293 <0x0 0x1404000 0 0x2000>, /* GICH */
0294 <0x0 0x1406000 0 0x2000>; /* GICV */
0295 interrupts = <1 9 0xf08>;
0296 };
0297
0298 soc: soc {
0299 compatible = "simple-bus";
0300 #address-cells = <2>;
0301 #size-cells = <2>;
0302 ranges;
0303
0304 clockgen: clocking@1ee1000 {
0305 compatible = "fsl,ls1043a-clockgen";
0306 reg = <0x0 0x1ee1000 0x0 0x1000>;
0307 #clock-cells = <2>;
0308 clocks = <&sysclk>;
0309 };
0310
0311 scfg: scfg@1570000 {
0312 compatible = "fsl,ls1043a-scfg", "syscon";
0313 reg = <0x0 0x1570000 0x0 0x10000>;
0314 big-endian;
0315 #address-cells = <1>;
0316 #size-cells = <1>;
0317 ranges = <0x0 0x0 0x1570000 0x10000>;
0318
0319 extirq: interrupt-controller@1ac {
0320 compatible = "fsl,ls1043a-extirq";
0321 #interrupt-cells = <2>;
0322 #address-cells = <0>;
0323 interrupt-controller;
0324 reg = <0x1ac 4>;
0325 interrupt-map =
0326 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0327 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0328 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0329 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0330 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0331 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0332 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0333 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0334 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0335 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0336 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0337 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0338 interrupt-map-mask = <0xf 0x0>;
0339 };
0340 };
0341
0342 crypto: crypto@1700000 {
0343 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
0344 "fsl,sec-v4.0";
0345 fsl,sec-era = <3>;
0346 #address-cells = <1>;
0347 #size-cells = <1>;
0348 ranges = <0x0 0x00 0x1700000 0x100000>;
0349 reg = <0x00 0x1700000 0x0 0x100000>;
0350 interrupts = <0 75 0x4>;
0351 dma-coherent;
0352
0353 sec_jr0: jr@10000 {
0354 compatible = "fsl,sec-v5.4-job-ring",
0355 "fsl,sec-v5.0-job-ring",
0356 "fsl,sec-v4.0-job-ring";
0357 reg = <0x10000 0x10000>;
0358 interrupts = <0 71 0x4>;
0359 };
0360
0361 sec_jr1: jr@20000 {
0362 compatible = "fsl,sec-v5.4-job-ring",
0363 "fsl,sec-v5.0-job-ring",
0364 "fsl,sec-v4.0-job-ring";
0365 reg = <0x20000 0x10000>;
0366 interrupts = <0 72 0x4>;
0367 };
0368
0369 sec_jr2: jr@30000 {
0370 compatible = "fsl,sec-v5.4-job-ring",
0371 "fsl,sec-v5.0-job-ring",
0372 "fsl,sec-v4.0-job-ring";
0373 reg = <0x30000 0x10000>;
0374 interrupts = <0 73 0x4>;
0375 };
0376
0377 sec_jr3: jr@40000 {
0378 compatible = "fsl,sec-v5.4-job-ring",
0379 "fsl,sec-v5.0-job-ring",
0380 "fsl,sec-v4.0-job-ring";
0381 reg = <0x40000 0x10000>;
0382 interrupts = <0 74 0x4>;
0383 };
0384 };
0385
0386 sfp: efuse@1e80000 {
0387 compatible = "fsl,ls1021a-sfp";
0388 reg = <0x0 0x1e80000 0x0 0x10000>;
0389 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0390 QORIQ_CLK_PLL_DIV(4)>;
0391 clock-names = "sfp";
0392 };
0393
0394 dcfg: dcfg@1ee0000 {
0395 compatible = "fsl,ls1043a-dcfg", "syscon";
0396 reg = <0x0 0x1ee0000 0x0 0x10000>;
0397 big-endian;
0398 };
0399
0400 ifc: memory-controller@1530000 {
0401 compatible = "fsl,ifc";
0402 reg = <0x0 0x1530000 0x0 0x10000>;
0403 interrupts = <0 43 0x4>;
0404 };
0405
0406 qspi: spi@1550000 {
0407 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 reg = <0x0 0x1550000 0x0 0x10000>,
0411 <0x0 0x40000000 0x0 0x4000000>;
0412 reg-names = "QuadSPI", "QuadSPI-memory";
0413 interrupts = <0 99 0x4>;
0414 clock-names = "qspi_en", "qspi";
0415 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0416 QORIQ_CLK_PLL_DIV(1)>,
0417 <&clockgen QORIQ_CLK_PLATFORM_PLL
0418 QORIQ_CLK_PLL_DIV(1)>;
0419 status = "disabled";
0420 };
0421
0422 esdhc: esdhc@1560000 {
0423 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
0424 reg = <0x0 0x1560000 0x0 0x10000>;
0425 interrupts = <0 62 0x4>;
0426 clock-frequency = <0>;
0427 voltage-ranges = <1800 1800 3300 3300>;
0428 sdhci,auto-cmd12;
0429 big-endian;
0430 bus-width = <4>;
0431 };
0432
0433 ddr: memory-controller@1080000 {
0434 compatible = "fsl,qoriq-memory-controller";
0435 reg = <0x0 0x1080000 0x0 0x1000>;
0436 interrupts = <0 144 0x4>;
0437 big-endian;
0438 };
0439
0440 tmu: tmu@1f00000 {
0441 compatible = "fsl,qoriq-tmu";
0442 reg = <0x0 0x1f00000 0x0 0x10000>;
0443 interrupts = <0 33 0x4>;
0444 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
0445 fsl,tmu-calibration = <0x00000000 0x00000023
0446 0x00000001 0x0000002a
0447 0x00000002 0x00000031
0448 0x00000003 0x00000037
0449 0x00000004 0x0000003e
0450 0x00000005 0x00000044
0451 0x00000006 0x0000004b
0452 0x00000007 0x00000051
0453 0x00000008 0x00000058
0454 0x00000009 0x0000005e
0455 0x0000000a 0x00000065
0456 0x0000000b 0x0000006b
0457
0458 0x00010000 0x00000023
0459 0x00010001 0x0000002b
0460 0x00010002 0x00000033
0461 0x00010003 0x0000003b
0462 0x00010004 0x00000043
0463 0x00010005 0x0000004b
0464 0x00010006 0x00000054
0465 0x00010007 0x0000005c
0466 0x00010008 0x00000064
0467 0x00010009 0x0000006c
0468
0469 0x00020000 0x00000021
0470 0x00020001 0x0000002c
0471 0x00020002 0x00000036
0472 0x00020003 0x00000040
0473 0x00020004 0x0000004b
0474 0x00020005 0x00000055
0475 0x00020006 0x0000005f
0476
0477 0x00030000 0x00000013
0478 0x00030001 0x0000001d
0479 0x00030002 0x00000028
0480 0x00030003 0x00000032
0481 0x00030004 0x0000003d
0482 0x00030005 0x00000047
0483 0x00030006 0x00000052
0484 0x00030007 0x0000005c>;
0485 #thermal-sensor-cells = <1>;
0486 };
0487
0488 qman: qman@1880000 {
0489 compatible = "fsl,qman";
0490 reg = <0x0 0x1880000 0x0 0x10000>;
0491 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0492 memory-region = <&qman_fqd &qman_pfdr>;
0493 };
0494
0495 bman: bman@1890000 {
0496 compatible = "fsl,bman";
0497 reg = <0x0 0x1890000 0x0 0x10000>;
0498 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0499 memory-region = <&bman_fbpr>;
0500 };
0501
0502 bportals: bman-portals@508000000 {
0503 ranges = <0x0 0x5 0x08000000 0x8000000>;
0504 };
0505
0506 qportals: qman-portals@500000000 {
0507 ranges = <0x0 0x5 0x00000000 0x8000000>;
0508 };
0509
0510 dspi0: spi@2100000 {
0511 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
0512 #address-cells = <1>;
0513 #size-cells = <0>;
0514 reg = <0x0 0x2100000 0x0 0x10000>;
0515 interrupts = <0 64 0x4>;
0516 clock-names = "dspi";
0517 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0518 QORIQ_CLK_PLL_DIV(1)>;
0519 spi-num-chipselects = <5>;
0520 big-endian;
0521 status = "disabled";
0522 };
0523
0524 dspi1: spi@2110000 {
0525 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 reg = <0x0 0x2110000 0x0 0x10000>;
0529 interrupts = <0 65 0x4>;
0530 clock-names = "dspi";
0531 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0532 QORIQ_CLK_PLL_DIV(1)>;
0533 spi-num-chipselects = <5>;
0534 big-endian;
0535 status = "disabled";
0536 };
0537
0538 i2c0: i2c@2180000 {
0539 compatible = "fsl,vf610-i2c";
0540 #address-cells = <1>;
0541 #size-cells = <0>;
0542 reg = <0x0 0x2180000 0x0 0x10000>;
0543 interrupts = <0 56 0x4>;
0544 clock-names = "i2c";
0545 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0546 QORIQ_CLK_PLL_DIV(1)>;
0547 dmas = <&edma0 1 38>,
0548 <&edma0 1 39>;
0549 dma-names = "rx", "tx";
0550 status = "disabled";
0551 };
0552
0553 i2c1: i2c@2190000 {
0554 compatible = "fsl,vf610-i2c";
0555 #address-cells = <1>;
0556 #size-cells = <0>;
0557 reg = <0x0 0x2190000 0x0 0x10000>;
0558 interrupts = <0 57 0x4>;
0559 clock-names = "i2c";
0560 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0561 QORIQ_CLK_PLL_DIV(1)>;
0562 status = "disabled";
0563 };
0564
0565 i2c2: i2c@21a0000 {
0566 compatible = "fsl,vf610-i2c";
0567 #address-cells = <1>;
0568 #size-cells = <0>;
0569 reg = <0x0 0x21a0000 0x0 0x10000>;
0570 interrupts = <0 58 0x4>;
0571 clock-names = "i2c";
0572 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0573 QORIQ_CLK_PLL_DIV(1)>;
0574 status = "disabled";
0575 };
0576
0577 i2c3: i2c@21b0000 {
0578 compatible = "fsl,vf610-i2c";
0579 #address-cells = <1>;
0580 #size-cells = <0>;
0581 reg = <0x0 0x21b0000 0x0 0x10000>;
0582 interrupts = <0 59 0x4>;
0583 clock-names = "i2c";
0584 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0585 QORIQ_CLK_PLL_DIV(1)>;
0586 status = "disabled";
0587 };
0588
0589 duart0: serial@21c0500 {
0590 compatible = "fsl,ns16550", "ns16550a";
0591 reg = <0x00 0x21c0500 0x0 0x100>;
0592 interrupts = <0 54 0x4>;
0593 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0594 QORIQ_CLK_PLL_DIV(1)>;
0595 };
0596
0597 duart1: serial@21c0600 {
0598 compatible = "fsl,ns16550", "ns16550a";
0599 reg = <0x00 0x21c0600 0x0 0x100>;
0600 interrupts = <0 54 0x4>;
0601 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0602 QORIQ_CLK_PLL_DIV(1)>;
0603 };
0604
0605 duart2: serial@21d0500 {
0606 compatible = "fsl,ns16550", "ns16550a";
0607 reg = <0x0 0x21d0500 0x0 0x100>;
0608 interrupts = <0 55 0x4>;
0609 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0610 QORIQ_CLK_PLL_DIV(1)>;
0611 };
0612
0613 duart3: serial@21d0600 {
0614 compatible = "fsl,ns16550", "ns16550a";
0615 reg = <0x0 0x21d0600 0x0 0x100>;
0616 interrupts = <0 55 0x4>;
0617 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0618 QORIQ_CLK_PLL_DIV(1)>;
0619 };
0620
0621 gpio1: gpio@2300000 {
0622 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
0623 reg = <0x0 0x2300000 0x0 0x10000>;
0624 interrupts = <0 66 0x4>;
0625 gpio-controller;
0626 #gpio-cells = <2>;
0627 interrupt-controller;
0628 #interrupt-cells = <2>;
0629 };
0630
0631 gpio2: gpio@2310000 {
0632 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
0633 reg = <0x0 0x2310000 0x0 0x10000>;
0634 interrupts = <0 67 0x4>;
0635 gpio-controller;
0636 #gpio-cells = <2>;
0637 interrupt-controller;
0638 #interrupt-cells = <2>;
0639 };
0640
0641 gpio3: gpio@2320000 {
0642 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
0643 reg = <0x0 0x2320000 0x0 0x10000>;
0644 interrupts = <0 68 0x4>;
0645 gpio-controller;
0646 #gpio-cells = <2>;
0647 interrupt-controller;
0648 #interrupt-cells = <2>;
0649 };
0650
0651 gpio4: gpio@2330000 {
0652 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
0653 reg = <0x0 0x2330000 0x0 0x10000>;
0654 interrupts = <0 134 0x4>;
0655 gpio-controller;
0656 #gpio-cells = <2>;
0657 interrupt-controller;
0658 #interrupt-cells = <2>;
0659 };
0660
0661 uqe: uqe@2400000 {
0662 #address-cells = <1>;
0663 #size-cells = <1>;
0664 compatible = "fsl,qe", "simple-bus";
0665 ranges = <0x0 0x0 0x2400000 0x40000>;
0666 reg = <0x0 0x2400000 0x0 0x480>;
0667 brg-frequency = <100000000>;
0668 bus-frequency = <200000000>;
0669 fsl,qe-num-riscs = <1>;
0670 fsl,qe-num-snums = <28>;
0671
0672 qeic: qeic@80 {
0673 compatible = "fsl,qe-ic";
0674 reg = <0x80 0x80>;
0675 #address-cells = <0>;
0676 interrupt-controller;
0677 #interrupt-cells = <1>;
0678 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0679 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0680 };
0681
0682 si1: si@700 {
0683 #address-cells = <1>;
0684 #size-cells = <0>;
0685 compatible = "fsl,ls1043-qe-si",
0686 "fsl,t1040-qe-si";
0687 reg = <0x700 0x80>;
0688 };
0689
0690 siram1: siram@1000 {
0691 #address-cells = <1>;
0692 #size-cells = <1>;
0693 compatible = "fsl,ls1043-qe-siram",
0694 "fsl,t1040-qe-siram";
0695 reg = <0x1000 0x800>;
0696 };
0697
0698 ucc@2000 {
0699 cell-index = <1>;
0700 reg = <0x2000 0x200>;
0701 interrupts = <32>;
0702 interrupt-parent = <&qeic>;
0703 };
0704
0705 ucc@2200 {
0706 cell-index = <3>;
0707 reg = <0x2200 0x200>;
0708 interrupts = <34>;
0709 interrupt-parent = <&qeic>;
0710 };
0711
0712 muram@10000 {
0713 #address-cells = <1>;
0714 #size-cells = <1>;
0715 compatible = "fsl,qe-muram", "fsl,cpm-muram";
0716 ranges = <0x0 0x10000 0x6000>;
0717
0718 data-only@0 {
0719 compatible = "fsl,qe-muram-data",
0720 "fsl,cpm-muram-data";
0721 reg = <0x0 0x6000>;
0722 };
0723 };
0724 };
0725
0726 lpuart0: serial@2950000 {
0727 compatible = "fsl,ls1021a-lpuart";
0728 reg = <0x0 0x2950000 0x0 0x1000>;
0729 interrupts = <0 48 0x4>;
0730 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
0731 clock-names = "ipg";
0732 status = "disabled";
0733 };
0734
0735 lpuart1: serial@2960000 {
0736 compatible = "fsl,ls1021a-lpuart";
0737 reg = <0x0 0x2960000 0x0 0x1000>;
0738 interrupts = <0 49 0x4>;
0739 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0740 QORIQ_CLK_PLL_DIV(1)>;
0741 clock-names = "ipg";
0742 status = "disabled";
0743 };
0744
0745 lpuart2: serial@2970000 {
0746 compatible = "fsl,ls1021a-lpuart";
0747 reg = <0x0 0x2970000 0x0 0x1000>;
0748 interrupts = <0 50 0x4>;
0749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0750 QORIQ_CLK_PLL_DIV(1)>;
0751 clock-names = "ipg";
0752 status = "disabled";
0753 };
0754
0755 lpuart3: serial@2980000 {
0756 compatible = "fsl,ls1021a-lpuart";
0757 reg = <0x0 0x2980000 0x0 0x1000>;
0758 interrupts = <0 51 0x4>;
0759 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0760 QORIQ_CLK_PLL_DIV(1)>;
0761 clock-names = "ipg";
0762 status = "disabled";
0763 };
0764
0765 lpuart4: serial@2990000 {
0766 compatible = "fsl,ls1021a-lpuart";
0767 reg = <0x0 0x2990000 0x0 0x1000>;
0768 interrupts = <0 52 0x4>;
0769 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0770 QORIQ_CLK_PLL_DIV(1)>;
0771 clock-names = "ipg";
0772 status = "disabled";
0773 };
0774
0775 lpuart5: serial@29a0000 {
0776 compatible = "fsl,ls1021a-lpuart";
0777 reg = <0x0 0x29a0000 0x0 0x1000>;
0778 interrupts = <0 53 0x4>;
0779 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0780 QORIQ_CLK_PLL_DIV(1)>;
0781 clock-names = "ipg";
0782 status = "disabled";
0783 };
0784
0785 wdog0: watchdog@2ad0000 {
0786 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
0787 reg = <0x0 0x2ad0000 0x0 0x10000>;
0788 interrupts = <0 83 0x4>;
0789 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0790 QORIQ_CLK_PLL_DIV(1)>;
0791 clock-names = "wdog";
0792 big-endian;
0793 };
0794
0795 edma0: dma-controller@2c00000 {
0796 #dma-cells = <2>;
0797 compatible = "fsl,vf610-edma";
0798 reg = <0x0 0x2c00000 0x0 0x10000>,
0799 <0x0 0x2c10000 0x0 0x10000>,
0800 <0x0 0x2c20000 0x0 0x10000>;
0801 interrupts = <0 103 0x4>,
0802 <0 103 0x4>;
0803 interrupt-names = "edma-tx", "edma-err";
0804 dma-channels = <32>;
0805 big-endian;
0806 clock-names = "dmamux0", "dmamux1";
0807 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0808 QORIQ_CLK_PLL_DIV(1)>,
0809 <&clockgen QORIQ_CLK_PLATFORM_PLL
0810 QORIQ_CLK_PLL_DIV(1)>;
0811 };
0812
0813 usb0: usb@2f00000 {
0814 compatible = "snps,dwc3";
0815 reg = <0x0 0x2f00000 0x0 0x10000>;
0816 interrupts = <0 60 0x4>;
0817 dr_mode = "host";
0818 snps,quirk-frame-length-adjustment = <0x20>;
0819 snps,dis_rxdet_inp3_quirk;
0820 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0821 status = "disabled";
0822 };
0823
0824 usb1: usb@3000000 {
0825 compatible = "snps,dwc3";
0826 reg = <0x0 0x3000000 0x0 0x10000>;
0827 interrupts = <0 61 0x4>;
0828 dr_mode = "host";
0829 snps,quirk-frame-length-adjustment = <0x20>;
0830 snps,dis_rxdet_inp3_quirk;
0831 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0832 status = "disabled";
0833 };
0834
0835 usb2: usb@3100000 {
0836 compatible = "snps,dwc3";
0837 reg = <0x0 0x3100000 0x0 0x10000>;
0838 interrupts = <0 63 0x4>;
0839 dr_mode = "host";
0840 snps,quirk-frame-length-adjustment = <0x20>;
0841 snps,dis_rxdet_inp3_quirk;
0842 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0843 status = "disabled";
0844 };
0845
0846 sata: sata@3200000 {
0847 compatible = "fsl,ls1043a-ahci";
0848 reg = <0x0 0x3200000 0x0 0x10000>,
0849 <0x0 0x20140520 0x0 0x4>;
0850 reg-names = "ahci", "sata-ecc";
0851 interrupts = <0 69 0x4>;
0852 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0853 QORIQ_CLK_PLL_DIV(1)>;
0854 dma-coherent;
0855 };
0856
0857 msi1: msi-controller1@1571000 {
0858 compatible = "fsl,ls1043a-msi";
0859 reg = <0x0 0x1571000 0x0 0x8>;
0860 msi-controller;
0861 interrupts = <0 116 0x4>;
0862 };
0863
0864 msi2: msi-controller2@1572000 {
0865 compatible = "fsl,ls1043a-msi";
0866 reg = <0x0 0x1572000 0x0 0x8>;
0867 msi-controller;
0868 interrupts = <0 126 0x4>;
0869 };
0870
0871 msi3: msi-controller3@1573000 {
0872 compatible = "fsl,ls1043a-msi";
0873 reg = <0x0 0x1573000 0x0 0x8>;
0874 msi-controller;
0875 interrupts = <0 160 0x4>;
0876 };
0877
0878 pcie1: pcie@3400000 {
0879 compatible = "fsl,ls1043a-pcie";
0880 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0881 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
0882 reg-names = "regs", "config";
0883 interrupts = <0 118 0x4>, /* controller interrupt */
0884 <0 117 0x4>; /* PME interrupt */
0885 interrupt-names = "intr", "pme";
0886 #address-cells = <3>;
0887 #size-cells = <2>;
0888 device_type = "pci";
0889 dma-coherent;
0890 num-viewport = <6>;
0891 bus-range = <0x0 0xff>;
0892 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0893 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0894 msi-parent = <&msi1>, <&msi2>, <&msi3>;
0895 #interrupt-cells = <1>;
0896 interrupt-map-mask = <0 0 0 7>;
0897 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
0898 <0000 0 0 2 &gic 0 111 0x4>,
0899 <0000 0 0 3 &gic 0 112 0x4>,
0900 <0000 0 0 4 &gic 0 113 0x4>;
0901 status = "disabled";
0902 };
0903
0904 pcie2: pcie@3500000 {
0905 compatible = "fsl,ls1043a-pcie";
0906 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
0907 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
0908 reg-names = "regs", "config";
0909 interrupts = <0 128 0x4>,
0910 <0 127 0x4>;
0911 interrupt-names = "intr", "pme";
0912 #address-cells = <3>;
0913 #size-cells = <2>;
0914 device_type = "pci";
0915 dma-coherent;
0916 num-viewport = <6>;
0917 bus-range = <0x0 0xff>;
0918 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0919 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0920 msi-parent = <&msi1>, <&msi2>, <&msi3>;
0921 #interrupt-cells = <1>;
0922 interrupt-map-mask = <0 0 0 7>;
0923 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
0924 <0000 0 0 2 &gic 0 121 0x4>,
0925 <0000 0 0 3 &gic 0 122 0x4>,
0926 <0000 0 0 4 &gic 0 123 0x4>;
0927 status = "disabled";
0928 };
0929
0930 pcie3: pcie@3600000 {
0931 compatible = "fsl,ls1043a-pcie";
0932 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
0933 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
0934 reg-names = "regs", "config";
0935 interrupts = <0 162 0x4>,
0936 <0 161 0x4>;
0937 interrupt-names = "intr", "pme";
0938 #address-cells = <3>;
0939 #size-cells = <2>;
0940 device_type = "pci";
0941 dma-coherent;
0942 num-viewport = <6>;
0943 bus-range = <0x0 0xff>;
0944 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0945 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0946 msi-parent = <&msi1>, <&msi2>, <&msi3>;
0947 #interrupt-cells = <1>;
0948 interrupt-map-mask = <0 0 0 7>;
0949 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
0950 <0000 0 0 2 &gic 0 155 0x4>,
0951 <0000 0 0 3 &gic 0 156 0x4>,
0952 <0000 0 0 4 &gic 0 157 0x4>;
0953 status = "disabled";
0954 };
0955
0956 qdma: dma-controller@8380000 {
0957 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
0958 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
0959 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
0960 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
0961 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0962 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0963 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0964 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0965 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0966 interrupt-names = "qdma-error", "qdma-queue0",
0967 "qdma-queue1", "qdma-queue2", "qdma-queue3";
0968 dma-channels = <8>;
0969 block-number = <1>;
0970 block-offset = <0x10000>;
0971 fsl,dma-queues = <2>;
0972 status-sizes = <64>;
0973 queue-sizes = <64 64>;
0974 big-endian;
0975 };
0976
0977 rcpm: power-controller@1ee2140 {
0978 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
0979 reg = <0x0 0x1ee2140 0x0 0x4>;
0980 #fsl,rcpm-wakeup-cells = <1>;
0981 };
0982
0983 ftm_alarm0: timer@29d0000 {
0984 compatible = "fsl,ls1043a-ftm-alarm";
0985 reg = <0x0 0x29d0000 0x0 0x10000>;
0986 fsl,rcpm-wakeup = <&rcpm 0x20000>;
0987 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0988 big-endian;
0989 };
0990 };
0991
0992 firmware {
0993 optee {
0994 compatible = "linaro,optee-tz";
0995 method = "smc";
0996 };
0997 };
0998
0999 };
1000
1001 #include "qoriq-qman-portals.dtsi"
1002 #include "qoriq-bman-portals.dtsi"
