0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
0004 *
0005 * Copyright 2014-2015 Freescale Semiconductor, Inc.
0006 * Copyright 2018 NXP
0007 *
0008 * Mingkai Hu <Mingkai.hu@freescale.com>
0009 */
0010
0011 /dts-v1/;
0012 #include "fsl-ls1043a.dtsi"
0013
0014 / {
0015 model = "LS1043A RDB Board";
0016 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
0017
0018 aliases {
0019 serial0 = &duart0;
0020 serial1 = &duart1;
0021 serial2 = &duart2;
0022 serial3 = &duart3;
0023 };
0024
0025 chosen {
0026 stdout-path = "serial0:115200n8";
0027 };
0028 };
0029
0030 &i2c0 {
0031 status = "okay";
0032 ina220@40 {
0033 compatible = "ti,ina220";
0034 reg = <0x40>;
0035 shunt-resistor = <1000>;
0036 };
0037 adt7461a@4c {
0038 compatible = "adi,adt7461";
0039 reg = <0x4c>;
0040 };
0041 eeprom@52 {
0042 compatible = "atmel,24c512";
0043 reg = <0x52>;
0044 };
0045 eeprom@53 {
0046 compatible = "atmel,24c512";
0047 reg = <0x53>;
0048 };
0049 rtc@68 {
0050 compatible = "pericom,pt7c4338";
0051 reg = <0x68>;
0052 };
0053 };
0054
0055 &ifc {
0056 status = "okay";
0057 #address-cells = <2>;
0058 #size-cells = <1>;
0059 /* NOR, NAND Flashes and FPGA on board */
0060 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0061 0x1 0x0 0x0 0x7e800000 0x00010000
0062 0x2 0x0 0x0 0x7fb00000 0x00000100>;
0063
0064 nor@0,0 {
0065 compatible = "cfi-flash";
0066 #address-cells = <1>;
0067 #size-cells = <1>;
0068 reg = <0x0 0x0 0x8000000>;
0069 big-endian;
0070 bank-width = <2>;
0071 device-width = <1>;
0072 };
0073
0074 nand@1,0 {
0075 compatible = "fsl,ifc-nand";
0076 #address-cells = <1>;
0077 #size-cells = <1>;
0078 reg = <0x1 0x0 0x10000>;
0079 };
0080
0081 cpld: board-control@2,0 {
0082 compatible = "fsl,ls1043ardb-cpld";
0083 reg = <0x2 0x0 0x0000100>;
0084 };
0085 };
0086
0087 &dspi0 {
0088 bus-num = <0>;
0089 status = "okay";
0090
0091 flash@0 {
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
0095 reg = <0>;
0096 spi-max-frequency = <1000000>; /* input clock */
0097 fsl,spi-cs-sck-delay = <100>;
0098 fsl,spi-sck-cs-delay = <100>;
0099 };
0100
0101 slic@2 {
0102 compatible = "maxim,ds26522";
0103 reg = <2>;
0104 spi-max-frequency = <2000000>;
0105 fsl,spi-cs-sck-delay = <100>;
0106 fsl,spi-sck-cs-delay = <50>;
0107 };
0108
0109 slic@3 {
0110 compatible = "maxim,ds26522";
0111 reg = <3>;
0112 spi-max-frequency = <2000000>;
0113 fsl,spi-cs-sck-delay = <100>;
0114 fsl,spi-sck-cs-delay = <50>;
0115 };
0116 };
0117
0118 &duart0 {
0119 status = "okay";
0120 };
0121
0122 &duart1 {
0123 status = "okay";
0124 };
0125
0126 #include "fsl-ls1043-post.dtsi"
0127
0128 &fman0 {
0129 ethernet@e0000 {
0130 phy-handle = <&qsgmii_phy1>;
0131 phy-connection-type = "qsgmii";
0132 };
0133
0134 ethernet@e2000 {
0135 phy-handle = <&qsgmii_phy2>;
0136 phy-connection-type = "qsgmii";
0137 };
0138
0139 ethernet@e4000 {
0140 phy-handle = <&rgmii_phy1>;
0141 phy-connection-type = "rgmii-id";
0142 };
0143
0144 ethernet@e6000 {
0145 phy-handle = <&rgmii_phy2>;
0146 phy-connection-type = "rgmii-id";
0147 };
0148
0149 ethernet@e8000 {
0150 phy-handle = <&qsgmii_phy3>;
0151 phy-connection-type = "qsgmii";
0152 };
0153
0154 ethernet@ea000 {
0155 phy-handle = <&qsgmii_phy4>;
0156 phy-connection-type = "qsgmii";
0157 };
0158
0159 ethernet@f0000 { /* 10GEC1 */
0160 phy-handle = <&aqr105_phy>;
0161 phy-connection-type = "xgmii";
0162 };
0163
0164 mdio@fc000 {
0165 rgmii_phy1: ethernet-phy@1 {
0166 reg = <0x1>;
0167 };
0168
0169 rgmii_phy2: ethernet-phy@2 {
0170 reg = <0x2>;
0171 };
0172
0173 qsgmii_phy1: ethernet-phy@4 {
0174 reg = <0x4>;
0175 };
0176
0177 qsgmii_phy2: ethernet-phy@5 {
0178 reg = <0x5>;
0179 };
0180
0181 qsgmii_phy3: ethernet-phy@6 {
0182 reg = <0x6>;
0183 };
0184
0185 qsgmii_phy4: ethernet-phy@7 {
0186 reg = <0x7>;
0187 };
0188 };
0189
0190 mdio@fd000 {
0191 aqr105_phy: ethernet-phy@1 {
0192 compatible = "ethernet-phy-ieee802.3-c45";
0193 interrupts = <0 132 4>;
0194 reg = <0x1>;
0195 };
0196 };
0197 };
0198
0199 &uqe {
0200 ucc_hdlc: ucc@2000 {
0201 compatible = "fsl,ucc-hdlc";
0202 rx-clock-name = "clk8";
0203 tx-clock-name = "clk9";
0204 fsl,rx-sync-clock = "rsync_pin";
0205 fsl,tx-sync-clock = "tsync_pin";
0206 fsl,tx-timeslot-mask = <0xfffffffe>;
0207 fsl,rx-timeslot-mask = <0xfffffffe>;
0208 fsl,tdm-framer-type = "e1";
0209 fsl,tdm-id = <0>;
0210 fsl,siram-entry-id = <0>;
0211 fsl,tdm-interface;
0212 };
0213 };
0214
0215 &usb0 {
0216 status = "okay";
0217 };
0218
0219 &usb1 {
0220 status = "okay";
0221 };
