0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for NXP Layerscape-1028A family SoC.
0004 *
0005 * Copyright 2018-2020 NXP
0006 *
0007 * Harninder Rai <harninder.rai@nxp.com>
0008 *
0009 */
0010
0011 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 compatible = "fsl,ls1028a";
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu0: cpu@0 {
0026 device_type = "cpu";
0027 compatible = "arm,cortex-a72";
0028 reg = <0x0>;
0029 enable-method = "psci";
0030 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0031 next-level-cache = <&l2>;
0032 cpu-idle-states = <&CPU_PW20>;
0033 #cooling-cells = <2>;
0034 };
0035
0036 cpu1: cpu@1 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a72";
0039 reg = <0x1>;
0040 enable-method = "psci";
0041 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0042 next-level-cache = <&l2>;
0043 cpu-idle-states = <&CPU_PW20>;
0044 #cooling-cells = <2>;
0045 };
0046
0047 l2: l2-cache {
0048 compatible = "cache";
0049 };
0050 };
0051
0052 idle-states {
0053 /*
0054 * PSCI node is not added default, U-boot will add missing
0055 * parts if it determines to use PSCI.
0056 */
0057 entry-method = "psci";
0058
0059 CPU_PW20: cpu-pw20 {
0060 compatible = "arm,idle-state";
0061 idle-state-name = "PW20";
0062 arm,psci-suspend-param = <0x0>;
0063 entry-latency-us = <2000>;
0064 exit-latency-us = <2000>;
0065 min-residency-us = <6000>;
0066 };
0067 };
0068
0069 rtc_clk: rtc-clk {
0070 compatible = "fixed-clock";
0071 #clock-cells = <0>;
0072 clock-frequency = <32768>;
0073 clock-output-names = "rtc_clk";
0074 };
0075
0076 sysclk: sysclk {
0077 compatible = "fixed-clock";
0078 #clock-cells = <0>;
0079 clock-frequency = <100000000>;
0080 clock-output-names = "sysclk";
0081 };
0082
0083 osc_27m: clock-osc-27m {
0084 compatible = "fixed-clock";
0085 #clock-cells = <0>;
0086 clock-frequency = <27000000>;
0087 clock-output-names = "phy_27m";
0088 };
0089
0090 firmware {
0091 optee: optee {
0092 compatible = "linaro,optee-tz";
0093 method = "smc";
0094 status = "disabled";
0095 };
0096 };
0097
0098 reboot {
0099 compatible = "syscon-reboot";
0100 regmap = <&rst>;
0101 offset = <0>;
0102 mask = <0x02>;
0103 };
0104
0105 timer {
0106 compatible = "arm,armv8-timer";
0107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
0108 IRQ_TYPE_LEVEL_LOW)>,
0109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
0110 IRQ_TYPE_LEVEL_LOW)>,
0111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
0112 IRQ_TYPE_LEVEL_LOW)>,
0113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
0114 IRQ_TYPE_LEVEL_LOW)>;
0115 };
0116
0117 pmu {
0118 compatible = "arm,cortex-a72-pmu";
0119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0120 };
0121
0122 gic: interrupt-controller@6000000 {
0123 compatible = "arm,gic-v3";
0124 #address-cells = <2>;
0125 #size-cells = <2>;
0126 ranges;
0127 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
0128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
0129 #interrupt-cells = <3>;
0130 interrupt-controller;
0131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
0132 IRQ_TYPE_LEVEL_LOW)>;
0133 its: gic-its@6020000 {
0134 compatible = "arm,gic-v3-its";
0135 msi-controller;
0136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
0137 };
0138 };
0139
0140 thermal-zones {
0141 ddr-controller {
0142 polling-delay-passive = <1000>;
0143 polling-delay = <5000>;
0144 thermal-sensors = <&tmu 0>;
0145
0146 trips {
0147 ddr-ctrler-alert {
0148 temperature = <85000>;
0149 hysteresis = <2000>;
0150 type = "passive";
0151 };
0152
0153 ddr-ctrler-crit {
0154 temperature = <95000>;
0155 hysteresis = <2000>;
0156 type = "critical";
0157 };
0158 };
0159 };
0160
0161 core-cluster {
0162 polling-delay-passive = <1000>;
0163 polling-delay = <5000>;
0164 thermal-sensors = <&tmu 1>;
0165
0166 trips {
0167 core_cluster_alert: core-cluster-alert {
0168 temperature = <85000>;
0169 hysteresis = <2000>;
0170 type = "passive";
0171 };
0172
0173 core_cluster_crit: core-cluster-crit {
0174 temperature = <95000>;
0175 hysteresis = <2000>;
0176 type = "critical";
0177 };
0178 };
0179
0180 cooling-maps {
0181 map0 {
0182 trip = <&core_cluster_alert>;
0183 cooling-device =
0184 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0186 };
0187 };
0188 };
0189 };
0190
0191 soc: soc {
0192 compatible = "simple-bus";
0193 #address-cells = <2>;
0194 #size-cells = <2>;
0195 ranges;
0196
0197 ddr: memory-controller@1080000 {
0198 compatible = "fsl,qoriq-memory-controller";
0199 reg = <0x0 0x1080000 0x0 0x1000>;
0200 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0201 little-endian;
0202 };
0203
0204 dcfg: syscon@1e00000 {
0205 #address-cells = <1>;
0206 #size-cells = <1>;
0207 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
0208 reg = <0x0 0x1e00000 0x0 0x10000>;
0209 ranges = <0x0 0x0 0x1e00000 0x10000>;
0210 little-endian;
0211
0212 fspi_clk: clock-controller@900 {
0213 compatible = "fsl,ls1028a-flexspi-clk";
0214 reg = <0x900 0x4>;
0215 #clock-cells = <0>;
0216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
0217 clock-output-names = "fspi_clk";
0218 };
0219 };
0220
0221 rst: syscon@1e60000 {
0222 compatible = "syscon";
0223 reg = <0x0 0x1e60000 0x0 0x10000>;
0224 little-endian;
0225 };
0226
0227 sfp: efuse@1e80000 {
0228 compatible = "fsl,ls1028a-sfp";
0229 reg = <0x0 0x1e80000 0x0 0x10000>;
0230 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0231 QORIQ_CLK_PLL_DIV(4)>;
0232 clock-names = "sfp";
0233 #address-cells = <1>;
0234 #size-cells = <1>;
0235
0236 ls1028a_uid: unique-id@1c {
0237 reg = <0x1c 0x8>;
0238 };
0239 };
0240
0241 scfg: syscon@1fc0000 {
0242 compatible = "fsl,ls1028a-scfg", "syscon";
0243 reg = <0x0 0x1fc0000 0x0 0x10000>;
0244 big-endian;
0245 };
0246
0247 clockgen: clock-controller@1300000 {
0248 compatible = "fsl,ls1028a-clockgen";
0249 reg = <0x0 0x1300000 0x0 0xa0000>;
0250 #clock-cells = <2>;
0251 clocks = <&sysclk>;
0252 };
0253
0254 i2c0: i2c@2000000 {
0255 compatible = "fsl,vf610-i2c";
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 reg = <0x0 0x2000000 0x0 0x10000>;
0259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0260 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0261 QORIQ_CLK_PLL_DIV(4)>;
0262 status = "disabled";
0263 };
0264
0265 i2c1: i2c@2010000 {
0266 compatible = "fsl,vf610-i2c";
0267 #address-cells = <1>;
0268 #size-cells = <0>;
0269 reg = <0x0 0x2010000 0x0 0x10000>;
0270 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0271 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0272 QORIQ_CLK_PLL_DIV(4)>;
0273 status = "disabled";
0274 };
0275
0276 i2c2: i2c@2020000 {
0277 compatible = "fsl,vf610-i2c";
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 reg = <0x0 0x2020000 0x0 0x10000>;
0281 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0282 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0283 QORIQ_CLK_PLL_DIV(4)>;
0284 status = "disabled";
0285 };
0286
0287 i2c3: i2c@2030000 {
0288 compatible = "fsl,vf610-i2c";
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 reg = <0x0 0x2030000 0x0 0x10000>;
0292 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0293 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0294 QORIQ_CLK_PLL_DIV(4)>;
0295 status = "disabled";
0296 };
0297
0298 i2c4: i2c@2040000 {
0299 compatible = "fsl,vf610-i2c";
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 reg = <0x0 0x2040000 0x0 0x10000>;
0303 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0304 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0305 QORIQ_CLK_PLL_DIV(4)>;
0306 status = "disabled";
0307 };
0308
0309 i2c5: i2c@2050000 {
0310 compatible = "fsl,vf610-i2c";
0311 #address-cells = <1>;
0312 #size-cells = <0>;
0313 reg = <0x0 0x2050000 0x0 0x10000>;
0314 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0315 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0316 QORIQ_CLK_PLL_DIV(4)>;
0317 status = "disabled";
0318 };
0319
0320 i2c6: i2c@2060000 {
0321 compatible = "fsl,vf610-i2c";
0322 #address-cells = <1>;
0323 #size-cells = <0>;
0324 reg = <0x0 0x2060000 0x0 0x10000>;
0325 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0326 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0327 QORIQ_CLK_PLL_DIV(4)>;
0328 status = "disabled";
0329 };
0330
0331 i2c7: i2c@2070000 {
0332 compatible = "fsl,vf610-i2c";
0333 #address-cells = <1>;
0334 #size-cells = <0>;
0335 reg = <0x0 0x2070000 0x0 0x10000>;
0336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0337 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0338 QORIQ_CLK_PLL_DIV(4)>;
0339 status = "disabled";
0340 };
0341
0342 fspi: spi@20c0000 {
0343 compatible = "nxp,lx2160a-fspi";
0344 #address-cells = <1>;
0345 #size-cells = <0>;
0346 reg = <0x0 0x20c0000 0x0 0x10000>,
0347 <0x0 0x20000000 0x0 0x10000000>;
0348 reg-names = "fspi_base", "fspi_mmap";
0349 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0350 clocks = <&fspi_clk>, <&fspi_clk>;
0351 clock-names = "fspi_en", "fspi";
0352 status = "disabled";
0353 };
0354
0355 dspi0: spi@2100000 {
0356 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
0357 #address-cells = <1>;
0358 #size-cells = <0>;
0359 reg = <0x0 0x2100000 0x0 0x10000>;
0360 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0361 clock-names = "dspi";
0362 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0363 QORIQ_CLK_PLL_DIV(2)>;
0364 dmas = <&edma0 0 62>, <&edma0 0 60>;
0365 dma-names = "tx", "rx";
0366 spi-num-chipselects = <4>;
0367 little-endian;
0368 status = "disabled";
0369 };
0370
0371 dspi1: spi@2110000 {
0372 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
0373 #address-cells = <1>;
0374 #size-cells = <0>;
0375 reg = <0x0 0x2110000 0x0 0x10000>;
0376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0377 clock-names = "dspi";
0378 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0379 QORIQ_CLK_PLL_DIV(2)>;
0380 dmas = <&edma0 0 58>, <&edma0 0 56>;
0381 dma-names = "tx", "rx";
0382 spi-num-chipselects = <4>;
0383 little-endian;
0384 status = "disabled";
0385 };
0386
0387 dspi2: spi@2120000 {
0388 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
0389 #address-cells = <1>;
0390 #size-cells = <0>;
0391 reg = <0x0 0x2120000 0x0 0x10000>;
0392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0393 clock-names = "dspi";
0394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0395 QORIQ_CLK_PLL_DIV(2)>;
0396 dmas = <&edma0 0 54>, <&edma0 0 2>;
0397 dma-names = "tx", "rx";
0398 spi-num-chipselects = <3>;
0399 little-endian;
0400 status = "disabled";
0401 };
0402
0403 esdhc: mmc@2140000 {
0404 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
0405 reg = <0x0 0x2140000 0x0 0x10000>;
0406 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0407 clock-frequency = <0>; /* fixed up by bootloader */
0408 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
0409 voltage-ranges = <1800 1800 3300 3300>;
0410 sdhci,auto-cmd12;
0411 little-endian;
0412 bus-width = <4>;
0413 status = "disabled";
0414 };
0415
0416 esdhc1: mmc@2150000 {
0417 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
0418 reg = <0x0 0x2150000 0x0 0x10000>;
0419 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0420 clock-frequency = <0>; /* fixed up by bootloader */
0421 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
0422 voltage-ranges = <1800 1800>;
0423 sdhci,auto-cmd12;
0424 non-removable;
0425 little-endian;
0426 bus-width = <4>;
0427 status = "disabled";
0428 };
0429
0430 can0: can@2180000 {
0431 compatible = "fsl,lx2160ar1-flexcan";
0432 reg = <0x0 0x2180000 0x0 0x10000>;
0433 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0435 QORIQ_CLK_PLL_DIV(2)>,
0436 <&clockgen QORIQ_CLK_PLATFORM_PLL
0437 QORIQ_CLK_PLL_DIV(2)>;
0438 clock-names = "ipg", "per";
0439 status = "disabled";
0440 };
0441
0442 can1: can@2190000 {
0443 compatible = "fsl,lx2160ar1-flexcan";
0444 reg = <0x0 0x2190000 0x0 0x10000>;
0445 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0446 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0447 QORIQ_CLK_PLL_DIV(2)>,
0448 <&clockgen QORIQ_CLK_PLATFORM_PLL
0449 QORIQ_CLK_PLL_DIV(2)>;
0450 clock-names = "ipg", "per";
0451 status = "disabled";
0452 };
0453
0454 duart0: serial@21c0500 {
0455 compatible = "fsl,ns16550", "ns16550a";
0456 reg = <0x00 0x21c0500 0x0 0x100>;
0457 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0458 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0459 QORIQ_CLK_PLL_DIV(2)>;
0460 status = "disabled";
0461 };
0462
0463 duart1: serial@21c0600 {
0464 compatible = "fsl,ns16550", "ns16550a";
0465 reg = <0x00 0x21c0600 0x0 0x100>;
0466 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0467 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0468 QORIQ_CLK_PLL_DIV(2)>;
0469 status = "disabled";
0470 };
0471
0472
0473 lpuart0: serial@2260000 {
0474 compatible = "fsl,ls1028a-lpuart";
0475 reg = <0x0 0x2260000 0x0 0x1000>;
0476 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
0477 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0478 QORIQ_CLK_PLL_DIV(2)>;
0479 clock-names = "ipg";
0480 dma-names = "rx","tx";
0481 dmas = <&edma0 1 32>,
0482 <&edma0 1 33>;
0483 status = "disabled";
0484 };
0485
0486 lpuart1: serial@2270000 {
0487 compatible = "fsl,ls1028a-lpuart";
0488 reg = <0x0 0x2270000 0x0 0x1000>;
0489 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
0490 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0491 QORIQ_CLK_PLL_DIV(2)>;
0492 clock-names = "ipg";
0493 dma-names = "rx","tx";
0494 dmas = <&edma0 1 30>,
0495 <&edma0 1 31>;
0496 status = "disabled";
0497 };
0498
0499 lpuart2: serial@2280000 {
0500 compatible = "fsl,ls1028a-lpuart";
0501 reg = <0x0 0x2280000 0x0 0x1000>;
0502 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0504 QORIQ_CLK_PLL_DIV(2)>;
0505 clock-names = "ipg";
0506 dma-names = "rx","tx";
0507 dmas = <&edma0 1 28>,
0508 <&edma0 1 29>;
0509 status = "disabled";
0510 };
0511
0512 lpuart3: serial@2290000 {
0513 compatible = "fsl,ls1028a-lpuart";
0514 reg = <0x0 0x2290000 0x0 0x1000>;
0515 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
0516 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0517 QORIQ_CLK_PLL_DIV(2)>;
0518 clock-names = "ipg";
0519 dma-names = "rx","tx";
0520 dmas = <&edma0 1 26>,
0521 <&edma0 1 27>;
0522 status = "disabled";
0523 };
0524
0525 lpuart4: serial@22a0000 {
0526 compatible = "fsl,ls1028a-lpuart";
0527 reg = <0x0 0x22a0000 0x0 0x1000>;
0528 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
0529 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0530 QORIQ_CLK_PLL_DIV(2)>;
0531 clock-names = "ipg";
0532 dma-names = "rx","tx";
0533 dmas = <&edma0 1 24>,
0534 <&edma0 1 25>;
0535 status = "disabled";
0536 };
0537
0538 lpuart5: serial@22b0000 {
0539 compatible = "fsl,ls1028a-lpuart";
0540 reg = <0x0 0x22b0000 0x0 0x1000>;
0541 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
0542 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0543 QORIQ_CLK_PLL_DIV(2)>;
0544 clock-names = "ipg";
0545 dma-names = "rx","tx";
0546 dmas = <&edma0 1 22>,
0547 <&edma0 1 23>;
0548 status = "disabled";
0549 };
0550
0551 edma0: dma-controller@22c0000 {
0552 #dma-cells = <2>;
0553 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
0554 reg = <0x0 0x22c0000 0x0 0x10000>,
0555 <0x0 0x22d0000 0x0 0x10000>,
0556 <0x0 0x22e0000 0x0 0x10000>;
0557 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0558 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0559 interrupt-names = "edma-tx", "edma-err";
0560 dma-channels = <32>;
0561 clock-names = "dmamux0", "dmamux1";
0562 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0563 QORIQ_CLK_PLL_DIV(2)>,
0564 <&clockgen QORIQ_CLK_PLATFORM_PLL
0565 QORIQ_CLK_PLL_DIV(2)>;
0566 };
0567
0568 gpio1: gpio@2300000 {
0569 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
0570 reg = <0x0 0x2300000 0x0 0x10000>;
0571 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0572 gpio-controller;
0573 #gpio-cells = <2>;
0574 interrupt-controller;
0575 #interrupt-cells = <2>;
0576 little-endian;
0577 };
0578
0579 gpio2: gpio@2310000 {
0580 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
0581 reg = <0x0 0x2310000 0x0 0x10000>;
0582 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0583 gpio-controller;
0584 #gpio-cells = <2>;
0585 interrupt-controller;
0586 #interrupt-cells = <2>;
0587 little-endian;
0588 };
0589
0590 gpio3: gpio@2320000 {
0591 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
0592 reg = <0x0 0x2320000 0x0 0x10000>;
0593 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0594 gpio-controller;
0595 #gpio-cells = <2>;
0596 interrupt-controller;
0597 #interrupt-cells = <2>;
0598 little-endian;
0599 };
0600
0601 usb0: usb@3100000 {
0602 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
0603 reg = <0x0 0x3100000 0x0 0x10000>;
0604 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0605 snps,dis_rxdet_inp3_quirk;
0606 snps,quirk-frame-length-adjustment = <0x20>;
0607 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0608 status = "disabled";
0609 };
0610
0611 usb1: usb@3110000 {
0612 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
0613 reg = <0x0 0x3110000 0x0 0x10000>;
0614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0615 snps,dis_rxdet_inp3_quirk;
0616 snps,quirk-frame-length-adjustment = <0x20>;
0617 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0618 status = "disabled";
0619 };
0620
0621 sata: sata@3200000 {
0622 compatible = "fsl,ls1028a-ahci";
0623 reg = <0x0 0x3200000 0x0 0x10000>,
0624 <0x7 0x100520 0x0 0x4>;
0625 reg-names = "ahci", "sata-ecc";
0626 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0627 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0628 QORIQ_CLK_PLL_DIV(2)>;
0629 status = "disabled";
0630 };
0631
0632 pcie1: pcie@3400000 {
0633 compatible = "fsl,ls1028a-pcie";
0634 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0635 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
0636 reg-names = "regs", "config";
0637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
0638 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
0639 interrupt-names = "pme", "aer";
0640 #address-cells = <3>;
0641 #size-cells = <2>;
0642 device_type = "pci";
0643 dma-coherent;
0644 num-viewport = <8>;
0645 bus-range = <0x0 0xff>;
0646 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0647 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0648 msi-parent = <&its>;
0649 #interrupt-cells = <1>;
0650 interrupt-map-mask = <0 0 0 7>;
0651 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0652 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0653 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0654 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0655 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0656 status = "disabled";
0657 };
0658
0659 pcie_ep1: pcie-ep@3400000 {
0660 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
0661 reg = <0x00 0x03400000 0x0 0x00100000
0662 0x80 0x00000000 0x8 0x00000000>;
0663 reg-names = "regs", "addr_space";
0664 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
0665 interrupt-names = "pme";
0666 num-ib-windows = <6>;
0667 num-ob-windows = <8>;
0668 status = "disabled";
0669 };
0670
0671 pcie2: pcie@3500000 {
0672 compatible = "fsl,ls1028a-pcie";
0673 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
0674 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
0675 reg-names = "regs", "config";
0676 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0677 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0678 interrupt-names = "pme", "aer";
0679 #address-cells = <3>;
0680 #size-cells = <2>;
0681 device_type = "pci";
0682 dma-coherent;
0683 num-viewport = <8>;
0684 bus-range = <0x0 0xff>;
0685 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0686 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0687 msi-parent = <&its>;
0688 #interrupt-cells = <1>;
0689 interrupt-map-mask = <0 0 0 7>;
0690 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0691 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0692 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0693 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0694 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0695 status = "disabled";
0696 };
0697
0698 pcie_ep2: pcie-ep@3500000 {
0699 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
0700 reg = <0x00 0x03500000 0x0 0x00100000
0701 0x88 0x00000000 0x8 0x00000000>;
0702 reg-names = "regs", "addr_space";
0703 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
0704 interrupt-names = "pme";
0705 num-ib-windows = <6>;
0706 num-ob-windows = <8>;
0707 status = "disabled";
0708 };
0709
0710 smmu: iommu@5000000 {
0711 compatible = "arm,mmu-500";
0712 reg = <0 0x5000000 0 0x800000>;
0713 #global-interrupts = <8>;
0714 #iommu-cells = <1>;
0715 stream-match-mask = <0x7c00>;
0716 /* global secure fault */
0717 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0718 /* combined secure interrupt */
0719 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0720 /* global non-secure fault */
0721 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0722 /* combined non-secure interrupt */
0723 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0724 /* performance counter interrupts 0-7 */
0725 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0726 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
0727 /* per context interrupt, 64 interrupts */
0728 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0729 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0730 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0731 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0732 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
0735 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0736 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0737 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0738 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0739 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0741 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
0742 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
0743 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
0744 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
0745 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
0746 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
0747 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0748 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
0749 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0750 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
0751 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
0752 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
0753 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0754 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0755 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0756 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0757 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0758 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0759 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0760 };
0761
0762 crypto: crypto@8000000 {
0763 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
0764 fsl,sec-era = <10>;
0765 #address-cells = <1>;
0766 #size-cells = <1>;
0767 ranges = <0x0 0x00 0x8000000 0x100000>;
0768 reg = <0x00 0x8000000 0x0 0x100000>;
0769 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0770 dma-coherent;
0771
0772 sec_jr0: jr@10000 {
0773 compatible = "fsl,sec-v5.0-job-ring",
0774 "fsl,sec-v4.0-job-ring";
0775 reg = <0x10000 0x10000>;
0776 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0777 };
0778
0779 sec_jr1: jr@20000 {
0780 compatible = "fsl,sec-v5.0-job-ring",
0781 "fsl,sec-v4.0-job-ring";
0782 reg = <0x20000 0x10000>;
0783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0784 };
0785
0786 sec_jr2: jr@30000 {
0787 compatible = "fsl,sec-v5.0-job-ring",
0788 "fsl,sec-v4.0-job-ring";
0789 reg = <0x30000 0x10000>;
0790 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0791 };
0792
0793 sec_jr3: jr@40000 {
0794 compatible = "fsl,sec-v5.0-job-ring",
0795 "fsl,sec-v4.0-job-ring";
0796 reg = <0x40000 0x10000>;
0797 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0798 };
0799 };
0800
0801 qdma: dma-controller@8380000 {
0802 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
0803 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
0804 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
0805 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
0806 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0807 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
0808 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
0809 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
0810 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
0811 interrupt-names = "qdma-error", "qdma-queue0",
0812 "qdma-queue1", "qdma-queue2", "qdma-queue3";
0813 dma-channels = <8>;
0814 block-number = <1>;
0815 block-offset = <0x10000>;
0816 fsl,dma-queues = <2>;
0817 status-sizes = <64>;
0818 queue-sizes = <64 64>;
0819 };
0820
0821 cluster1_core0_watchdog: watchdog@c000000 {
0822 compatible = "arm,sp805", "arm,primecell";
0823 reg = <0x0 0xc000000 0x0 0x1000>;
0824 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0825 QORIQ_CLK_PLL_DIV(16)>,
0826 <&clockgen QORIQ_CLK_PLATFORM_PLL
0827 QORIQ_CLK_PLL_DIV(16)>;
0828 clock-names = "wdog_clk", "apb_pclk";
0829 };
0830
0831 cluster1_core1_watchdog: watchdog@c010000 {
0832 compatible = "arm,sp805", "arm,primecell";
0833 reg = <0x0 0xc010000 0x0 0x1000>;
0834 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0835 QORIQ_CLK_PLL_DIV(16)>,
0836 <&clockgen QORIQ_CLK_PLATFORM_PLL
0837 QORIQ_CLK_PLL_DIV(16)>;
0838 clock-names = "wdog_clk", "apb_pclk";
0839 };
0840
0841 malidp0: display@f080000 {
0842 compatible = "arm,mali-dp500";
0843 reg = <0x0 0xf080000 0x0 0x10000>;
0844 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
0845 <0 223 IRQ_TYPE_LEVEL_HIGH>;
0846 interrupt-names = "DE", "SE";
0847 clocks = <&dpclk>,
0848 <&clockgen QORIQ_CLK_HWACCEL 2>,
0849 <&clockgen QORIQ_CLK_HWACCEL 2>,
0850 <&clockgen QORIQ_CLK_HWACCEL 2>;
0851 clock-names = "pxlclk", "mclk", "aclk", "pclk";
0852 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
0853 arm,malidp-arqos-value = <0xd000d000>;
0854
0855 port {
0856 dpi0_out: endpoint {
0857
0858 };
0859 };
0860 };
0861
0862 gpu: gpu@f0c0000 {
0863 compatible = "vivante,gc";
0864 reg = <0x0 0xf0c0000 0x0 0x10000>;
0865 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
0866 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
0867 <&clockgen QORIQ_CLK_HWACCEL 2>,
0868 <&clockgen QORIQ_CLK_HWACCEL 2>;
0869 clock-names = "core", "shader", "bus";
0870 #cooling-cells = <2>;
0871 };
0872
0873 sai1: audio-controller@f100000 {
0874 #sound-dai-cells = <0>;
0875 compatible = "fsl,vf610-sai";
0876 reg = <0x0 0xf100000 0x0 0x10000>;
0877 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0878 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0879 QORIQ_CLK_PLL_DIV(2)>,
0880 <&clockgen QORIQ_CLK_PLATFORM_PLL
0881 QORIQ_CLK_PLL_DIV(2)>,
0882 <&clockgen QORIQ_CLK_PLATFORM_PLL
0883 QORIQ_CLK_PLL_DIV(2)>,
0884 <&clockgen QORIQ_CLK_PLATFORM_PLL
0885 QORIQ_CLK_PLL_DIV(2)>;
0886 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0887 dma-names = "tx", "rx";
0888 dmas = <&edma0 1 4>,
0889 <&edma0 1 3>;
0890 fsl,sai-asynchronous;
0891 status = "disabled";
0892 };
0893
0894 sai2: audio-controller@f110000 {
0895 #sound-dai-cells = <0>;
0896 compatible = "fsl,vf610-sai";
0897 reg = <0x0 0xf110000 0x0 0x10000>;
0898 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0899 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0900 QORIQ_CLK_PLL_DIV(2)>,
0901 <&clockgen QORIQ_CLK_PLATFORM_PLL
0902 QORIQ_CLK_PLL_DIV(2)>,
0903 <&clockgen QORIQ_CLK_PLATFORM_PLL
0904 QORIQ_CLK_PLL_DIV(2)>,
0905 <&clockgen QORIQ_CLK_PLATFORM_PLL
0906 QORIQ_CLK_PLL_DIV(2)>;
0907 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0908 dma-names = "tx", "rx";
0909 dmas = <&edma0 1 6>,
0910 <&edma0 1 5>;
0911 fsl,sai-asynchronous;
0912 status = "disabled";
0913 };
0914
0915 sai3: audio-controller@f120000 {
0916 #sound-dai-cells = <0>;
0917 compatible = "fsl,vf610-sai";
0918 reg = <0x0 0xf120000 0x0 0x10000>;
0919 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0920 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0921 QORIQ_CLK_PLL_DIV(2)>,
0922 <&clockgen QORIQ_CLK_PLATFORM_PLL
0923 QORIQ_CLK_PLL_DIV(2)>,
0924 <&clockgen QORIQ_CLK_PLATFORM_PLL
0925 QORIQ_CLK_PLL_DIV(2)>,
0926 <&clockgen QORIQ_CLK_PLATFORM_PLL
0927 QORIQ_CLK_PLL_DIV(2)>;
0928 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0929 dma-names = "tx", "rx";
0930 dmas = <&edma0 1 8>,
0931 <&edma0 1 7>;
0932 fsl,sai-asynchronous;
0933 status = "disabled";
0934 };
0935
0936 sai4: audio-controller@f130000 {
0937 #sound-dai-cells = <0>;
0938 compatible = "fsl,vf610-sai";
0939 reg = <0x0 0xf130000 0x0 0x10000>;
0940 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0941 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0942 QORIQ_CLK_PLL_DIV(2)>,
0943 <&clockgen QORIQ_CLK_PLATFORM_PLL
0944 QORIQ_CLK_PLL_DIV(2)>,
0945 <&clockgen QORIQ_CLK_PLATFORM_PLL
0946 QORIQ_CLK_PLL_DIV(2)>,
0947 <&clockgen QORIQ_CLK_PLATFORM_PLL
0948 QORIQ_CLK_PLL_DIV(2)>;
0949 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0950 dma-names = "tx", "rx";
0951 dmas = <&edma0 1 10>,
0952 <&edma0 1 9>;
0953 fsl,sai-asynchronous;
0954 status = "disabled";
0955 };
0956
0957 sai5: audio-controller@f140000 {
0958 #sound-dai-cells = <0>;
0959 compatible = "fsl,vf610-sai";
0960 reg = <0x0 0xf140000 0x0 0x10000>;
0961 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0962 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0963 QORIQ_CLK_PLL_DIV(2)>,
0964 <&clockgen QORIQ_CLK_PLATFORM_PLL
0965 QORIQ_CLK_PLL_DIV(2)>,
0966 <&clockgen QORIQ_CLK_PLATFORM_PLL
0967 QORIQ_CLK_PLL_DIV(2)>,
0968 <&clockgen QORIQ_CLK_PLATFORM_PLL
0969 QORIQ_CLK_PLL_DIV(2)>;
0970 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0971 dma-names = "tx", "rx";
0972 dmas = <&edma0 1 12>,
0973 <&edma0 1 11>;
0974 fsl,sai-asynchronous;
0975 status = "disabled";
0976 };
0977
0978 sai6: audio-controller@f150000 {
0979 #sound-dai-cells = <0>;
0980 compatible = "fsl,vf610-sai";
0981 reg = <0x0 0xf150000 0x0 0x10000>;
0982 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0983 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0984 QORIQ_CLK_PLL_DIV(2)>,
0985 <&clockgen QORIQ_CLK_PLATFORM_PLL
0986 QORIQ_CLK_PLL_DIV(2)>,
0987 <&clockgen QORIQ_CLK_PLATFORM_PLL
0988 QORIQ_CLK_PLL_DIV(2)>,
0989 <&clockgen QORIQ_CLK_PLATFORM_PLL
0990 QORIQ_CLK_PLL_DIV(2)>;
0991 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0992 dma-names = "tx", "rx";
0993 dmas = <&edma0 1 14>,
0994 <&edma0 1 13>;
0995 fsl,sai-asynchronous;
0996 status = "disabled";
0997 };
0998
0999 dpclk: clock-controller@f1f0000 {
1000 compatible = "fsl,ls1028a-plldig";
1001 reg = <0x0 0xf1f0000 0x0 0x10000>;
1002 #clock-cells = <0>;
1003 clocks = <&osc_27m>;
1004 };
1005
1006 tmu: tmu@1f80000 {
1007 compatible = "fsl,qoriq-tmu";
1008 reg = <0x0 0x1f80000 0x0 0x10000>;
1009 interrupts = <0 23 0x4>;
1010 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
1011 fsl,tmu-calibration = <0x00000000 0x00000024
1012 0x00000001 0x0000002b
1013 0x00000002 0x00000031
1014 0x00000003 0x00000038
1015 0x00000004 0x0000003f
1016 0x00000005 0x00000045
1017 0x00000006 0x0000004c
1018 0x00000007 0x00000053
1019 0x00000008 0x00000059
1020 0x00000009 0x00000060
1021 0x0000000a 0x00000066
1022 0x0000000b 0x0000006d
1023
1024 0x00010000 0x0000001c
1025 0x00010001 0x00000024
1026 0x00010002 0x0000002c
1027 0x00010003 0x00000035
1028 0x00010004 0x0000003d
1029 0x00010005 0x00000045
1030 0x00010006 0x0000004d
1031 0x00010007 0x00000055
1032 0x00010008 0x0000005e
1033 0x00010009 0x00000066
1034 0x0001000a 0x0000006e
1035
1036 0x00020000 0x00000018
1037 0x00020001 0x00000022
1038 0x00020002 0x0000002d
1039 0x00020003 0x00000038
1040 0x00020004 0x00000043
1041 0x00020005 0x0000004d
1042 0x00020006 0x00000058
1043 0x00020007 0x00000063
1044 0x00020008 0x0000006e
1045
1046 0x00030000 0x00000010
1047 0x00030001 0x0000001c
1048 0x00030002 0x00000029
1049 0x00030003 0x00000036
1050 0x00030004 0x00000042
1051 0x00030005 0x0000004f
1052 0x00030006 0x0000005b
1053 0x00030007 0x00000068>;
1054 little-endian;
1055 #thermal-sensor-cells = <1>;
1056 };
1057
1058 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
1059 compatible = "pci-host-ecam-generic";
1060 reg = <0x01 0xf0000000 0x0 0x100000>;
1061 #address-cells = <3>;
1062 #size-cells = <2>;
1063 msi-parent = <&its>;
1064 device_type = "pci";
1065 bus-range = <0x0 0x0>;
1066 dma-coherent;
1067 msi-map = <0 &its 0x17 0xe>;
1068 iommu-map = <0 &smmu 0x17 0xe>;
1069 /* PF0-6 BAR0 - non-prefetchable memory */
1070 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
1071 /* PF0-6 BAR2 - prefetchable memory */
1072 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
1073 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
1074 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
1075 /* PF0: VF0-1 BAR2 - prefetchable memory */
1076 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
1077 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
1078 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
1079 /* PF1: VF0-1 BAR2 - prefetchable memory */
1080 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
1081 /* BAR4 (PF5) - non-prefetchable memory */
1082 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
1083
1084 enetc_port0: ethernet@0,0 {
1085 compatible = "fsl,enetc";
1086 reg = <0x000000 0 0 0 0>;
1087 status = "disabled";
1088 };
1089
1090 enetc_port1: ethernet@0,1 {
1091 compatible = "fsl,enetc";
1092 reg = <0x000100 0 0 0 0>;
1093 status = "disabled";
1094 };
1095
1096 enetc_port2: ethernet@0,2 {
1097 compatible = "fsl,enetc";
1098 reg = <0x000200 0 0 0 0>;
1099 phy-mode = "internal";
1100 status = "disabled";
1101
1102 fixed-link {
1103 speed = <2500>;
1104 full-duplex;
1105 pause;
1106 };
1107 };
1108
1109 enetc_mdio_pf3: mdio@0,3 {
1110 compatible = "fsl,enetc-mdio";
1111 reg = <0x000300 0 0 0 0>;
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114 };
1115
1116 ethernet@0,4 {
1117 compatible = "fsl,enetc-ptp";
1118 reg = <0x000400 0 0 0 0>;
1119 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
1120 little-endian;
1121 fsl,extts-fifo;
1122 };
1123
1124 mscc_felix: ethernet-switch@0,5 {
1125 reg = <0x000500 0 0 0 0>;
1126 /* IEP INT_B */
1127 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1128 status = "disabled";
1129
1130 mscc_felix_ports: ports {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133
1134 /* External ports */
1135 mscc_felix_port0: port@0 {
1136 reg = <0>;
1137 status = "disabled";
1138 };
1139
1140 mscc_felix_port1: port@1 {
1141 reg = <1>;
1142 status = "disabled";
1143 };
1144
1145 mscc_felix_port2: port@2 {
1146 reg = <2>;
1147 status = "disabled";
1148 };
1149
1150 mscc_felix_port3: port@3 {
1151 reg = <3>;
1152 status = "disabled";
1153 };
1154
1155 /* Internal ports */
1156 mscc_felix_port4: port@4 {
1157 reg = <4>;
1158 phy-mode = "internal";
1159 status = "disabled";
1160
1161 fixed-link {
1162 speed = <2500>;
1163 full-duplex;
1164 pause;
1165 };
1166 };
1167
1168 mscc_felix_port5: port@5 {
1169 reg = <5>;
1170 phy-mode = "internal";
1171 status = "disabled";
1172
1173 fixed-link {
1174 speed = <1000>;
1175 full-duplex;
1176 pause;
1177 };
1178 };
1179 };
1180 };
1181
1182 enetc_port3: ethernet@0,6 {
1183 compatible = "fsl,enetc";
1184 reg = <0x000600 0 0 0 0>;
1185 phy-mode = "internal";
1186 status = "disabled";
1187
1188 fixed-link {
1189 speed = <1000>;
1190 full-duplex;
1191 pause;
1192 };
1193 };
1194
1195 rcec@1f,0 {
1196 reg = <0x00f800 0 0 0 0>;
1197 /* IEP INT_A */
1198 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1199 };
1200 };
1201
1202 /* Integrated Endpoint Register Block */
1203 ierb@1f0800000 {
1204 compatible = "fsl,ls1028a-enetc-ierb";
1205 reg = <0x01 0xf0800000 0x0 0x10000>;
1206 };
1207
1208 pwm0: pwm@2800000 {
1209 compatible = "fsl,vf610-ftm-pwm";
1210 #pwm-cells = <3>;
1211 reg = <0x0 0x2800000 0x0 0x10000>;
1212 clock-names = "ftm_sys", "ftm_ext",
1213 "ftm_fix", "ftm_cnt_clk_en";
1214 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1215 <&rtc_clk>, <&clockgen 4 1>;
1216 status = "disabled";
1217 };
1218
1219 pwm1: pwm@2810000 {
1220 compatible = "fsl,vf610-ftm-pwm";
1221 #pwm-cells = <3>;
1222 reg = <0x0 0x2810000 0x0 0x10000>;
1223 clock-names = "ftm_sys", "ftm_ext",
1224 "ftm_fix", "ftm_cnt_clk_en";
1225 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1226 <&rtc_clk>, <&clockgen 4 1>;
1227 status = "disabled";
1228 };
1229
1230 pwm2: pwm@2820000 {
1231 compatible = "fsl,vf610-ftm-pwm";
1232 #pwm-cells = <3>;
1233 reg = <0x0 0x2820000 0x0 0x10000>;
1234 clock-names = "ftm_sys", "ftm_ext",
1235 "ftm_fix", "ftm_cnt_clk_en";
1236 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1237 <&rtc_clk>, <&clockgen 4 1>;
1238 status = "disabled";
1239 };
1240
1241 pwm3: pwm@2830000 {
1242 compatible = "fsl,vf610-ftm-pwm";
1243 #pwm-cells = <3>;
1244 reg = <0x0 0x2830000 0x0 0x10000>;
1245 clock-names = "ftm_sys", "ftm_ext",
1246 "ftm_fix", "ftm_cnt_clk_en";
1247 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1248 <&rtc_clk>, <&clockgen 4 1>;
1249 status = "disabled";
1250 };
1251
1252 pwm4: pwm@2840000 {
1253 compatible = "fsl,vf610-ftm-pwm";
1254 #pwm-cells = <3>;
1255 reg = <0x0 0x2840000 0x0 0x10000>;
1256 clock-names = "ftm_sys", "ftm_ext",
1257 "ftm_fix", "ftm_cnt_clk_en";
1258 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1259 <&rtc_clk>, <&clockgen 4 1>;
1260 status = "disabled";
1261 };
1262
1263 pwm5: pwm@2850000 {
1264 compatible = "fsl,vf610-ftm-pwm";
1265 #pwm-cells = <3>;
1266 reg = <0x0 0x2850000 0x0 0x10000>;
1267 clock-names = "ftm_sys", "ftm_ext",
1268 "ftm_fix", "ftm_cnt_clk_en";
1269 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1270 <&rtc_clk>, <&clockgen 4 1>;
1271 status = "disabled";
1272 };
1273
1274 pwm6: pwm@2860000 {
1275 compatible = "fsl,vf610-ftm-pwm";
1276 #pwm-cells = <3>;
1277 reg = <0x0 0x2860000 0x0 0x10000>;
1278 clock-names = "ftm_sys", "ftm_ext",
1279 "ftm_fix", "ftm_cnt_clk_en";
1280 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1281 <&rtc_clk>, <&clockgen 4 1>;
1282 status = "disabled";
1283 };
1284
1285 pwm7: pwm@2870000 {
1286 compatible = "fsl,vf610-ftm-pwm";
1287 #pwm-cells = <3>;
1288 reg = <0x0 0x2870000 0x0 0x10000>;
1289 clock-names = "ftm_sys", "ftm_ext",
1290 "ftm_fix", "ftm_cnt_clk_en";
1291 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1292 <&rtc_clk>, <&clockgen 4 1>;
1293 status = "disabled";
1294 };
1295
1296 rcpm: power-controller@1e34040 {
1297 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
1298 reg = <0x0 0x1e34040 0x0 0x1c>;
1299 #fsl,rcpm-wakeup-cells = <7>;
1300 little-endian;
1301 };
1302
1303 ftm_alarm0: timer@2800000 {
1304 compatible = "fsl,ls1028a-ftm-alarm";
1305 reg = <0x0 0x2800000 0x0 0x10000>;
1306 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1307 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1308 status = "disabled";
1309 };
1310
1311 ftm_alarm1: timer@2810000 {
1312 compatible = "fsl,ls1028a-ftm-alarm";
1313 reg = <0x0 0x2810000 0x0 0x10000>;
1314 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1315 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1316 status = "disabled";
1317 };
1318 };
1319
1320 };
