0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree fragment for LS1028A QDS board, serdes 7777
0004 *
0005 * Copyright 2019-2021 NXP
0006 *
0007 * Requires a LS1028A QDS board without lane B rework.
0008 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
0009 * disabled, plugged in slot 1.
0010 */
0011
0012 /dts-v1/;
0013 /plugin/;
0014
0015 &mdio_slot1 {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 /* 4 ports on AQR412 */
0020 slot1_sxgmii0: ethernet-phy@0 {
0021 reg = <0x0>;
0022 compatible = "ethernet-phy-ieee802.3-c45";
0023 };
0024
0025 slot1_sxgmii1: ethernet-phy@1 {
0026 reg = <0x1>;
0027 compatible = "ethernet-phy-ieee802.3-c45";
0028 };
0029
0030 slot1_sxgmii2: ethernet-phy@2 {
0031 reg = <0x2>;
0032 compatible = "ethernet-phy-ieee802.3-c45";
0033 };
0034
0035 slot1_sxgmii3: ethernet-phy@3 {
0036 reg = <0x3>;
0037 compatible = "ethernet-phy-ieee802.3-c45";
0038 };
0039 };
0040
0041 &mscc_felix_ports {
0042 port@0 {
0043 status = "okay";
0044 phy-handle = <&slot1_sxgmii0>;
0045 phy-mode = "2500base-x";
0046 };
0047
0048 port@1 {
0049 status = "okay";
0050 phy-handle = <&slot1_sxgmii1>;
0051 phy-mode = "2500base-x";
0052 };
0053
0054 port@2 {
0055 status = "okay";
0056 phy-handle = <&slot1_sxgmii2>;
0057 phy-mode = "2500base-x";
0058 };
0059
0060 port@3 {
0061 status = "okay";
0062 phy-handle = <&slot1_sxgmii3>;
0063 phy-mode = "2500base-x";
0064 };
0065 };
0066
0067 &mscc_felix {
0068 status = "okay";
0069 };
