0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree fragment for LS1028A QDS board, serdes 13bb
0004 *
0005 * Copyright 2019-2021 NXP
0006 *
0007 * Requires a LS1028A QDS board with lane B rework.
0008 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
0009 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
0010 */
0011
0012 /dts-v1/;
0013 /plugin/;
0014
0015 &mdio_slot1 {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 slot1_sgmii: ethernet-phy@2 {
0020 /* AQR112 */
0021 reg = <0x2>;
0022 compatible = "ethernet-phy-ieee802.3-c45";
0023 };
0024 };
0025
0026 &enetc_port0 {
0027 phy-handle = <&slot1_sgmii>;
0028 phy-mode = "usxgmii";
0029 managed = "in-band-status";
0030 status = "okay";
0031 };
0032
0033 &mdio_slot2 {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036
0037 /* 4 ports on AQR412 */
0038 slot2_qxgmii0: ethernet-phy@0 {
0039 reg = <0x0>;
0040 compatible = "ethernet-phy-ieee802.3-c45";
0041 };
0042
0043 slot2_qxgmii1: ethernet-phy@1 {
0044 reg = <0x1>;
0045 compatible = "ethernet-phy-ieee802.3-c45";
0046 };
0047
0048 slot2_qxgmii2: ethernet-phy@2 {
0049 reg = <0x2>;
0050 compatible = "ethernet-phy-ieee802.3-c45";
0051 };
0052
0053 slot2_qxgmii3: ethernet-phy@3 {
0054 reg = <0x3>;
0055 compatible = "ethernet-phy-ieee802.3-c45";
0056 };
0057 };
0058
0059 &mscc_felix_ports {
0060 port@0 {
0061 status = "okay";
0062 phy-handle = <&slot2_qxgmii0>;
0063 phy-mode = "usxgmii";
0064 managed = "in-band-status";
0065 };
0066
0067 port@1 {
0068 status = "okay";
0069 phy-handle = <&slot2_qxgmii1>;
0070 phy-mode = "usxgmii";
0071 managed = "in-band-status";
0072 };
0073
0074 port@2 {
0075 status = "okay";
0076 phy-handle = <&slot2_qxgmii2>;
0077 phy-mode = "usxgmii";
0078 managed = "in-band-status";
0079 };
0080
0081 port@3 {
0082 status = "okay";
0083 phy-handle = <&slot2_qxgmii3>;
0084 phy-mode = "usxgmii";
0085 managed = "in-band-status";
0086 };
0087 };
0088
0089 &mscc_felix {
0090 status = "okay";
0091 };
