0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for NXP Layerscape-1012A family SoC.
0004 *
0005 * Copyright 2016 Freescale Semiconductor, Inc.
0006 * Copyright 2019-2020 NXP
0007 *
0008 */
0009
0010 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013
0014 / {
0015 compatible = "fsl,ls1012a";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 crypto = &crypto;
0022 rtc1 = &ftm_alarm0;
0023 rtic-a = &rtic_a;
0024 rtic-b = &rtic_b;
0025 rtic-c = &rtic_c;
0026 rtic-d = &rtic_d;
0027 sec-mon = &sec_mon;
0028 };
0029
0030 cpus {
0031 #address-cells = <1>;
0032 #size-cells = <0>;
0033
0034 cpu0: cpu@0 {
0035 device_type = "cpu";
0036 compatible = "arm,cortex-a53";
0037 reg = <0x0>;
0038 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0039 #cooling-cells = <2>;
0040 cpu-idle-states = <&CPU_PH20>;
0041 };
0042 };
0043
0044 idle-states {
0045 /*
0046 * PSCI node is not added default, U-boot will add missing
0047 * parts if it determines to use PSCI.
0048 */
0049 entry-method = "psci";
0050
0051 CPU_PH20: cpu-ph20 {
0052 compatible = "arm,idle-state";
0053 idle-state-name = "PH20";
0054 arm,psci-suspend-param = <0x0>;
0055 entry-latency-us = <1000>;
0056 exit-latency-us = <1000>;
0057 min-residency-us = <3000>;
0058 };
0059 };
0060
0061 sysclk: sysclk {
0062 compatible = "fixed-clock";
0063 #clock-cells = <0>;
0064 clock-frequency = <125000000>;
0065 clock-output-names = "sysclk";
0066 };
0067
0068 coreclk: coreclk {
0069 compatible = "fixed-clock";
0070 #clock-cells = <0>;
0071 clock-frequency = <100000000>;
0072 clock-output-names = "coreclk";
0073 };
0074
0075 timer {
0076 compatible = "arm,armv8-timer";
0077 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
0078 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
0079 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
0080 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
0081 };
0082
0083 pmu {
0084 compatible = "arm,armv8-pmuv3";
0085 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
0086 };
0087
0088 gic: interrupt-controller@1400000 {
0089 compatible = "arm,gic-400";
0090 #interrupt-cells = <3>;
0091 interrupt-controller;
0092 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
0093 <0x0 0x1402000 0 0x2000>, /* GICC */
0094 <0x0 0x1404000 0 0x2000>, /* GICH */
0095 <0x0 0x1406000 0 0x2000>; /* GICV */
0096 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
0097 };
0098
0099 reboot {
0100 compatible = "syscon-reboot";
0101 regmap = <&dcfg>;
0102 offset = <0xb0>;
0103 mask = <0x02>;
0104 };
0105
0106 thermal-zones {
0107 cpu_thermal: cpu-thermal {
0108 polling-delay-passive = <1000>;
0109 polling-delay = <5000>;
0110 thermal-sensors = <&tmu 0>;
0111
0112 trips {
0113 cpu_alert: cpu-alert {
0114 temperature = <85000>;
0115 hysteresis = <2000>;
0116 type = "passive";
0117 };
0118
0119 cpu_crit: cpu-crit {
0120 temperature = <95000>;
0121 hysteresis = <2000>;
0122 type = "critical";
0123 };
0124 };
0125
0126 cooling-maps {
0127 map0 {
0128 trip = <&cpu_alert>;
0129 cooling-device =
0130 <&cpu0 THERMAL_NO_LIMIT
0131 THERMAL_NO_LIMIT>;
0132 };
0133 };
0134 };
0135 };
0136
0137 soc {
0138 compatible = "simple-bus";
0139 #address-cells = <2>;
0140 #size-cells = <2>;
0141 ranges;
0142
0143 qspi: spi@1550000 {
0144 compatible = "fsl,ls1021a-qspi";
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 reg = <0x0 0x1550000 0x0 0x10000>,
0148 <0x0 0x40000000 0x0 0x10000000>;
0149 reg-names = "QuadSPI", "QuadSPI-memory";
0150 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0151 clock-names = "qspi_en", "qspi";
0152 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0153 QORIQ_CLK_PLL_DIV(1)>,
0154 <&clockgen QORIQ_CLK_PLATFORM_PLL
0155 QORIQ_CLK_PLL_DIV(1)>;
0156 status = "disabled";
0157 };
0158
0159 esdhc0: esdhc@1560000 {
0160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
0161 reg = <0x0 0x1560000 0x0 0x10000>;
0162 interrupts = <0 62 0x4>;
0163 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0164 QORIQ_CLK_PLL_DIV(1)>;
0165 voltage-ranges = <1800 1800 3300 3300>;
0166 sdhci,auto-cmd12;
0167 big-endian;
0168 bus-width = <4>;
0169 status = "disabled";
0170 };
0171
0172 scfg: scfg@1570000 {
0173 compatible = "fsl,ls1012a-scfg", "syscon";
0174 reg = <0x0 0x1570000 0x0 0x10000>;
0175 big-endian;
0176 };
0177
0178 esdhc1: esdhc@1580000 {
0179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
0180 reg = <0x0 0x1580000 0x0 0x10000>;
0181 interrupts = <0 65 0x4>;
0182 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0183 QORIQ_CLK_PLL_DIV(1)>;
0184 voltage-ranges = <1800 1800 3300 3300>;
0185 sdhci,auto-cmd12;
0186 big-endian;
0187 broken-cd;
0188 bus-width = <4>;
0189 status = "disabled";
0190 };
0191
0192 crypto: crypto@1700000 {
0193 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
0194 "fsl,sec-v4.0";
0195 fsl,sec-era = <8>;
0196 #address-cells = <1>;
0197 #size-cells = <1>;
0198 ranges = <0x0 0x00 0x1700000 0x100000>;
0199 reg = <0x00 0x1700000 0x0 0x100000>;
0200 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0201 dma-coherent;
0202
0203 sec_jr0: jr@10000 {
0204 compatible = "fsl,sec-v5.4-job-ring",
0205 "fsl,sec-v5.0-job-ring",
0206 "fsl,sec-v4.0-job-ring";
0207 reg = <0x10000 0x10000>;
0208 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0209 };
0210
0211 sec_jr1: jr@20000 {
0212 compatible = "fsl,sec-v5.4-job-ring",
0213 "fsl,sec-v5.0-job-ring",
0214 "fsl,sec-v4.0-job-ring";
0215 reg = <0x20000 0x10000>;
0216 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0217 };
0218
0219 sec_jr2: jr@30000 {
0220 compatible = "fsl,sec-v5.4-job-ring",
0221 "fsl,sec-v5.0-job-ring",
0222 "fsl,sec-v4.0-job-ring";
0223 reg = <0x30000 0x10000>;
0224 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0225 };
0226
0227 sec_jr3: jr@40000 {
0228 compatible = "fsl,sec-v5.4-job-ring",
0229 "fsl,sec-v5.0-job-ring",
0230 "fsl,sec-v4.0-job-ring";
0231 reg = <0x40000 0x10000>;
0232 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0233 };
0234
0235 rtic@60000 {
0236 compatible = "fsl,sec-v5.4-rtic",
0237 "fsl,sec-v5.0-rtic",
0238 "fsl,sec-v4.0-rtic";
0239 #address-cells = <1>;
0240 #size-cells = <1>;
0241 reg = <0x60000 0x100>, <0x60e00 0x18>;
0242 ranges = <0x0 0x60100 0x500>;
0243
0244 rtic_a: rtic-a@0 {
0245 compatible = "fsl,sec-v5.4-rtic-memory",
0246 "fsl,sec-v5.0-rtic-memory",
0247 "fsl,sec-v4.0-rtic-memory";
0248 reg = <0x00 0x20>, <0x100 0x100>;
0249 };
0250
0251 rtic_b: rtic-b@20 {
0252 compatible = "fsl,sec-v5.4-rtic-memory",
0253 "fsl,sec-v5.0-rtic-memory",
0254 "fsl,sec-v4.0-rtic-memory";
0255 reg = <0x20 0x20>, <0x200 0x100>;
0256 };
0257
0258 rtic_c: rtic-c@40 {
0259 compatible = "fsl,sec-v5.4-rtic-memory",
0260 "fsl,sec-v5.0-rtic-memory",
0261 "fsl,sec-v4.0-rtic-memory";
0262 reg = <0x40 0x20>, <0x300 0x100>;
0263 };
0264
0265 rtic_d: rtic-d@60 {
0266 compatible = "fsl,sec-v5.4-rtic-memory",
0267 "fsl,sec-v5.0-rtic-memory",
0268 "fsl,sec-v4.0-rtic-memory";
0269 reg = <0x60 0x20>, <0x400 0x100>;
0270 };
0271 };
0272 };
0273
0274 sfp: efuse@1e80000 {
0275 compatible = "fsl,ls1021a-sfp";
0276 reg = <0x0 0x1e80000 0x0 0x10000>;
0277 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0278 QORIQ_CLK_PLL_DIV(4)>;
0279 clock-names = "sfp";
0280 };
0281
0282 sec_mon: sec_mon@1e90000 {
0283 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
0284 "fsl,sec-v4.0-mon";
0285 reg = <0x0 0x1e90000 0x0 0x10000>;
0286 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0287 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0288 };
0289
0290 dcfg: dcfg@1ee0000 {
0291 compatible = "fsl,ls1012a-dcfg",
0292 "syscon";
0293 reg = <0x0 0x1ee0000 0x0 0x10000>;
0294 big-endian;
0295 };
0296
0297 clockgen: clocking@1ee1000 {
0298 compatible = "fsl,ls1012a-clockgen";
0299 reg = <0x0 0x1ee1000 0x0 0x1000>;
0300 #clock-cells = <2>;
0301 clocks = <&sysclk &coreclk>;
0302 clock-names = "sysclk", "coreclk";
0303 };
0304
0305 tmu: tmu@1f00000 {
0306 compatible = "fsl,qoriq-tmu";
0307 reg = <0x0 0x1f00000 0x0 0x10000>;
0308 interrupts = <0 33 0x4>;
0309 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
0310 fsl,tmu-calibration = <0x00000000 0x00000025
0311 0x00000001 0x0000002c
0312 0x00000002 0x00000032
0313 0x00000003 0x00000039
0314 0x00000004 0x0000003f
0315 0x00000005 0x00000046
0316 0x00000006 0x0000004c
0317 0x00000007 0x00000053
0318 0x00000008 0x00000059
0319 0x00000009 0x0000005f
0320 0x0000000a 0x00000066
0321 0x0000000b 0x0000006c
0322
0323 0x00010000 0x00000026
0324 0x00010001 0x0000002d
0325 0x00010002 0x00000035
0326 0x00010003 0x0000003d
0327 0x00010004 0x00000045
0328 0x00010005 0x0000004d
0329 0x00010006 0x00000055
0330 0x00010007 0x0000005d
0331 0x00010008 0x00000065
0332 0x00010009 0x0000006d
0333
0334 0x00020000 0x00000026
0335 0x00020001 0x00000030
0336 0x00020002 0x0000003a
0337 0x00020003 0x00000044
0338 0x00020004 0x0000004e
0339 0x00020005 0x00000059
0340 0x00020006 0x00000063
0341
0342 0x00030000 0x00000014
0343 0x00030001 0x00000021
0344 0x00030002 0x0000002e
0345 0x00030003 0x0000003a
0346 0x00030004 0x00000047
0347 0x00030005 0x00000053
0348 0x00030006 0x00000060>;
0349 big-endian;
0350 #thermal-sensor-cells = <1>;
0351 };
0352
0353 i2c0: i2c@2180000 {
0354 compatible = "fsl,vf610-i2c";
0355 #address-cells = <1>;
0356 #size-cells = <0>;
0357 reg = <0x0 0x2180000 0x0 0x10000>;
0358 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
0359 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0360 QORIQ_CLK_PLL_DIV(4)>;
0361 status = "disabled";
0362 };
0363
0364 i2c1: i2c@2190000 {
0365 compatible = "fsl,vf610-i2c";
0366 #address-cells = <1>;
0367 #size-cells = <0>;
0368 reg = <0x0 0x2190000 0x0 0x10000>;
0369 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
0370 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0371 QORIQ_CLK_PLL_DIV(4)>;
0372 status = "disabled";
0373 };
0374
0375 dspi: spi@2100000 {
0376 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
0377 #address-cells = <1>;
0378 #size-cells = <0>;
0379 reg = <0x0 0x2100000 0x0 0x10000>;
0380 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
0381 clock-names = "dspi";
0382 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0383 QORIQ_CLK_PLL_DIV(1)>;
0384 spi-num-chipselects = <5>;
0385 big-endian;
0386 status = "disabled";
0387 };
0388
0389 duart0: serial@21c0500 {
0390 compatible = "fsl,ns16550", "ns16550a";
0391 reg = <0x00 0x21c0500 0x0 0x100>;
0392 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
0393 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0394 QORIQ_CLK_PLL_DIV(1)>;
0395 status = "disabled";
0396 };
0397
0398 duart1: serial@21c0600 {
0399 compatible = "fsl,ns16550", "ns16550a";
0400 reg = <0x00 0x21c0600 0x0 0x100>;
0401 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0403 QORIQ_CLK_PLL_DIV(1)>;
0404 status = "disabled";
0405 };
0406
0407 gpio0: gpio@2300000 {
0408 compatible = "fsl,qoriq-gpio";
0409 reg = <0x0 0x2300000 0x0 0x10000>;
0410 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
0411 gpio-controller;
0412 #gpio-cells = <2>;
0413 interrupt-controller;
0414 #interrupt-cells = <2>;
0415 };
0416
0417 gpio1: gpio@2310000 {
0418 compatible = "fsl,qoriq-gpio";
0419 reg = <0x0 0x2310000 0x0 0x10000>;
0420 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
0421 gpio-controller;
0422 #gpio-cells = <2>;
0423 interrupt-controller;
0424 #interrupt-cells = <2>;
0425 };
0426
0427 wdog0: watchdog@2ad0000 {
0428 compatible = "fsl,ls1012a-wdt",
0429 "fsl,imx21-wdt";
0430 reg = <0x0 0x2ad0000 0x0 0x10000>;
0431 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
0432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
0433 big-endian;
0434 };
0435
0436 sai1: sai@2b50000 {
0437 #sound-dai-cells = <0>;
0438 compatible = "fsl,vf610-sai";
0439 reg = <0x0 0x2b50000 0x0 0x10000>;
0440 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
0441 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0442 QORIQ_CLK_PLL_DIV(4)>,
0443 <&clockgen QORIQ_CLK_PLATFORM_PLL
0444 QORIQ_CLK_PLL_DIV(4)>,
0445 <&clockgen QORIQ_CLK_PLATFORM_PLL
0446 QORIQ_CLK_PLL_DIV(4)>,
0447 <&clockgen QORIQ_CLK_PLATFORM_PLL
0448 QORIQ_CLK_PLL_DIV(4)>;
0449 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0450 dma-names = "tx", "rx";
0451 dmas = <&edma0 1 47>,
0452 <&edma0 1 46>;
0453 status = "disabled";
0454 };
0455
0456 sai2: sai@2b60000 {
0457 #sound-dai-cells = <0>;
0458 compatible = "fsl,vf610-sai";
0459 reg = <0x0 0x2b60000 0x0 0x10000>;
0460 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
0461 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0462 QORIQ_CLK_PLL_DIV(4)>,
0463 <&clockgen QORIQ_CLK_PLATFORM_PLL
0464 QORIQ_CLK_PLL_DIV(4)>,
0465 <&clockgen QORIQ_CLK_PLATFORM_PLL
0466 QORIQ_CLK_PLL_DIV(4)>,
0467 <&clockgen QORIQ_CLK_PLATFORM_PLL
0468 QORIQ_CLK_PLL_DIV(4)>;
0469 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0470 dma-names = "tx", "rx";
0471 dmas = <&edma0 1 45>,
0472 <&edma0 1 44>;
0473 status = "disabled";
0474 };
0475
0476 edma0: dma-controller@2c00000 {
0477 #dma-cells = <2>;
0478 compatible = "fsl,vf610-edma";
0479 reg = <0x0 0x2c00000 0x0 0x10000>,
0480 <0x0 0x2c10000 0x0 0x10000>,
0481 <0x0 0x2c20000 0x0 0x10000>;
0482 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
0483 <0 103 IRQ_TYPE_LEVEL_HIGH>;
0484 interrupt-names = "edma-tx", "edma-err";
0485 dma-channels = <32>;
0486 big-endian;
0487 clock-names = "dmamux0", "dmamux1";
0488 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0489 QORIQ_CLK_PLL_DIV(4)>,
0490 <&clockgen QORIQ_CLK_PLATFORM_PLL
0491 QORIQ_CLK_PLL_DIV(4)>;
0492 };
0493
0494 usb0: usb@2f00000 {
0495 compatible = "snps,dwc3";
0496 reg = <0x0 0x2f00000 0x0 0x10000>;
0497 interrupts = <0 60 0x4>;
0498 dr_mode = "host";
0499 snps,quirk-frame-length-adjustment = <0x20>;
0500 snps,dis_rxdet_inp3_quirk;
0501 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0502 };
0503
0504 sata: sata@3200000 {
0505 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
0506 reg = <0x0 0x3200000 0x0 0x10000>,
0507 <0x0 0x20140520 0x0 0x4>;
0508 reg-names = "ahci", "sata-ecc";
0509 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
0510 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0511 QORIQ_CLK_PLL_DIV(1)>;
0512 dma-coherent;
0513 status = "disabled";
0514 };
0515
0516 usb1: usb@8600000 {
0517 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
0518 reg = <0x0 0x8600000 0x0 0x1000>;
0519 interrupts = <0 139 0x4>;
0520 dr_mode = "host";
0521 phy_type = "ulpi";
0522 };
0523
0524 msi: msi-controller1@1572000 {
0525 compatible = "fsl,ls1012a-msi";
0526 reg = <0x0 0x1572000 0x0 0x8>;
0527 msi-controller;
0528 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
0529 };
0530
0531 pcie1: pcie@3400000 {
0532 compatible = "fsl,ls1012a-pcie";
0533 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0534 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
0535 reg-names = "regs", "config";
0536 interrupts = <0 118 0x4>, /* controller interrupt */
0537 <0 117 0x4>; /* PME interrupt */
0538 interrupt-names = "aer", "pme";
0539 #address-cells = <3>;
0540 #size-cells = <2>;
0541 device_type = "pci";
0542 num-viewport = <2>;
0543 bus-range = <0x0 0xff>;
0544 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0545 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0546 msi-parent = <&msi>;
0547 #interrupt-cells = <1>;
0548 interrupt-map-mask = <0 0 0 7>;
0549 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
0550 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
0551 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
0552 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
0553 status = "disabled";
0554 };
0555
0556 rcpm: power-controller@1ee2140 {
0557 compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
0558 reg = <0x0 0x1ee2140 0x0 0x4>;
0559 #fsl,rcpm-wakeup-cells = <1>;
0560 };
0561
0562 ftm_alarm0: timer@29d0000 {
0563 compatible = "fsl,ls1012a-ftm-alarm";
0564 reg = <0x0 0x29d0000 0x0 0x10000>;
0565 fsl,rcpm-wakeup = <&rcpm 0x20000>;
0566 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0567 big-endian;
0568 };
0569 };
0570
0571 firmware {
0572 optee {
0573 compatible = "linaro,optee-tz";
0574 method = "smc";
0575 };
0576 };
0577 };
