0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's ExynosAuto v9 SoC device tree source
0004 *
0005 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
0006 *
0007 */
0008
0009 #include <dt-bindings/clock/samsung,exynosautov9.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/soc/samsung,boot-mode.h>
0012 #include <dt-bindings/soc/samsung,exynos-usi.h>
0013
0014 / {
0015 compatible = "samsung,exynosautov9";
0016 #address-cells = <2>;
0017 #size-cells = <1>;
0018
0019 interrupt-parent = <&gic>;
0020
0021 aliases {
0022 pinctrl0 = &pinctrl_alive;
0023 pinctrl1 = &pinctrl_aud;
0024 pinctrl2 = &pinctrl_fsys0;
0025 pinctrl3 = &pinctrl_fsys1;
0026 pinctrl4 = &pinctrl_fsys2;
0027 pinctrl5 = &pinctrl_peric0;
0028 pinctrl6 = &pinctrl_peric1;
0029 };
0030
0031 arm-pmu {
0032 compatible = "arm,cortex-a76-pmu";
0033 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0034 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0035 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0036 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0037 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0038 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0039 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0040 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0041 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
0042 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0043 };
0044
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 cpu-map {
0050 cluster0 {
0051 core0 {
0052 cpu = <&cpu0>;
0053 };
0054 core1 {
0055 cpu = <&cpu1>;
0056 };
0057 core2 {
0058 cpu = <&cpu2>;
0059 };
0060 core3 {
0061 cpu = <&cpu3>;
0062 };
0063 };
0064
0065 cluster1 {
0066 core0 {
0067 cpu = <&cpu4>;
0068 };
0069 core1 {
0070 cpu = <&cpu5>;
0071 };
0072 core2 {
0073 cpu = <&cpu6>;
0074 };
0075 core3 {
0076 cpu = <&cpu7>;
0077 };
0078 };
0079 };
0080
0081 cpu0: cpu@0 {
0082 device_type = "cpu";
0083 compatible = "arm,cortex-a76";
0084 reg = <0x0>;
0085 enable-method = "psci";
0086 };
0087
0088 cpu1: cpu@100 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a76";
0091 reg = <0x100>;
0092 enable-method = "psci";
0093 };
0094
0095 cpu2: cpu@200 {
0096 device_type = "cpu";
0097 compatible = "arm,cortex-a76";
0098 reg = <0x200>;
0099 enable-method = "psci";
0100 };
0101
0102 cpu3: cpu@300 {
0103 device_type = "cpu";
0104 compatible = "arm,cortex-a76";
0105 reg = <0x300>;
0106 enable-method = "psci";
0107 };
0108
0109 cpu4: cpu@10000 {
0110 device_type = "cpu";
0111 compatible = "arm,cortex-a76";
0112 reg = <0x10000>;
0113 enable-method = "psci";
0114 };
0115
0116 cpu5: cpu@10100 {
0117 device_type = "cpu";
0118 compatible = "arm,cortex-a76";
0119 reg = <0x10100>;
0120 enable-method = "psci";
0121 };
0122
0123 cpu6: cpu@10200 {
0124 device_type = "cpu";
0125 compatible = "arm,cortex-a76";
0126 reg = <0x10200>;
0127 enable-method = "psci";
0128 };
0129
0130 cpu7: cpu@10300 {
0131 device_type = "cpu";
0132 compatible = "arm,cortex-a76";
0133 reg = <0x10300>;
0134 enable-method = "psci";
0135 };
0136 };
0137
0138 psci {
0139 compatible = "arm,psci-1.0";
0140 method = "smc";
0141 cpu_suspend = <0xc4000001>;
0142 cpu_off = <0x84000002>;
0143 cpu_on = <0xc4000003>;
0144 };
0145
0146 timer {
0147 compatible = "arm,armv8-timer";
0148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0152 };
0153
0154 fixed-rate-clocks {
0155 xtcxo: clock {
0156 compatible = "fixed-clock";
0157 #clock-cells = <0>;
0158 clock-output-names = "oscclk";
0159 };
0160 };
0161
0162 soc: soc@0 {
0163 compatible = "simple-bus";
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166 ranges = <0x0 0x0 0x0 0x20000000>;
0167
0168 chipid@10000000 {
0169 compatible = "samsung,exynos850-chipid";
0170 reg = <0x10000000 0x24>;
0171 };
0172
0173 cmu_peris: clock-controller@10020000 {
0174 compatible = "samsung,exynosautov9-cmu-peris";
0175 reg = <0x10020000 0x8000>;
0176 #clock-cells = <1>;
0177
0178 clocks = <&xtcxo>,
0179 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
0180 clock-names = "oscclk",
0181 "dout_clkcmu_peris_bus";
0182 };
0183
0184 cmu_peric0: clock-controller@10200000 {
0185 compatible = "samsung,exynosautov9-cmu-peric0";
0186 reg = <0x10200000 0x8000>;
0187 #clock-cells = <1>;
0188
0189 clocks = <&xtcxo>,
0190 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
0191 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
0192 clock-names = "oscclk",
0193 "dout_clkcmu_peric0_bus",
0194 "dout_clkcmu_peric0_ip";
0195 };
0196
0197 cmu_peric1: clock-controller@10800000 {
0198 compatible = "samsung,exynosautov9-cmu-peric1";
0199 reg = <0x10800000 0x8000>;
0200 #clock-cells = <1>;
0201
0202 clocks = <&xtcxo>,
0203 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
0204 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
0205 clock-names = "oscclk",
0206 "dout_clkcmu_peric1_bus",
0207 "dout_clkcmu_peric1_ip";
0208 };
0209
0210 cmu_fsys2: clock-controller@17c00000 {
0211 compatible = "samsung,exynosautov9-cmu-fsys2";
0212 reg = <0x17c00000 0x8000>;
0213 #clock-cells = <1>;
0214
0215 clocks = <&xtcxo>,
0216 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
0217 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
0218 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
0219 clock-names = "oscclk",
0220 "dout_clkcmu_fsys2_bus",
0221 "dout_fsys2_clkcmu_ufs_embd",
0222 "dout_fsys2_clkcmu_ethernet";
0223 };
0224
0225 cmu_core: clock-controller@1b030000 {
0226 compatible = "samsung,exynosautov9-cmu-core";
0227 reg = <0x1b030000 0x8000>;
0228 #clock-cells = <1>;
0229
0230 clocks = <&xtcxo>,
0231 <&cmu_top DOUT_CLKCMU_CORE_BUS>;
0232 clock-names = "oscclk",
0233 "dout_clkcmu_core_bus";
0234 };
0235
0236 cmu_busmc: clock-controller@1b200000 {
0237 compatible = "samsung,exynosautov9-cmu-busmc";
0238 reg = <0x1b200000 0x8000>;
0239 #clock-cells = <1>;
0240
0241 clocks = <&xtcxo>,
0242 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>;
0243 clock-names = "oscclk",
0244 "dout_clkcmu_busmc_bus";
0245 };
0246
0247 cmu_top: clock-controller@1b240000 {
0248 compatible = "samsung,exynosautov9-cmu-top";
0249 reg = <0x1b240000 0x8000>;
0250 #clock-cells = <1>;
0251
0252 clocks = <&xtcxo>;
0253 clock-names = "oscclk";
0254 };
0255
0256 gic: interrupt-controller@10101000 {
0257 compatible = "arm,gic-400";
0258 #interrupt-cells = <3>;
0259 #address-cells = <0>;
0260 interrupt-controller;
0261 reg = <0x10101000 0x1000>,
0262 <0x10102000 0x2000>,
0263 <0x10104000 0x2000>,
0264 <0x10106000 0x2000>;
0265 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
0266 IRQ_TYPE_LEVEL_HIGH)>;
0267 };
0268
0269 pdma0: dma-controller@1b2e0000 {
0270 compatible = "arm,pl330", "arm,primecell";
0271 reg = <0x1b2e0000 0x1000>;
0272 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0273 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>;
0274 clock-names = "apb_pclk";
0275 arm,pl330-broken-no-flushp;
0276 #dma-cells = <1>;
0277 };
0278
0279 pinctrl_alive: pinctrl@10450000 {
0280 compatible = "samsung,exynosautov9-pinctrl";
0281 reg = <0x10450000 0x1000>;
0282
0283 wakeup-interrupt-controller {
0284 compatible = "samsung,exynosautov9-wakeup-eint";
0285 };
0286 };
0287
0288 pinctrl_aud: pinctrl@19c60000{
0289 compatible = "samsung,exynosautov9-pinctrl";
0290 reg = <0x19c60000 0x1000>;
0291 };
0292
0293 pinctrl_fsys0: pinctrl@17740000 {
0294 compatible = "samsung,exynosautov9-pinctrl";
0295 reg = <0x17740000 0x1000>;
0296 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0297 };
0298
0299 pinctrl_fsys1: pinctrl@17060000 {
0300 compatible = "samsung,exynosautov9-pinctrl";
0301 reg = <0x17060000 0x1000>;
0302 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0303 };
0304
0305 pinctrl_fsys2: pinctrl@17c30000 {
0306 compatible = "samsung,exynosautov9-pinctrl";
0307 reg = <0x17c30000 0x1000>;
0308 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
0309 };
0310
0311 pinctrl_peric0: pinctrl@10230000 {
0312 compatible = "samsung,exynosautov9-pinctrl";
0313 reg = <0x10230000 0x1000>;
0314 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
0315 };
0316
0317 pinctrl_peric1: pinctrl@10830000 {
0318 compatible = "samsung,exynosautov9-pinctrl";
0319 reg = <0x10830000 0x1000>;
0320 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
0321 };
0322
0323 pmu_system_controller: system-controller@10460000 {
0324 compatible = "samsung,exynos7-pmu", "syscon";
0325 reg = <0x10460000 0x10000>;
0326
0327 reboot: syscon-reboot {
0328 compatible = "syscon-reboot";
0329 regmap = <&pmu_system_controller>;
0330 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
0331 value = <0x2>;
0332 mask = <0x2>;
0333 };
0334
0335 reboot-mode {
0336 compatible = "syscon-reboot-mode";
0337 offset = <0x810>; /* SYSIP_DAT0 */
0338 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>;
0339 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>;
0340 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>;
0341 };
0342 };
0343
0344 syscon_fsys2: syscon@17c20000 {
0345 compatible = "samsung,exynosautov9-sysreg", "syscon";
0346 reg = <0x17c20000 0x1000>;
0347 };
0348
0349 syscon_peric0: syscon@10220000 {
0350 compatible = "samsung,exynosautov9-sysreg", "syscon";
0351 reg = <0x10220000 0x2000>;
0352 };
0353
0354 syscon_peric1: syscon@10820000 {
0355 compatible = "samsung,exynosautov9-sysreg", "syscon";
0356 reg = <0x10820000 0x2000>;
0357 };
0358
0359 usi_0: usi@103000c0 {
0360 compatible = "samsung,exynosautov9-usi",
0361 "samsung,exynos850-usi";
0362 reg = <0x103000c0 0x20>;
0363 samsung,sysreg = <&syscon_peric0 0x1000>;
0364 samsung,mode = <USI_V2_UART>;
0365 #address-cells = <1>;
0366 #size-cells = <1>;
0367 ranges;
0368 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
0369 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
0370 clock-names = "pclk", "ipclk";
0371 status = "disabled";
0372
0373 serial_0: serial@10300000 {
0374 compatible = "samsung,exynosautov9-uart",
0375 "samsung,exynos850-uart";
0376 reg = <0x10300000 0xc0>;
0377 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
0378 pinctrl-names = "default";
0379 pinctrl-0 = <&uart0_bus>;
0380 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,
0381 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;
0382 clock-names = "uart", "clk_uart_baud0";
0383 samsung,uart-fifosize = <256>;
0384 status = "disabled";
0385 };
0386
0387 spi_0: spi@10300000 {
0388 compatible = "samsung,exynosautov9-spi";
0389 reg = <0x10300000 0x30>;
0390 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
0391 pinctrl-names = "default";
0392 pinctrl-0 = <&spi0_bus &spi0_cs_func>;
0393 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
0394 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>,
0395 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
0396 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0397 samsung,spi-src-clk = <0>;
0398 dmas = <&pdma0 1>, <&pdma0 0>;
0399 dma-names = "tx", "rx";
0400 num-cs = <1>;
0401 #address-cells = <1>;
0402 #size-cells = <0>;
0403 status = "disabled";
0404 };
0405
0406 hsi2c_0: i2c@10300000 {
0407 compatible = "samsung,exynosautov9-hsi2c";
0408 reg = <0x10300000 0xc0>;
0409 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&hsi2c0_bus>;
0412 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>,
0413 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>;
0414 clock-names = "hsi2c", "hsi2c_pclk";
0415 #address-cells = <1>;
0416 #size-cells = <0>;
0417 status = "disabled";
0418 };
0419 };
0420
0421 usi_i2c_0: usi@103100c0 {
0422 compatible = "samsung,exynosautov9-usi",
0423 "samsung,exynos850-usi";
0424 reg = <0x103100c0 0x20>;
0425 samsung,sysreg = <&syscon_peric0 0x1004>;
0426 samsung,mode = <USI_V2_I2C>;
0427 #address-cells = <1>;
0428 #size-cells = <1>;
0429 ranges;
0430 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>,
0431 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>;
0432 clock-names = "pclk", "ipclk";
0433 status = "disabled";
0434
0435 hsi2c_1: i2c@10310000 {
0436 compatible = "samsung,exynosautov9-hsi2c";
0437 reg = <0x10310000 0xc0>;
0438 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
0439 pinctrl-names = "default";
0440 pinctrl-0 = <&hsi2c1_bus>;
0441 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>,
0442 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>;
0443 clock-names = "hsi2c", "hsi2c_pclk";
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 status = "disabled";
0447 };
0448 };
0449
0450 usi_1: usi@103200c0 {
0451 compatible = "samsung,exynosautov9-usi",
0452 "samsung,exynos850-usi";
0453 reg = <0x103200c0 0x20>;
0454 samsung,sysreg = <&syscon_peric0 0x1008>;
0455 samsung,mode = <USI_V2_UART>;
0456 #address-cells = <1>;
0457 #size-cells = <1>;
0458 ranges;
0459 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>,
0460 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>;
0461 clock-names = "pclk", "ipclk";
0462 status = "disabled";
0463
0464 serial_1: serial@10320000 {
0465 compatible = "samsung,exynosautov9-uart",
0466 "samsung,exynos850-uart";
0467 reg = <0x10320000 0xc0>;
0468 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
0469 pinctrl-names = "default";
0470 pinctrl-0 = <&uart1_bus>;
0471 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>,
0472 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>;
0473 clock-names = "uart", "clk_uart_baud0";
0474 samsung,uart-fifosize = <256>;
0475 status = "disabled";
0476 };
0477
0478 spi_1: spi@10320000 {
0479 compatible = "samsung,exynosautov9-spi";
0480 reg = <0x10320000 0x30>;
0481 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
0482 pinctrl-names = "default";
0483 pinctrl-0 = <&spi1_bus &spi1_cs_func>;
0484 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>,
0485 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>,
0486 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>;
0487 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0488 samsung,spi-src-clk = <0>;
0489 dmas = <&pdma0 3>, <&pdma0 2>;
0490 dma-names = "tx", "rx";
0491 num-cs = <1>;
0492 #address-cells = <1>;
0493 #size-cells = <0>;
0494 status = "disabled";
0495 };
0496
0497 hsi2c_2: i2c@10320000 {
0498 compatible = "samsung,exynosautov9-hsi2c";
0499 reg = <0x10320000 0xc0>;
0500 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
0501 pinctrl-names = "default";
0502 pinctrl-0 = <&hsi2c2_bus>;
0503 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>,
0504 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>;
0505 clock-names = "hsi2c", "hsi2c_pclk";
0506 #address-cells = <1>;
0507 #size-cells = <0>;
0508 status = "disabled";
0509 };
0510 };
0511
0512 usi_i2c_1: usi@103300c0 {
0513 compatible = "samsung,exynosautov9-usi",
0514 "samsung,exynos850-usi";
0515 reg = <0x103300c0 0x20>;
0516 samsung,sysreg = <&syscon_peric0 0x100c>;
0517 samsung,mode = <USI_V2_I2C>;
0518 #address-cells = <1>;
0519 #size-cells = <1>;
0520 ranges;
0521 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>,
0522 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>;
0523 clock-names = "pclk", "ipclk";
0524 status = "disabled";
0525
0526 hsi2c_3: i2c@10330000 {
0527 compatible = "samsung,exynosautov9-hsi2c";
0528 reg = <0x10330000 0xc0>;
0529 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
0530 pinctrl-names = "default";
0531 pinctrl-0 = <&hsi2c3_bus>;
0532 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>,
0533 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>;
0534 clock-names = "hsi2c", "hsi2c_pclk";
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537 status = "disabled";
0538 };
0539 };
0540
0541 usi_2: usi@103400c0 {
0542 compatible = "samsung,exynosautov9-usi",
0543 "samsung,exynos850-usi";
0544 reg = <0x103400c0 0x20>;
0545 samsung,sysreg = <&syscon_peric0 0x1010>;
0546 samsung,mode = <USI_V2_UART>;
0547 #address-cells = <1>;
0548 #size-cells = <1>;
0549 ranges;
0550 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>,
0551 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>;
0552 clock-names = "pclk", "ipclk";
0553 status = "disabled";
0554
0555 serial_2: serial@10340000 {
0556 compatible = "samsung,exynosautov9-uart",
0557 "samsung,exynos850-uart";
0558 reg = <0x10340000 0xc0>;
0559 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
0560 pinctrl-names = "default";
0561 pinctrl-0 = <&uart2_bus>;
0562 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>,
0563 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>;
0564 clock-names = "uart", "clk_uart_baud0";
0565 samsung,uart-fifosize = <64>;
0566 status = "disabled";
0567 };
0568
0569 spi_2: spi@10340000 {
0570 compatible = "samsung,exynosautov9-spi";
0571 reg = <0x10340000 0x30>;
0572 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
0573 pinctrl-names = "default";
0574 pinctrl-0 = <&spi2_bus &spi2_cs_func>;
0575 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>,
0576 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>,
0577 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>;
0578 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0579 samsung,spi-src-clk = <0>;
0580 dmas = <&pdma0 5>, <&pdma0 4>;
0581 dma-names = "tx", "rx";
0582 num-cs = <1>;
0583 #address-cells = <1>;
0584 #size-cells = <0>;
0585 status = "disabled";
0586 };
0587
0588 hsi2c_4: i2c@10340000 {
0589 compatible = "samsung,exynosautov9-hsi2c";
0590 reg = <0x10340000 0xc0>;
0591 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
0592 pinctrl-names = "default";
0593 pinctrl-0 = <&hsi2c4_bus>;
0594 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>,
0595 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>;
0596 clock-names = "hsi2c", "hsi2c_pclk";
0597 #address-cells = <1>;
0598 #size-cells = <0>;
0599 status = "disabled";
0600 };
0601 };
0602
0603 usi_i2c_2: usi@103500c0 {
0604 compatible = "samsung,exynosautov9-usi",
0605 "samsung,exynos850-usi";
0606 reg = <0x103500c0 0x20>;
0607 samsung,sysreg = <&syscon_peric0 0x1014>;
0608 samsung,mode = <USI_V2_I2C>;
0609 #address-cells = <1>;
0610 #size-cells = <1>;
0611 ranges;
0612 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>,
0613 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>;
0614 clock-names = "pclk", "ipclk";
0615 status = "disabled";
0616
0617 hsi2c_5: i2c@10350000 {
0618 compatible = "samsung,exynosautov9-hsi2c";
0619 reg = <0x10350000 0xc0>;
0620 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
0621 pinctrl-names = "default";
0622 pinctrl-0 = <&hsi2c5_bus>;
0623 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>,
0624 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>;
0625 clock-names = "hsi2c", "hsi2c_pclk";
0626 #address-cells = <1>;
0627 #size-cells = <0>;
0628 status = "disabled";
0629 };
0630 };
0631
0632 usi_3: usi@103600c0 {
0633 compatible = "samsung,exynosautov9-usi",
0634 "samsung,exynos850-usi";
0635 reg = <0x103600c0 0x20>;
0636 samsung,sysreg = <&syscon_peric0 0x1018>;
0637 samsung,mode = <USI_V2_UART>;
0638 #address-cells = <1>;
0639 #size-cells = <1>;
0640 ranges;
0641 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>,
0642 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>;
0643 clock-names = "pclk", "ipclk";
0644 status = "disabled";
0645
0646 serial_3: serial@10360000 {
0647 compatible = "samsung,exynosautov9-uart",
0648 "samsung,exynos850-uart";
0649 reg = <0x10360000 0xc0>;
0650 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
0651 pinctrl-names = "default";
0652 pinctrl-0 = <&uart3_bus>;
0653 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>,
0654 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>;
0655 clock-names = "uart", "clk_uart_baud0";
0656 samsung,uart-fifosize = <64>;
0657 status = "disabled";
0658 };
0659
0660 spi_3: spi@10360000 {
0661 compatible = "samsung,exynosautov9-spi";
0662 reg = <0x10360000 0x30>;
0663 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
0664 pinctrl-names = "default";
0665 pinctrl-0 = <&spi3_bus &spi3_cs_func>;
0666 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>,
0667 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>,
0668 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>;
0669 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0670 samsung,spi-src-clk = <0>;
0671 dmas = <&pdma0 7>, <&pdma0 6>;
0672 dma-names = "tx", "rx";
0673 num-cs = <1>;
0674 #address-cells = <1>;
0675 #size-cells = <0>;
0676 status = "disabled";
0677 };
0678
0679 hsi2c_6: i2c@10360000 {
0680 compatible = "samsung,exynosautov9-hsi2c";
0681 reg = <0x10360000 0xc0>;
0682 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
0683 pinctrl-names = "default";
0684 pinctrl-0 = <&hsi2c6_bus>;
0685 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>,
0686 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>;
0687 clock-names = "hsi2c", "hsi2c_pclk";
0688 #address-cells = <1>;
0689 #size-cells = <0>;
0690 status = "disabled";
0691 };
0692 };
0693
0694 usi_i2c_3: usi@103700c0 {
0695 compatible = "samsung,exynosautov9-usi",
0696 "samsung,exynos850-usi";
0697 reg = <0x103700c0 0x20>;
0698 samsung,sysreg = <&syscon_peric0 0x101c>;
0699 samsung,mode = <USI_V2_I2C>;
0700 #address-cells = <1>;
0701 #size-cells = <1>;
0702 ranges;
0703 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>,
0704 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>;
0705 clock-names = "pclk", "ipclk";
0706 status = "disabled";
0707
0708 hsi2c_7: i2c@10370000 {
0709 compatible = "samsung,exynosautov9-hsi2c";
0710 reg = <0x10370000 0xc0>;
0711 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
0712 pinctrl-names = "default";
0713 pinctrl-0 = <&hsi2c7_bus>;
0714 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>,
0715 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>;
0716 clock-names = "hsi2c", "hsi2c_pclk";
0717 #address-cells = <1>;
0718 #size-cells = <0>;
0719 status = "disabled";
0720 };
0721 };
0722
0723 usi_4: usi@103800c0 {
0724 compatible = "samsung,exynosautov9-usi",
0725 "samsung,exynos850-usi";
0726 reg = <0x103800c0 0x20>;
0727 samsung,sysreg = <&syscon_peric0 0x1020>;
0728 samsung,mode = <USI_V2_UART>;
0729 #address-cells = <1>;
0730 #size-cells = <1>;
0731 ranges;
0732 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>,
0733 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>;
0734 clock-names = "pclk", "ipclk";
0735 status = "disabled";
0736
0737 serial_4: serial@10380000 {
0738 compatible = "samsung,exynosautov9-uart",
0739 "samsung,exynos850-uart";
0740 reg = <0x10380000 0xc0>;
0741 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0742 pinctrl-names = "default";
0743 pinctrl-0 = <&uart4_bus>;
0744 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>,
0745 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>;
0746 clock-names = "uart", "clk_uart_baud0";
0747 samsung,uart-fifosize = <64>;
0748 status = "disabled";
0749 };
0750
0751 spi_4: spi@10380000 {
0752 compatible = "samsung,exynosautov9-spi";
0753 reg = <0x10380000 0x30>;
0754 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0755 pinctrl-names = "default";
0756 pinctrl-0 = <&spi4_bus &spi4_cs_func>;
0757 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>,
0758 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>,
0759 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>;
0760 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0761 samsung,spi-src-clk = <0>;
0762 dmas = <&pdma0 9>, <&pdma0 8>;
0763 dma-names = "tx", "rx";
0764 num-cs = <1>;
0765 #address-cells = <1>;
0766 #size-cells = <0>;
0767 status = "disabled";
0768 };
0769
0770 hsi2c_8: i2c@10380000 {
0771 compatible = "samsung,exynosautov9-hsi2c";
0772 reg = <0x10380000 0xc0>;
0773 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0774 pinctrl-names = "default";
0775 pinctrl-0 = <&hsi2c8_bus>;
0776 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>,
0777 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>;
0778 clock-names = "hsi2c", "hsi2c_pclk";
0779 #address-cells = <1>;
0780 #size-cells = <0>;
0781 status = "disabled";
0782 };
0783 };
0784
0785 usi_i2c_4: usi@103900c0 {
0786 compatible = "samsung,exynosautov9-usi",
0787 "samsung,exynos850-usi";
0788 reg = <0x103900c0 0x20>;
0789 samsung,sysreg = <&syscon_peric0 0x1024>;
0790 samsung,mode = <USI_V2_I2C>;
0791 #address-cells = <1>;
0792 #size-cells = <1>;
0793 ranges;
0794 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>,
0795 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>;
0796 clock-names = "pclk", "ipclk";
0797 status = "disabled";
0798
0799 hsi2c_9: i2c@10390000 {
0800 compatible = "samsung,exynosautov9-hsi2c";
0801 reg = <0x10390000 0xc0>;
0802 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
0803 pinctrl-names = "default";
0804 pinctrl-0 = <&hsi2c9_bus>;
0805 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>,
0806 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>;
0807 clock-names = "hsi2c", "hsi2c_pclk";
0808 #address-cells = <1>;
0809 #size-cells = <0>;
0810 status = "disabled";
0811 };
0812 };
0813
0814 usi_5: usi@103a00c0 {
0815 compatible = "samsung,exynosautov9-usi",
0816 "samsung,exynos850-usi";
0817 reg = <0x103a00c0 0x20>;
0818 samsung,sysreg = <&syscon_peric0 0x1028>;
0819 samsung,mode = <USI_V2_UART>;
0820 #address-cells = <1>;
0821 #size-cells = <1>;
0822 ranges;
0823 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>,
0824 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>;
0825 clock-names = "pclk", "ipclk";
0826 status = "disabled";
0827
0828 serial_5: serial@103a0000 {
0829 compatible = "samsung,exynosautov9-uart",
0830 "samsung,exynos850-uart";
0831 reg = <0x103a0000 0xc0>;
0832 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0833 pinctrl-names = "default";
0834 pinctrl-0 = <&uart5_bus>;
0835 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>,
0836 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>;
0837 clock-names = "uart", "clk_uart_baud0";
0838 samsung,uart-fifosize = <64>;
0839 status = "disabled";
0840 };
0841
0842 spi_5: spi@103a0000 {
0843 compatible = "samsung,exynosautov9-spi";
0844 reg = <0x103a0000 0x30>;
0845 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0846 pinctrl-names = "default";
0847 pinctrl-0 = <&spi5_bus &spi5_cs_func>;
0848 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>,
0849 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>,
0850 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>;
0851 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0852 samsung,spi-src-clk = <0>;
0853 dmas = <&pdma0 11>, <&pdma0 10>;
0854 dma-names = "tx", "rx";
0855 num-cs = <1>;
0856 #address-cells = <1>;
0857 #size-cells = <0>;
0858 status = "disabled";
0859 };
0860
0861 hsi2c_10: i2c@103a0000 {
0862 compatible = "samsung,exynosautov9-hsi2c";
0863 reg = <0x103a0000 0xc0>;
0864 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0865 pinctrl-names = "default";
0866 pinctrl-0 = <&hsi2c10_bus>;
0867 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>,
0868 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>;
0869 clock-names = "hsi2c", "hsi2c_pclk";
0870 #address-cells = <1>;
0871 #size-cells = <0>;
0872 status = "disabled";
0873 };
0874 };
0875
0876 usi_i2c_5: usi@103b00c0 {
0877 compatible = "samsung,exynosautov9-usi",
0878 "samsung,exynos850-usi";
0879 reg = <0x103b00c0 0x20>;
0880 samsung,sysreg = <&syscon_peric0 0x102c>;
0881 samsung,mode = <USI_V2_I2C>;
0882 #address-cells = <1>;
0883 #size-cells = <1>;
0884 ranges;
0885 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>,
0886 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>;
0887 clock-names = "pclk", "ipclk";
0888 status = "disabled";
0889
0890 hsi2c_11: i2c@103b0000 {
0891 compatible = "samsung,exynosautov9-hsi2c";
0892 reg = <0x103b0000 0xc0>;
0893 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
0894 pinctrl-names = "default";
0895 pinctrl-0 = <&hsi2c11_bus>;
0896 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>,
0897 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>;
0898 clock-names = "hsi2c", "hsi2c_pclk";
0899 #address-cells = <1>;
0900 #size-cells = <0>;
0901 status = "disabled";
0902 };
0903 };
0904
0905 usi_6: usi@109000c0 {
0906 compatible = "samsung,exynosautov9-usi",
0907 "samsung,exynos850-usi";
0908 reg = <0x109000c0 0x20>;
0909 samsung,sysreg = <&syscon_peric1 0x1000>;
0910 samsung,mode = <USI_V2_UART>;
0911 #address-cells = <1>;
0912 #size-cells = <1>;
0913 ranges;
0914 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>,
0915 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>;
0916 clock-names = "pclk", "ipclk";
0917 status = "disabled";
0918
0919 serial_6: serial@10900000 {
0920 compatible = "samsung,exynosautov9-uart",
0921 "samsung,exynos850-uart";
0922 reg = <0x10900000 0xc0>;
0923 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
0924 pinctrl-names = "default";
0925 pinctrl-0 = <&uart6_bus>;
0926 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>,
0927 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>;
0928 clock-names = "uart", "clk_uart_baud0";
0929 samsung,uart-fifosize = <256>;
0930 status = "disabled";
0931 };
0932
0933 spi_6: spi@10900000 {
0934 compatible = "samsung,exynosautov9-spi";
0935 reg = <0x10900000 0x30>;
0936 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
0937 pinctrl-names = "default";
0938 pinctrl-0 = <&spi6_bus &spi6_cs_func>;
0939 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>,
0940 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>,
0941 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>;
0942 clock-names = "spi", "spi_busclk0", "spi_ioclk";
0943 samsung,spi-src-clk = <0>;
0944 dmas = <&pdma0 13>, <&pdma0 12>;
0945 dma-names = "tx", "rx";
0946 num-cs = <1>;
0947 #address-cells = <1>;
0948 #size-cells = <0>;
0949 status = "disabled";
0950 };
0951
0952 hsi2c_12: i2c@10900000 {
0953 compatible = "samsung,exynosautov9-hsi2c";
0954 reg = <0x10900000 0xc0>;
0955 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
0956 pinctrl-names = "default";
0957 pinctrl-0 = <&hsi2c12_bus>;
0958 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>,
0959 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>;
0960 clock-names = "hsi2c", "hsi2c_pclk";
0961 #address-cells = <1>;
0962 #size-cells = <0>;
0963 status = "disabled";
0964 };
0965 };
0966
0967 usi_i2c_6: usi@109100c0 {
0968 compatible = "samsung,exynosautov9-usi",
0969 "samsung,exynos850-usi";
0970 reg = <0x109100c0 0x20>;
0971 samsung,sysreg = <&syscon_peric1 0x1004>;
0972 samsung,mode = <USI_V2_I2C>;
0973 #address-cells = <1>;
0974 #size-cells = <1>;
0975 ranges;
0976 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>,
0977 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>;
0978 clock-names = "pclk", "ipclk";
0979 status = "disabled";
0980
0981 hsi2c_13: i2c@10910000 {
0982 compatible = "samsung,exynosautov9-hsi2c";
0983 reg = <0x10910000 0xc0>;
0984 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
0985 pinctrl-names = "default";
0986 pinctrl-0 = <&hsi2c13_bus>;
0987 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>,
0988 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>;
0989 clock-names = "hsi2c", "hsi2c_pclk";
0990 #address-cells = <1>;
0991 #size-cells = <0>;
0992 status = "disabled";
0993 };
0994 };
0995
0996 usi_7: usi@109200c0 {
0997 compatible = "samsung,exynosautov9-usi",
0998 "samsung,exynos850-usi";
0999 reg = <0x109200c0 0x20>;
1000 samsung,sysreg = <&syscon_peric1 0x1008>;
1001 samsung,mode = <USI_V2_UART>;
1002 #address-cells = <1>;
1003 #size-cells = <1>;
1004 ranges;
1005 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>,
1006 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>;
1007 clock-names = "pclk", "ipclk";
1008 status = "disabled";
1009
1010 serial_7: serial@10920000 {
1011 compatible = "samsung,exynosautov9-uart",
1012 "samsung,exynos850-uart";
1013 reg = <0x10920000 0xc0>;
1014 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&uart7_bus>;
1017 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>,
1018 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>;
1019 clock-names = "uart", "clk_uart_baud0";
1020 samsung,uart-fifosize = <64>;
1021 status = "disabled";
1022 };
1023
1024 spi_7: spi@10920000 {
1025 compatible = "samsung,exynosautov9-spi";
1026 reg = <0x10920000 0x30>;
1027 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&spi7_bus &spi7_cs_func>;
1030 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>,
1031 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>,
1032 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>;
1033 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1034 samsung,spi-src-clk = <0>;
1035 dmas = <&pdma0 15>, <&pdma0 14>;
1036 dma-names = "tx", "rx";
1037 num-cs = <1>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 status = "disabled";
1041 };
1042
1043 hsi2c_14: i2c@10920000 {
1044 compatible = "samsung,exynosautov9-hsi2c";
1045 reg = <0x10920000 0xc0>;
1046 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&hsi2c14_bus>;
1049 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>,
1050 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>;
1051 clock-names = "hsi2c", "hsi2c_pclk";
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 status = "disabled";
1055 };
1056 };
1057
1058 usi_i2c_7: usi@109300c0 {
1059 compatible = "samsung,exynosautov9-usi",
1060 "samsung,exynos850-usi";
1061 reg = <0x109300c0 0x20>;
1062 samsung,sysreg = <&syscon_peric1 0x100c>;
1063 samsung,mode = <USI_V2_I2C>;
1064 #address-cells = <1>;
1065 #size-cells = <1>;
1066 ranges;
1067 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>,
1068 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>;
1069 clock-names = "pclk", "ipclk";
1070 status = "disabled";
1071
1072 hsi2c_15: i2c@10930000 {
1073 compatible = "samsung,exynosautov9-hsi2c";
1074 reg = <0x10930000 0xc0>;
1075 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&hsi2c15_bus>;
1078 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>,
1079 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>;
1080 clock-names = "hsi2c", "hsi2c_pclk";
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 status = "disabled";
1084 };
1085 };
1086
1087 usi_8: usi@109400c0 {
1088 compatible = "samsung,exynosautov9-usi",
1089 "samsung,exynos850-usi";
1090 reg = <0x109400c0 0x20>;
1091 samsung,sysreg = <&syscon_peric1 0x1010>;
1092 samsung,mode = <USI_V2_UART>;
1093 #address-cells = <1>;
1094 #size-cells = <1>;
1095 ranges;
1096 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>,
1097 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>;
1098 clock-names = "pclk", "ipclk";
1099 status = "disabled";
1100
1101 serial_8: serial@10940000 {
1102 compatible = "samsung,exynosautov9-uart",
1103 "samsung,exynos850-uart";
1104 reg = <0x10940000 0xc0>;
1105 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&uart8_bus>;
1108 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>,
1109 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>;
1110 clock-names = "uart", "clk_uart_baud0";
1111 samsung,uart-fifosize = <64>;
1112 status = "disabled";
1113 };
1114
1115 spi_8: spi@10940000 {
1116 compatible = "samsung,exynosautov9-spi";
1117 reg = <0x10940000 0x30>;
1118 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&spi8_bus &spi8_cs_func>;
1121 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>,
1122 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>,
1123 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>;
1124 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1125 samsung,spi-src-clk = <0>;
1126 dmas = <&pdma0 17>, <&pdma0 16>;
1127 dma-names = "tx", "rx";
1128 num-cs = <1>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 status = "disabled";
1132 };
1133
1134 hsi2c_16: i2c@10940000 {
1135 compatible = "samsung,exynosautov9-hsi2c";
1136 reg = <0x10940000 0xc0>;
1137 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>;
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&hsi2c16_bus>;
1140 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>,
1141 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>;
1142 clock-names = "hsi2c", "hsi2c_pclk";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 status = "disabled";
1146 };
1147 };
1148
1149 usi_i2c_8: usi@109500c0 {
1150 compatible = "samsung,exynosautov9-usi",
1151 "samsung,exynos850-usi";
1152 reg = <0x109500c0 0x20>;
1153 samsung,sysreg = <&syscon_peric1 0x1014>;
1154 samsung,mode = <USI_V2_I2C>;
1155 #address-cells = <1>;
1156 #size-cells = <1>;
1157 ranges;
1158 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>,
1159 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>;
1160 clock-names = "pclk", "ipclk";
1161 status = "disabled";
1162
1163 hsi2c_17: i2c@10950000 {
1164 compatible = "samsung,exynosautov9-hsi2c";
1165 reg = <0x10950000 0xc0>;
1166 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&hsi2c17_bus>;
1169 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>,
1170 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>;
1171 clock-names = "hsi2c", "hsi2c_pclk";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 status = "disabled";
1175 };
1176 };
1177
1178 usi_9: usi@109600c0 {
1179 compatible = "samsung,exynosautov9-usi",
1180 "samsung,exynos850-usi";
1181 reg = <0x109600c0 0x20>;
1182 samsung,sysreg = <&syscon_peric1 0x1018>;
1183 samsung,mode = <USI_V2_UART>;
1184 #address-cells = <1>;
1185 #size-cells = <1>;
1186 ranges;
1187 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>,
1188 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>;
1189 clock-names = "pclk", "ipclk";
1190 status = "disabled";
1191
1192 serial_9: serial@10960000 {
1193 compatible = "samsung,exynosautov9-uart",
1194 "samsung,exynos850-uart";
1195 reg = <0x10960000 0xc0>;
1196 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&uart9_bus>;
1199 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>,
1200 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>;
1201 clock-names = "uart", "clk_uart_baud0";
1202 samsung,uart-fifosize = <64>;
1203 status = "disabled";
1204 };
1205
1206 spi_9: spi@10960000 {
1207 compatible = "samsung,exynosautov9-spi";
1208 reg = <0x10960000 0x30>;
1209 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&spi9_bus &spi9_cs_func>;
1212 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>,
1213 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>,
1214 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>;
1215 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1216 samsung,spi-src-clk = <0>;
1217 dmas = <&pdma0 19>, <&pdma0 18>;
1218 dma-names = "tx", "rx";
1219 num-cs = <1>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 status = "disabled";
1223 };
1224
1225 hsi2c_18: i2c@10960000 {
1226 compatible = "samsung,exynosautov9-hsi2c";
1227 reg = <0x10960000 0xc0>;
1228 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&hsi2c18_bus>;
1231 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>,
1232 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>;
1233 clock-names = "hsi2c", "hsi2c_pclk";
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1236 status = "disabled";
1237 };
1238 };
1239
1240 usi_i2c_9: usi@109700c0 {
1241 compatible = "samsung,exynosautov9-usi",
1242 "samsung,exynos850-usi";
1243 reg = <0x109700c0 0x20>;
1244 samsung,sysreg = <&syscon_peric1 0x101c>;
1245 samsung,mode = <USI_V2_I2C>;
1246 #address-cells = <1>;
1247 #size-cells = <1>;
1248 ranges;
1249 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>,
1250 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>;
1251 clock-names = "pclk", "ipclk";
1252 status = "disabled";
1253
1254 hsi2c_19: i2c@10970000 {
1255 compatible = "samsung,exynosautov9-hsi2c";
1256 reg = <0x10970000 0xc0>;
1257 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&hsi2c19_bus>;
1260 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>,
1261 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>;
1262 clock-names = "hsi2c", "hsi2c_pclk";
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1265 status = "disabled";
1266 };
1267 };
1268
1269 usi_10: usi@109800c0 {
1270 compatible = "samsung,exynosautov9-usi",
1271 "samsung,exynos850-usi";
1272 reg = <0x109800c0 0x20>;
1273 samsung,sysreg = <&syscon_peric1 0x1020>;
1274 samsung,mode = <USI_V2_UART>;
1275 #address-cells = <1>;
1276 #size-cells = <1>;
1277 ranges;
1278 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>,
1279 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>;
1280 clock-names = "pclk", "ipclk";
1281 status = "disabled";
1282
1283 serial_10: serial@10980000 {
1284 compatible = "samsung,exynosautov9-uart",
1285 "samsung,exynos850-uart";
1286 reg = <0x10980000 0xc0>;
1287 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1288 pinctrl-names = "default";
1289 pinctrl-0 = <&uart10_bus>;
1290 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>,
1291 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>;
1292 clock-names = "uart", "clk_uart_baud0";
1293 samsung,uart-fifosize = <64>;
1294 status = "disabled";
1295 };
1296
1297 spi_10: spi@10980000 {
1298 compatible = "samsung,exynosautov9-spi";
1299 reg = <0x10980000 0x30>;
1300 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&spi10_bus &spi10_cs_func>;
1303 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>,
1304 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>,
1305 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>;
1306 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1307 samsung,spi-src-clk = <0>;
1308 dmas = <&pdma0 21>, <&pdma0 20>;
1309 dma-names = "tx", "rx";
1310 num-cs = <1>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1313 status = "disabled";
1314 };
1315
1316 hsi2c_20: i2c@10980000 {
1317 compatible = "samsung,exynosautov9-hsi2c";
1318 reg = <0x10980000 0xc0>;
1319 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&hsi2c20_bus>;
1322 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>,
1323 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>;
1324 clock-names = "hsi2c", "hsi2c_pclk";
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1327 status = "disabled";
1328 };
1329 };
1330
1331 usi_i2c_10: usi@109900c0 {
1332 compatible = "samsung,exynosautov9-usi",
1333 "samsung,exynos850-usi";
1334 reg = <0x109900c0 0x20>;
1335 samsung,sysreg = <&syscon_peric1 0x1024>;
1336 samsung,mode = <USI_V2_I2C>;
1337 #address-cells = <1>;
1338 #size-cells = <1>;
1339 ranges;
1340 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>,
1341 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>;
1342 clock-names = "pclk", "ipclk";
1343 status = "disabled";
1344
1345 hsi2c_21: i2c@10990000 {
1346 compatible = "samsung,exynosautov9-hsi2c";
1347 reg = <0x10990000 0xc0>;
1348 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
1349 pinctrl-names = "default";
1350 pinctrl-0 = <&hsi2c21_bus>;
1351 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>,
1352 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>;
1353 clock-names = "hsi2c", "hsi2c_pclk";
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 status = "disabled";
1357 };
1358 };
1359
1360 usi_11: usi@109a00c0 {
1361 compatible = "samsung,exynosautov9-usi",
1362 "samsung,exynos850-usi";
1363 reg = <0x109a00c0 0x20>;
1364 samsung,sysreg = <&syscon_peric1 0x1028>;
1365 samsung,mode = <USI_V2_UART>;
1366 #address-cells = <1>;
1367 #size-cells = <1>;
1368 ranges;
1369 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>,
1370 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>;
1371 clock-names = "pclk", "ipclk";
1372 status = "disabled";
1373
1374 serial_11: serial@109a0000 {
1375 compatible = "samsung,exynosautov9-uart",
1376 "samsung,exynos850-uart";
1377 reg = <0x109a0000 0xc0>;
1378 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1379 pinctrl-names = "default";
1380 pinctrl-0 = <&uart11_bus>;
1381 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>,
1382 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>;
1383 clock-names = "uart", "clk_uart_baud0";
1384 samsung,uart-fifosize = <64>;
1385 status = "disabled";
1386 };
1387
1388 spi_11: spi@109a0000 {
1389 compatible = "samsung,exynosautov9-spi";
1390 reg = <0x109a0000 0x30>;
1391 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&spi11_bus &spi11_cs_func>;
1394 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>,
1395 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>,
1396 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>;
1397 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1398 samsung,spi-src-clk = <0>;
1399 num-cs = <1>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1402 status = "disabled";
1403 };
1404
1405 hsi2c_22: i2c@109a0000 {
1406 compatible = "samsung,exynosautov9-hsi2c";
1407 reg = <0x109a0000 0xc0>;
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&hsi2c22_bus>;
1410 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>,
1412 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>;
1413 clock-names = "hsi2c", "hsi2c_pclk";
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 status = "disabled";
1417 };
1418 };
1419
1420 usi_i2c_11: usi@109b00c0 {
1421 compatible = "samsung,exynosautov9-usi",
1422 "samsung,exynos850-usi";
1423 reg = <0x109b00c0 0x20>;
1424 samsung,sysreg = <&syscon_peric1 0x102c>;
1425 samsung,mode = <USI_V2_I2C>;
1426 #address-cells = <1>;
1427 #size-cells = <1>;
1428 ranges;
1429 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>,
1430 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>;
1431 clock-names = "pclk", "ipclk";
1432 status = "disabled";
1433
1434 hsi2c_23: i2c@109b0000 {
1435 compatible = "samsung,exynosautov9-hsi2c";
1436 reg = <0x109b0000 0xc0>;
1437 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&hsi2c23_bus>;
1440 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>,
1441 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>;
1442 clock-names = "hsi2c", "hsi2c_pclk";
1443 #address-cells = <1>;
1444 #size-cells = <0>;
1445 status = "disabled";
1446 };
1447 };
1448
1449 ufs_0_phy: phy@17e04000 {
1450 compatible = "samsung,exynosautov9-ufs-phy";
1451 reg = <0x17e04000 0xc00>;
1452 reg-names = "phy-pma";
1453 samsung,pmu-syscon = <&pmu_system_controller>;
1454 #phy-cells = <0>;
1455 clocks = <&xtcxo>;
1456 clock-names = "ref_clk";
1457 status = "disabled";
1458 };
1459
1460 ufs_0: ufs@17e00000 {
1461 compatible = "samsung,exynosautov9-ufs";
1462
1463 reg = <0x17e00000 0x100>,
1464 <0x17e01100 0x410>,
1465 <0x17e80000 0x8000>,
1466 <0x17dc0000 0x2200>;
1467 reg-names = "hci", "vs_hci", "unipro", "ufsp";
1468 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
1470 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>;
1471 clock-names = "core_clk", "sclk_unipro_main";
1472 freq-table-hz = <0 0>, <0 0>;
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1475 phys = <&ufs_0_phy>;
1476 phy-names = "ufs-phy";
1477 samsung,sysreg = <&syscon_fsys2 0x710>;
1478 status = "disabled";
1479 };
1480
1481 ufs_1_phy: phy@17f04000 {
1482 compatible = "samsung,exynosautov9-ufs-phy";
1483 reg = <0x17f04000 0xc00>;
1484 reg-names = "phy-pma";
1485 samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
1486 #phy-cells = <0>;
1487 clocks = <&xtcxo>;
1488 clock-names = "ref_clk";
1489 status = "disabled";
1490 };
1491
1492 ufs_1: ufs@17f00000 {
1493 compatible = "samsung,exynosautov9-ufs";
1494
1495 reg = <0x17f00000 0x100>,
1496 <0x17f01100 0x410>,
1497 <0x17f80000 0x8000>,
1498 <0x17de0000 0x2200>;
1499 reg-names = "hci", "vs_hci", "unipro", "ufsp";
1500 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1501 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
1502 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
1503 clock-names = "core_clk", "sclk_unipro_main";
1504 freq-table-hz = <0 0>, <0 0>;
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
1507 phys = <&ufs_1_phy>;
1508 phy-names = "ufs-phy";
1509 samsung,sysreg = <&syscon_fsys2 0x714>;
1510 status = "disabled";
1511 };
1512
1513 watchdog_cl0: watchdog@10050000 {
1514 compatible = "samsung,exynosautov9-wdt";
1515 reg = <0x10050000 0x100>;
1516 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>;
1518 clock-names = "watchdog", "watchdog_src";
1519 samsung,syscon-phandle = <&pmu_system_controller>;
1520 samsung,cluster-index = <0>;
1521 };
1522
1523 watchdog_cl1: watchdog@10060000 {
1524 compatible = "samsung,exynosautov9-wdt";
1525 reg = <0x10060000 0x100>;
1526 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
1527 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>;
1528 clock-names = "watchdog", "watchdog_src";
1529 samsung,syscon-phandle = <&pmu_system_controller>;
1530 samsung,cluster-index = <1>;
1531 };
1532 };
1533 };
1534
1535 #include "exynosautov9-pinctrl.dtsi"
