0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos850 SoC device tree source
0004 *
0005 * Copyright (C) 2018 Samsung Electronics Co., Ltd.
0006 * Copyright (C) 2021 Linaro Ltd.
0007 *
0008 * Samsung Exynos850 SoC device nodes are listed in this file.
0009 * Exynos850 based board files can include this file and provide
0010 * values for board specific bindings.
0011 */
0012
0013 #include <dt-bindings/clock/exynos850.h>
0014 #include <dt-bindings/interrupt-controller/arm-gic.h>
0015 #include <dt-bindings/soc/samsung,exynos-usi.h>
0016
0017 / {
0018 /* Also known under engineering name Exynos3830 */
0019 compatible = "samsung,exynos850";
0020 #address-cells = <2>;
0021 #size-cells = <1>;
0022
0023 interrupt-parent = <&gic>;
0024
0025 aliases {
0026 pinctrl0 = &pinctrl_alive;
0027 pinctrl1 = &pinctrl_cmgp;
0028 pinctrl2 = &pinctrl_aud;
0029 pinctrl3 = &pinctrl_hsi;
0030 pinctrl4 = &pinctrl_core;
0031 pinctrl5 = &pinctrl_peri;
0032 };
0033
0034 arm-pmu {
0035 compatible = "arm,cortex-a55-pmu";
0036 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0037 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0038 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0039 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0040 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0041 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0042 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0043 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0044 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
0045 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0046 };
0047
0048 /* Main system clock (XTCXO); external, must be 26 MHz */
0049 oscclk: clock-oscclk {
0050 compatible = "fixed-clock";
0051 clock-output-names = "oscclk";
0052 #clock-cells = <0>;
0053 };
0054
0055 cpus {
0056 #address-cells = <1>;
0057 #size-cells = <0>;
0058
0059 cpu-map {
0060 cluster0 {
0061 core0 {
0062 cpu = <&cpu0>;
0063 };
0064 core1 {
0065 cpu = <&cpu1>;
0066 };
0067 core2 {
0068 cpu = <&cpu2>;
0069 };
0070 core3 {
0071 cpu = <&cpu3>;
0072 };
0073 };
0074
0075 cluster1 {
0076 core0 {
0077 cpu = <&cpu4>;
0078 };
0079 core1 {
0080 cpu = <&cpu5>;
0081 };
0082 core2 {
0083 cpu = <&cpu6>;
0084 };
0085 core3 {
0086 cpu = <&cpu7>;
0087 };
0088 };
0089 };
0090
0091 cpu0: cpu@0 {
0092 device_type = "cpu";
0093 compatible = "arm,cortex-a55";
0094 reg = <0x0>;
0095 enable-method = "psci";
0096 };
0097 cpu1: cpu@1 {
0098 device_type = "cpu";
0099 compatible = "arm,cortex-a55";
0100 reg = <0x1>;
0101 enable-method = "psci";
0102 };
0103 cpu2: cpu@2 {
0104 device_type = "cpu";
0105 compatible = "arm,cortex-a55";
0106 reg = <0x2>;
0107 enable-method = "psci";
0108 };
0109 cpu3: cpu@3 {
0110 device_type = "cpu";
0111 compatible = "arm,cortex-a55";
0112 reg = <0x3>;
0113 enable-method = "psci";
0114 };
0115 cpu4: cpu@100 {
0116 device_type = "cpu";
0117 compatible = "arm,cortex-a55";
0118 reg = <0x100>;
0119 enable-method = "psci";
0120 };
0121 cpu5: cpu@101 {
0122 device_type = "cpu";
0123 compatible = "arm,cortex-a55";
0124 reg = <0x101>;
0125 enable-method = "psci";
0126 };
0127 cpu6: cpu@102 {
0128 device_type = "cpu";
0129 compatible = "arm,cortex-a55";
0130 reg = <0x102>;
0131 enable-method = "psci";
0132 };
0133 cpu7: cpu@103 {
0134 device_type = "cpu";
0135 compatible = "arm,cortex-a55";
0136 reg = <0x103>;
0137 enable-method = "psci";
0138 };
0139 };
0140
0141 psci {
0142 compatible = "arm,psci-1.0";
0143 method = "smc";
0144 };
0145
0146 timer {
0147 compatible = "arm,armv8-timer";
0148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
0149 interrupts =
0150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0154 };
0155
0156 soc: soc@0 {
0157 compatible = "simple-bus";
0158 #address-cells = <1>;
0159 #size-cells = <1>;
0160 ranges = <0x0 0x0 0x0 0x20000000>;
0161
0162 chipid@10000000 {
0163 compatible = "samsung,exynos850-chipid";
0164 reg = <0x10000000 0x100>;
0165 };
0166
0167 timer@10040000 {
0168 compatible = "samsung,exynos850-mct",
0169 "samsung,exynos4210-mct";
0170 reg = <0x10040000 0x800>;
0171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
0178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
0183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
0184 clock-names = "fin_pll", "mct";
0185 };
0186
0187 gic: interrupt-controller@12a01000 {
0188 compatible = "arm,gic-400";
0189 #interrupt-cells = <3>;
0190 #address-cells = <0>;
0191 reg = <0x12a01000 0x1000>,
0192 <0x12a02000 0x2000>,
0193 <0x12a04000 0x2000>,
0194 <0x12a06000 0x2000>;
0195 interrupt-controller;
0196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
0197 IRQ_TYPE_LEVEL_HIGH)>;
0198 };
0199
0200 pmu_system_controller: system-controller@11860000 {
0201 compatible = "samsung,exynos850-pmu", "syscon";
0202 reg = <0x11860000 0x10000>;
0203 clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>;
0204
0205 reboot: syscon-reboot {
0206 compatible = "syscon-reboot";
0207 regmap = <&pmu_system_controller>;
0208 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
0209 mask = <0x2>; /* SWRESET_SYSTEM */
0210 value = <0x2>; /* reset value */
0211 };
0212 };
0213
0214 watchdog_cl0: watchdog@10050000 {
0215 compatible = "samsung,exynos850-wdt";
0216 reg = <0x10050000 0x100>;
0217 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
0219 clock-names = "watchdog", "watchdog_src";
0220 samsung,syscon-phandle = <&pmu_system_controller>;
0221 samsung,cluster-index = <0>;
0222 status = "disabled";
0223 };
0224
0225 watchdog_cl1: watchdog@10060000 {
0226 compatible = "samsung,exynos850-wdt";
0227 reg = <0x10060000 0x100>;
0228 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
0229 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
0230 clock-names = "watchdog", "watchdog_src";
0231 samsung,syscon-phandle = <&pmu_system_controller>;
0232 samsung,cluster-index = <1>;
0233 status = "disabled";
0234 };
0235
0236 cmu_peri: clock-controller@10030000 {
0237 compatible = "samsung,exynos850-cmu-peri";
0238 reg = <0x10030000 0x8000>;
0239 #clock-cells = <1>;
0240
0241 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
0242 <&cmu_top CLK_DOUT_PERI_UART>,
0243 <&cmu_top CLK_DOUT_PERI_IP>;
0244 clock-names = "oscclk", "dout_peri_bus",
0245 "dout_peri_uart", "dout_peri_ip";
0246 };
0247
0248 cmu_apm: clock-controller@11800000 {
0249 compatible = "samsung,exynos850-cmu-apm";
0250 reg = <0x11800000 0x8000>;
0251 #clock-cells = <1>;
0252
0253 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
0254 clock-names = "oscclk", "dout_clkcmu_apm_bus";
0255 };
0256
0257 cmu_cmgp: clock-controller@11c00000 {
0258 compatible = "samsung,exynos850-cmu-cmgp";
0259 reg = <0x11c00000 0x8000>;
0260 #clock-cells = <1>;
0261
0262 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
0263 clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
0264 };
0265
0266 cmu_core: clock-controller@12000000 {
0267 compatible = "samsung,exynos850-cmu-core";
0268 reg = <0x12000000 0x8000>;
0269 #clock-cells = <1>;
0270
0271 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
0272 <&cmu_top CLK_DOUT_CORE_CCI>,
0273 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
0274 <&cmu_top CLK_DOUT_CORE_SSS>;
0275 clock-names = "oscclk", "dout_core_bus",
0276 "dout_core_cci", "dout_core_mmc_embd",
0277 "dout_core_sss";
0278 };
0279
0280 cmu_top: clock-controller@120e0000 {
0281 compatible = "samsung,exynos850-cmu-top";
0282 reg = <0x120e0000 0x8000>;
0283 #clock-cells = <1>;
0284
0285 clocks = <&oscclk>;
0286 clock-names = "oscclk";
0287 };
0288
0289 cmu_dpu: clock-controller@13000000 {
0290 compatible = "samsung,exynos850-cmu-dpu";
0291 reg = <0x13000000 0x8000>;
0292 #clock-cells = <1>;
0293
0294 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
0295 clock-names = "oscclk", "dout_dpu";
0296 };
0297
0298 cmu_hsi: clock-controller@13400000 {
0299 compatible = "samsung,exynos850-cmu-hsi";
0300 reg = <0x13400000 0x8000>;
0301 #clock-cells = <1>;
0302
0303 clocks = <&oscclk>,
0304 <&cmu_top CLK_DOUT_HSI_BUS>,
0305 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
0306 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
0307 clock-names = "oscclk", "dout_hsi_bus",
0308 "dout_hsi_mmc_card", "dout_hsi_usb20drd";
0309 };
0310
0311 pinctrl_alive: pinctrl@11850000 {
0312 compatible = "samsung,exynos850-pinctrl";
0313 reg = <0x11850000 0x1000>;
0314
0315 wakeup-interrupt-controller {
0316 compatible = "samsung,exynos850-wakeup-eint";
0317 };
0318 };
0319
0320 pinctrl_cmgp: pinctrl@11c30000 {
0321 compatible = "samsung,exynos850-pinctrl";
0322 reg = <0x11c30000 0x1000>;
0323
0324 wakeup-interrupt-controller {
0325 compatible = "samsung,exynos850-wakeup-eint";
0326 };
0327 };
0328
0329 pinctrl_core: pinctrl@12070000 {
0330 compatible = "samsung,exynos850-pinctrl";
0331 reg = <0x12070000 0x1000>;
0332 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
0333 };
0334
0335 pinctrl_hsi: pinctrl@13430000 {
0336 compatible = "samsung,exynos850-pinctrl";
0337 reg = <0x13430000 0x1000>;
0338 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0339 };
0340
0341 pinctrl_peri: pinctrl@139b0000 {
0342 compatible = "samsung,exynos850-pinctrl";
0343 reg = <0x139b0000 0x1000>;
0344 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0345 };
0346
0347 pinctrl_aud: pinctrl@14a60000 {
0348 compatible = "samsung,exynos850-pinctrl";
0349 reg = <0x14a60000 0x1000>;
0350 };
0351
0352 rtc: rtc@11a30000 {
0353 compatible = "samsung,s3c6410-rtc";
0354 reg = <0x11a30000 0x100>;
0355 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0356 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0357 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
0358 clock-names = "rtc";
0359 status = "disabled";
0360 };
0361
0362 mmc_0: mmc@12100000 {
0363 compatible = "samsung,exynos7-dw-mshc-smu";
0364 reg = <0x12100000 0x2000>;
0365 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
0366 #address-cells = <1>;
0367 #size-cells = <0>;
0368 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
0369 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
0370 clock-names = "biu", "ciu";
0371 fifo-depth = <0x40>;
0372 status = "disabled";
0373 };
0374
0375 i2c_0: i2c@13830000 {
0376 compatible = "samsung,s3c2440-i2c";
0377 reg = <0x13830000 0x100>;
0378 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0379 #address-cells = <1>;
0380 #size-cells = <0>;
0381 pinctrl-names = "default";
0382 pinctrl-0 = <&i2c0_pins>;
0383 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
0384 clock-names = "i2c";
0385 status = "disabled";
0386 };
0387
0388 i2c_1: i2c@13840000 {
0389 compatible = "samsung,s3c2440-i2c";
0390 reg = <0x13840000 0x100>;
0391 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0392 #address-cells = <1>;
0393 #size-cells = <0>;
0394 pinctrl-names = "default";
0395 pinctrl-0 = <&i2c1_pins>;
0396 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
0397 clock-names = "i2c";
0398 status = "disabled";
0399 };
0400
0401 i2c_2: i2c@13850000 {
0402 compatible = "samsung,s3c2440-i2c";
0403 reg = <0x13850000 0x100>;
0404 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 pinctrl-names = "default";
0408 pinctrl-0 = <&i2c2_pins>;
0409 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
0410 clock-names = "i2c";
0411 status = "disabled";
0412 };
0413
0414 i2c_3: i2c@13860000 {
0415 compatible = "samsung,s3c2440-i2c";
0416 reg = <0x13860000 0x100>;
0417 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420 pinctrl-names = "default";
0421 pinctrl-0 = <&i2c3_pins>;
0422 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
0423 clock-names = "i2c";
0424 status = "disabled";
0425 };
0426
0427 i2c_4: i2c@13870000 {
0428 compatible = "samsung,s3c2440-i2c";
0429 reg = <0x13870000 0x100>;
0430 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0431 #address-cells = <1>;
0432 #size-cells = <0>;
0433 pinctrl-names = "default";
0434 pinctrl-0 = <&i2c4_pins>;
0435 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
0436 clock-names = "i2c";
0437 status = "disabled";
0438 };
0439
0440 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
0441 i2c_5: i2c@13880000 {
0442 compatible = "samsung,s3c2440-i2c";
0443 reg = <0x13880000 0x100>;
0444 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0445 #address-cells = <1>;
0446 #size-cells = <0>;
0447 pinctrl-names = "default";
0448 pinctrl-0 = <&i2c5_pins>;
0449 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
0450 clock-names = "i2c";
0451 status = "disabled";
0452 };
0453
0454 /* I2C_6 (also called MOTOR_I2C in TRM) */
0455 i2c_6: i2c@13890000 {
0456 compatible = "samsung,s3c2440-i2c";
0457 reg = <0x13890000 0x100>;
0458 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0459 #address-cells = <1>;
0460 #size-cells = <0>;
0461 pinctrl-names = "default";
0462 pinctrl-0 = <&i2c6_pins>;
0463 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
0464 clock-names = "i2c";
0465 status = "disabled";
0466 };
0467
0468 sysreg_peri: syscon@10020000 {
0469 compatible = "samsung,exynos850-sysreg", "syscon";
0470 reg = <0x10020000 0x10000>;
0471 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
0472 };
0473
0474 sysreg_cmgp: syscon@11c20000 {
0475 compatible = "samsung,exynos850-sysreg", "syscon";
0476 reg = <0x11c20000 0x10000>;
0477 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
0478 };
0479
0480 usi_uart: usi@138200c0 {
0481 compatible = "samsung,exynos850-usi";
0482 reg = <0x138200c0 0x20>;
0483 samsung,sysreg = <&sysreg_peri 0x1010>;
0484 samsung,mode = <USI_V2_UART>;
0485 #address-cells = <1>;
0486 #size-cells = <1>;
0487 ranges;
0488 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
0489 <&cmu_peri CLK_GOUT_UART_IPCLK>;
0490 clock-names = "pclk", "ipclk";
0491 status = "disabled";
0492
0493 serial_0: serial@13820000 {
0494 compatible = "samsung,exynos850-uart";
0495 reg = <0x13820000 0xc0>;
0496 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0497 pinctrl-names = "default";
0498 pinctrl-0 = <&uart0_pins>;
0499 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
0500 <&cmu_peri CLK_GOUT_UART_IPCLK>;
0501 clock-names = "uart", "clk_uart_baud0";
0502 status = "disabled";
0503 };
0504 };
0505
0506 usi_hsi2c_0: usi@138a00c0 {
0507 compatible = "samsung,exynos850-usi";
0508 reg = <0x138a00c0 0x20>;
0509 samsung,sysreg = <&sysreg_peri 0x1020>;
0510 samsung,mode = <USI_V2_I2C>;
0511 #address-cells = <1>;
0512 #size-cells = <1>;
0513 ranges;
0514 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
0515 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
0516 clock-names = "pclk", "ipclk";
0517 status = "disabled";
0518
0519 hsi2c_0: i2c@138a0000 {
0520 compatible = "samsung,exynosautov9-hsi2c";
0521 reg = <0x138a0000 0xc0>;
0522 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0523 #address-cells = <1>;
0524 #size-cells = <0>;
0525 pinctrl-names = "default";
0526 pinctrl-0 = <&hsi2c0_pins>;
0527 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
0528 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
0529 clock-names = "hsi2c", "hsi2c_pclk";
0530 status = "disabled";
0531 };
0532 };
0533
0534 usi_hsi2c_1: usi@138b00c0 {
0535 compatible = "samsung,exynos850-usi";
0536 reg = <0x138b00c0 0x20>;
0537 samsung,sysreg = <&sysreg_peri 0x1030>;
0538 samsung,mode = <USI_V2_I2C>;
0539 #address-cells = <1>;
0540 #size-cells = <1>;
0541 ranges;
0542 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
0543 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
0544 clock-names = "pclk", "ipclk";
0545 status = "disabled";
0546
0547 hsi2c_1: i2c@138b0000 {
0548 compatible = "samsung,exynosautov9-hsi2c";
0549 reg = <0x138b0000 0xc0>;
0550 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0551 #address-cells = <1>;
0552 #size-cells = <0>;
0553 pinctrl-names = "default";
0554 pinctrl-0 = <&hsi2c1_pins>;
0555 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
0556 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
0557 clock-names = "hsi2c", "hsi2c_pclk";
0558 status = "disabled";
0559 };
0560 };
0561
0562 usi_hsi2c_2: usi@138c00c0 {
0563 compatible = "samsung,exynos850-usi";
0564 reg = <0x138c00c0 0x20>;
0565 samsung,sysreg = <&sysreg_peri 0x1040>;
0566 samsung,mode = <USI_V2_I2C>;
0567 #address-cells = <1>;
0568 #size-cells = <1>;
0569 ranges;
0570 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
0571 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
0572 clock-names = "pclk", "ipclk";
0573 status = "disabled";
0574
0575 hsi2c_2: i2c@138c0000 {
0576 compatible = "samsung,exynosautov9-hsi2c";
0577 reg = <0x138c0000 0xc0>;
0578 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0579 #address-cells = <1>;
0580 #size-cells = <0>;
0581 pinctrl-names = "default";
0582 pinctrl-0 = <&hsi2c2_pins>;
0583 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
0584 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
0585 clock-names = "hsi2c", "hsi2c_pclk";
0586 status = "disabled";
0587 };
0588 };
0589
0590 usi_spi_0: usi@139400c0 {
0591 compatible = "samsung,exynos850-usi";
0592 reg = <0x139400c0 0x20>;
0593 samsung,sysreg = <&sysreg_peri 0x1050>;
0594 samsung,mode = <USI_V2_SPI>;
0595 #address-cells = <1>;
0596 #size-cells = <1>;
0597 ranges;
0598 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
0599 <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
0600 clock-names = "pclk", "ipclk";
0601 status = "disabled";
0602 };
0603
0604 usi_cmgp0: usi@11d000c0 {
0605 compatible = "samsung,exynos850-usi";
0606 reg = <0x11d000c0 0x20>;
0607 samsung,sysreg = <&sysreg_cmgp 0x2000>;
0608 samsung,mode = <USI_V2_I2C>;
0609 #address-cells = <1>;
0610 #size-cells = <1>;
0611 ranges;
0612 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
0613 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
0614 clock-names = "pclk", "ipclk";
0615 status = "disabled";
0616
0617 hsi2c_3: i2c@11d00000 {
0618 compatible = "samsung,exynosautov9-hsi2c";
0619 reg = <0x11d00000 0xc0>;
0620 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0621 #address-cells = <1>;
0622 #size-cells = <0>;
0623 pinctrl-names = "default";
0624 pinctrl-0 = <&hsi2c3_pins>;
0625 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
0626 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
0627 clock-names = "hsi2c", "hsi2c_pclk";
0628 status = "disabled";
0629 };
0630
0631 serial_1: serial@11d00000 {
0632 compatible = "samsung,exynos850-uart";
0633 reg = <0x11d00000 0xc0>;
0634 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0635 pinctrl-names = "default";
0636 pinctrl-0 = <&uart1_single_pins>;
0637 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
0638 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
0639 clock-names = "uart", "clk_uart_baud0";
0640 status = "disabled";
0641 };
0642 };
0643
0644 usi_cmgp1: usi@11d200c0 {
0645 compatible = "samsung,exynos850-usi";
0646 reg = <0x11d200c0 0x20>;
0647 samsung,sysreg = <&sysreg_cmgp 0x2010>;
0648 samsung,mode = <USI_V2_I2C>;
0649 #address-cells = <1>;
0650 #size-cells = <1>;
0651 ranges;
0652 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
0653 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
0654 clock-names = "pclk", "ipclk";
0655 status = "disabled";
0656
0657 hsi2c_4: i2c@11d20000 {
0658 compatible = "samsung,exynosautov9-hsi2c";
0659 reg = <0x11d20000 0xc0>;
0660 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0661 #address-cells = <1>;
0662 #size-cells = <0>;
0663 pinctrl-names = "default";
0664 pinctrl-0 = <&hsi2c4_pins>;
0665 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
0666 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
0667 clock-names = "hsi2c", "hsi2c_pclk";
0668 status = "disabled";
0669 };
0670
0671 serial_2: serial@11d20000 {
0672 compatible = "samsung,exynos850-uart";
0673 reg = <0x11d20000 0xc0>;
0674 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0675 pinctrl-names = "default";
0676 pinctrl-0 = <&uart2_single_pins>;
0677 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
0678 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
0679 clock-names = "uart", "clk_uart_baud0";
0680 status = "disabled";
0681 };
0682 };
0683 };
0684 };
0685
0686 #include "exynos850-pinctrl.dtsi"
