0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos7885 SoC device tree source
0004 *
0005 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
0006 * Copyright (c) 2021 Dávid Virág
0007 */
0008
0009 #include <dt-bindings/clock/exynos7885.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 / {
0013 compatible = "samsung,exynos7885";
0014 #address-cells = <2>;
0015 #size-cells = <1>;
0016
0017 interrupt-parent = <&gic>;
0018
0019 aliases {
0020 pinctrl0 = &pinctrl_alive;
0021 pinctrl1 = &pinctrl_dispaud;
0022 pinctrl2 = &pinctrl_fsys;
0023 pinctrl3 = &pinctrl_top;
0024 };
0025
0026 arm-a53-pmu {
0027 compatible = "arm,cortex-a53-pmu";
0028 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0029 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0030 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0031 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0032 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0033 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
0034 interrupt-affinity = <&cpu0>,
0035 <&cpu1>,
0036 <&cpu2>,
0037 <&cpu3>,
0038 <&cpu4>,
0039 <&cpu5>;
0040 };
0041
0042 arm-a73-pmu {
0043 compatible = "arm,cortex-a73-pmu";
0044 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0045 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0046 interrupt-affinity = <&cpu6>,
0047 <&cpu7>;
0048 };
0049
0050 cpus {
0051 #address-cells = <1>;
0052 #size-cells = <0>;
0053
0054 cpu-map {
0055 cluster0 {
0056 core0 {
0057 cpu = <&cpu0>;
0058 };
0059 core1 {
0060 cpu = <&cpu1>;
0061 };
0062 core2 {
0063 cpu = <&cpu2>;
0064 };
0065 core3 {
0066 cpu = <&cpu3>;
0067 };
0068 core4 {
0069 cpu = <&cpu4>;
0070 };
0071 core5 {
0072 cpu = <&cpu5>;
0073 };
0074 };
0075
0076 cluster1 {
0077 core0 {
0078 cpu = <&cpu6>;
0079 };
0080 core1 {
0081 cpu = <&cpu7>;
0082 };
0083 };
0084 };
0085
0086 cpu0: cpu@100 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a53";
0089 reg = <0x100>;
0090 enable-method = "psci";
0091 };
0092
0093 cpu1: cpu@101 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a53";
0096 reg = <0x101>;
0097 enable-method = "psci";
0098 };
0099
0100 cpu2: cpu@102 {
0101 device_type = "cpu";
0102 compatible = "arm,cortex-a53";
0103 reg = <0x102>;
0104 enable-method = "psci";
0105 };
0106
0107 cpu3: cpu@103 {
0108 device_type = "cpu";
0109 compatible = "arm,cortex-a53";
0110 reg = <0x103>;
0111 enable-method = "psci";
0112 };
0113
0114 cpu4: cpu@200 {
0115 device_type = "cpu";
0116 compatible = "arm,cortex-a53";
0117 reg = <0x200>;
0118 enable-method = "psci";
0119 };
0120
0121 cpu5: cpu@201 {
0122 device_type = "cpu";
0123 compatible = "arm,cortex-a53";
0124 reg = <0x201>;
0125 enable-method = "psci";
0126 };
0127
0128 cpu6: cpu@0 {
0129 device_type = "cpu";
0130 compatible = "arm,cortex-a73";
0131 reg = <0x0>;
0132 enable-method = "psci";
0133 };
0134
0135 cpu7: cpu@1 {
0136 device_type = "cpu";
0137 compatible = "arm,cortex-a73";
0138 reg = <0x1>;
0139 enable-method = "psci";
0140 };
0141 };
0142
0143 psci {
0144 compatible = "arm,psci";
0145 method = "smc";
0146 cpu_suspend = <0xc4000001>;
0147 cpu_off = <0x84000002>;
0148 cpu_on = <0xc4000003>;
0149 };
0150
0151 timer {
0152 compatible = "arm,armv8-timer";
0153 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
0154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0158 };
0159
0160 fixed-rate-clocks {
0161 oscclk: osc-clock {
0162 compatible = "fixed-clock";
0163 #clock-cells = <0>;
0164 clock-output-names = "oscclk";
0165 };
0166 };
0167
0168 soc: soc@0 {
0169 compatible = "simple-bus";
0170 #address-cells = <1>;
0171 #size-cells = <1>;
0172 ranges = <0x0 0x0 0x0 0x20000000>;
0173
0174 chipid@10000000 {
0175 compatible = "samsung,exynos850-chipid";
0176 reg = <0x10000000 0x24>;
0177 };
0178
0179 gic: interrupt-controller@12301000 {
0180 compatible = "arm,gic-400";
0181 #interrupt-cells = <3>;
0182 #address-cells = <0>;
0183 interrupt-controller;
0184 reg = <0x12301000 0x1000>,
0185 <0x12302000 0x2000>,
0186 <0x12304000 0x2000>,
0187 <0x12306000 0x2000>;
0188 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
0189 IRQ_TYPE_LEVEL_HIGH)>;
0190 };
0191
0192 cmu_peri: clock-controller@10010000 {
0193 compatible = "samsung,exynos7885-cmu-peri";
0194 reg = <0x10010000 0x8000>;
0195 #clock-cells = <1>;
0196
0197 clocks = <&oscclk>,
0198 <&cmu_top CLK_DOUT_PERI_BUS>,
0199 <&cmu_top CLK_DOUT_PERI_SPI0>,
0200 <&cmu_top CLK_DOUT_PERI_SPI1>,
0201 <&cmu_top CLK_DOUT_PERI_UART0>,
0202 <&cmu_top CLK_DOUT_PERI_UART1>,
0203 <&cmu_top CLK_DOUT_PERI_UART2>,
0204 <&cmu_top CLK_DOUT_PERI_USI0>,
0205 <&cmu_top CLK_DOUT_PERI_USI1>,
0206 <&cmu_top CLK_DOUT_PERI_USI2>;
0207 clock-names = "oscclk",
0208 "dout_peri_bus",
0209 "dout_peri_spi0",
0210 "dout_peri_spi1",
0211 "dout_peri_uart0",
0212 "dout_peri_uart1",
0213 "dout_peri_uart2",
0214 "dout_peri_usi0",
0215 "dout_peri_usi1",
0216 "dout_peri_usi2";
0217 };
0218
0219 cmu_core: clock-controller@12000000 {
0220 compatible = "samsung,exynos7885-cmu-core";
0221 reg = <0x12000000 0x8000>;
0222 #clock-cells = <1>;
0223
0224 clocks = <&oscclk>,
0225 <&cmu_top CLK_DOUT_CORE_BUS>,
0226 <&cmu_top CLK_DOUT_CORE_CCI>,
0227 <&cmu_top CLK_DOUT_CORE_G3D>;
0228 clock-names = "oscclk",
0229 "dout_core_bus",
0230 "dout_core_cci",
0231 "dout_core_g3d";
0232 };
0233
0234 cmu_top: clock-controller@12060000 {
0235 compatible = "samsung,exynos7885-cmu-top";
0236 reg = <0x12060000 0x8000>;
0237 #clock-cells = <1>;
0238
0239 clocks = <&oscclk>;
0240 clock-names = "oscclk";
0241 };
0242
0243 cmu_fsys: clock-controller@13400000 {
0244 compatible = "samsung,exynos7885-cmu-fsys";
0245 reg = <0x13400000 0x8000>;
0246 #clock-cells = <1>;
0247
0248 clocks = <&oscclk>,
0249 <&cmu_top CLK_DOUT_FSYS_BUS>,
0250 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
0251 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
0252 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
0253 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
0254 clock-names = "oscclk",
0255 "dout_fsys_bus",
0256 "dout_fsys_mmc_card",
0257 "dout_fsys_mmc_embd",
0258 "dout_fsys_mmc_sdio",
0259 "dout_fsys_usb30drd";
0260 };
0261
0262 pinctrl_alive: pinctrl@11cb0000 {
0263 compatible = "samsung,exynos7885-pinctrl";
0264 reg = <0x11cb0000 0x1000>;
0265
0266 wakeup-interrupt-controller {
0267 compatible = "samsung,exynos7-wakeup-eint";
0268 interrupt-parent = <&gic>;
0269 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
0270 };
0271 };
0272
0273 pinctrl_fsys: pinctrl@13430000 {
0274 compatible = "samsung,exynos7885-pinctrl";
0275 reg = <0x13430000 0x1000>;
0276 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
0277 };
0278
0279 pinctrl_top: pinctrl@139b0000 {
0280 compatible = "samsung,exynos7885-pinctrl";
0281 reg = <0x139b0000 0x1000>;
0282 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
0283 };
0284
0285 pinctrl_dispaud: pinctrl@148f0000 {
0286 compatible = "samsung,exynos7885-pinctrl";
0287 reg = <0x148f0000 0x1000>;
0288 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
0289 };
0290
0291 pmu_system_controller: system-controller@11c80000 {
0292 compatible = "samsung,exynos7-pmu", "syscon";
0293 reg = <0x11c80000 0x10000>;
0294 };
0295
0296 mmc_0: mmc@13500000 {
0297 compatible = "samsung,exynos7-dw-mshc-smu";
0298 reg = <0x13500000 0x2000>;
0299 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0300 #address-cells = <1>;
0301 #size-cells = <0>;
0302 clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
0303 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
0304 clock-names = "biu", "ciu";
0305 fifo-depth = <0x40>;
0306 status = "disabled";
0307 };
0308
0309 serial_0: serial@13800000 {
0310 compatible = "samsung,exynos5433-uart";
0311 reg = <0x13800000 0x100>;
0312 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
0313 pinctrl-names = "default";
0314 pinctrl-0 = <&uart0_bus>;
0315 clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
0316 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
0317 clock-names = "uart", "clk_uart_baud0";
0318 samsung,uart-fifosize = <64>;
0319 status = "disabled";
0320 };
0321
0322 serial_1: serial@13810000 {
0323 compatible = "samsung,exynos5433-uart";
0324 reg = <0x13810000 0x100>;
0325 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
0326 pinctrl-names = "default";
0327 pinctrl-0 = <&uart1_bus>;
0328 clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
0329 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
0330 clock-names = "uart", "clk_uart_baud0";
0331 samsung,uart-fifosize = <256>;
0332 status = "disabled";
0333 };
0334
0335 serial_2: serial@13820000 {
0336 compatible = "samsung,exynos5433-uart";
0337 reg = <0x13820000 0x100>;
0338 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
0339 pinctrl-names = "default";
0340 pinctrl-0 = <&uart2_bus>;
0341 clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
0342 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
0343 clock-names = "uart", "clk_uart_baud0";
0344 samsung,uart-fifosize = <256>;
0345 status = "disabled";
0346 };
0347
0348 i2c_0: i2c@13830000 {
0349 compatible = "samsung,s3c2440-i2c";
0350 reg = <0x13830000 0x100>;
0351 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
0352 #address-cells = <1>;
0353 #size-cells = <0>;
0354 pinctrl-names = "default";
0355 pinctrl-0 = <&i2c0_bus>;
0356 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
0357 clock-names = "i2c";
0358 status = "disabled";
0359 };
0360
0361 i2c_1: i2c@13840000 {
0362 compatible = "samsung,s3c2440-i2c";
0363 reg = <0x13840000 0x100>;
0364 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0365 #address-cells = <1>;
0366 #size-cells = <0>;
0367 pinctrl-names = "default";
0368 pinctrl-0 = <&i2c1_bus>;
0369 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
0370 clock-names = "i2c";
0371 status = "disabled";
0372 };
0373
0374 i2c_2: i2c@13850000 {
0375 compatible = "samsung,s3c2440-i2c";
0376 reg = <0x13850000 0x100>;
0377 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
0378 #address-cells = <1>;
0379 #size-cells = <0>;
0380 pinctrl-names = "default";
0381 pinctrl-0 = <&i2c2_bus>;
0382 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
0383 clock-names = "i2c";
0384 status = "disabled";
0385 };
0386
0387 i2c_3: i2c@13860000 {
0388 compatible = "samsung,s3c2440-i2c";
0389 reg = <0x13860000 0x100>;
0390 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
0391 #address-cells = <1>;
0392 #size-cells = <0>;
0393 pinctrl-names = "default";
0394 pinctrl-0 = <&i2c3_bus>;
0395 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
0396 clock-names = "i2c";
0397 status = "disabled";
0398 };
0399
0400 i2c_4: i2c@13870000 {
0401 compatible = "samsung,s3c2440-i2c";
0402 reg = <0x13870000 0x100>;
0403 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406 pinctrl-names = "default";
0407 pinctrl-0 = <&i2c4_bus>;
0408 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
0409 clock-names = "i2c";
0410 status = "disabled";
0411 };
0412
0413 i2c_5: i2c@13880000 {
0414 compatible = "samsung,s3c2440-i2c";
0415 reg = <0x13880000 0x100>;
0416 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 pinctrl-names = "default";
0420 pinctrl-0 = <&i2c5_bus>;
0421 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
0422 clock-names = "i2c";
0423 status = "disabled";
0424 };
0425
0426 i2c_6: i2c@13890000 {
0427 compatible = "samsung,s3c2440-i2c";
0428 reg = <0x13890000 0x100>;
0429 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
0430 #address-cells = <1>;
0431 #size-cells = <0>;
0432 pinctrl-names = "default";
0433 pinctrl-0 = <&i2c6_bus>;
0434 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
0435 clock-names = "i2c";
0436 status = "disabled";
0437 };
0438
0439 i2c_7: i2c@11cd0000 {
0440 compatible = "samsung,s3c2440-i2c";
0441 reg = <0x11cd0000 0x100>;
0442 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
0443 #address-cells = <1>;
0444 #size-cells = <0>;
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&i2c7_bus>;
0447 clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
0448 clock-names = "i2c";
0449 status = "disabled";
0450 };
0451 };
0452 };
0453
0454 #include "exynos7885-pinctrl.dtsi"
0455 #include "arm/exynos-syscon-restart.dtsi"
