0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung Exynos7 SoC device tree source
0004 *
0005 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0006 * http://www.samsung.com
0007 */
0008
0009 #include <dt-bindings/clock/exynos7-clk.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 / {
0013 compatible = "samsung,exynos7";
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 aliases {
0019 pinctrl0 = &pinctrl_alive;
0020 pinctrl1 = &pinctrl_bus0;
0021 pinctrl2 = &pinctrl_nfc;
0022 pinctrl3 = &pinctrl_touch;
0023 pinctrl4 = &pinctrl_ff;
0024 pinctrl5 = &pinctrl_ese;
0025 pinctrl6 = &pinctrl_fsys0;
0026 pinctrl7 = &pinctrl_fsys1;
0027 pinctrl8 = &pinctrl_bus1;
0028 tmuctrl0 = &tmuctrl_0;
0029 };
0030
0031 arm-pmu {
0032 compatible = "arm,cortex-a57-pmu";
0033 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0034 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0035 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0036 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0037 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
0038 <&cpu_atlas2>, <&cpu_atlas3>;
0039 };
0040
0041 fin_pll: clock {
0042 /* XXTI */
0043 compatible = "fixed-clock";
0044 clock-output-names = "fin_pll";
0045 #clock-cells = <0>;
0046 };
0047
0048 cpus {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 cpu_atlas0: cpu@0 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a57";
0055 reg = <0x0>;
0056 enable-method = "psci";
0057 i-cache-size = <0xc000>;
0058 i-cache-line-size = <64>;
0059 i-cache-sets = <256>;
0060 d-cache-size = <0x8000>;
0061 d-cache-line-size = <64>;
0062 d-cache-sets = <256>;
0063 next-level-cache = <&atlas_l2>;
0064 };
0065
0066 cpu_atlas1: cpu@1 {
0067 device_type = "cpu";
0068 compatible = "arm,cortex-a57";
0069 reg = <0x1>;
0070 enable-method = "psci";
0071 i-cache-size = <0xc000>;
0072 i-cache-line-size = <64>;
0073 i-cache-sets = <256>;
0074 d-cache-size = <0x8000>;
0075 d-cache-line-size = <64>;
0076 d-cache-sets = <256>;
0077 next-level-cache = <&atlas_l2>;
0078 };
0079
0080 cpu_atlas2: cpu@2 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a57";
0083 reg = <0x2>;
0084 enable-method = "psci";
0085 i-cache-size = <0xc000>;
0086 i-cache-line-size = <64>;
0087 i-cache-sets = <256>;
0088 d-cache-size = <0x8000>;
0089 d-cache-line-size = <64>;
0090 d-cache-sets = <256>;
0091 next-level-cache = <&atlas_l2>;
0092 };
0093
0094 cpu_atlas3: cpu@3 {
0095 device_type = "cpu";
0096 compatible = "arm,cortex-a57";
0097 reg = <0x3>;
0098 enable-method = "psci";
0099 i-cache-size = <0xc000>;
0100 i-cache-line-size = <64>;
0101 i-cache-sets = <256>;
0102 d-cache-size = <0x8000>;
0103 d-cache-line-size = <64>;
0104 d-cache-sets = <256>;
0105 next-level-cache = <&atlas_l2>;
0106 };
0107
0108 atlas_l2: l2-cache0 {
0109 compatible = "cache";
0110 cache-size = <0x200000>;
0111 cache-line-size = <64>;
0112 cache-sets = <2048>;
0113 };
0114 };
0115
0116 psci {
0117 compatible = "arm,psci";
0118 method = "smc";
0119 cpu_off = <0x84000002>;
0120 cpu_on = <0xC4000003>;
0121 };
0122
0123 soc: soc@0 {
0124 compatible = "simple-bus";
0125 #address-cells = <1>;
0126 #size-cells = <1>;
0127 ranges = <0 0 0 0x18000000>;
0128
0129 chipid@10000000 {
0130 compatible = "samsung,exynos4210-chipid";
0131 reg = <0x10000000 0x100>;
0132 };
0133
0134 gic: interrupt-controller@11001000 {
0135 compatible = "arm,gic-400";
0136 #interrupt-cells = <3>;
0137 #address-cells = <0>;
0138 interrupt-controller;
0139 reg = <0x11001000 0x1000>,
0140 <0x11002000 0x2000>,
0141 <0x11004000 0x2000>,
0142 <0x11006000 0x2000>;
0143 };
0144
0145 pdma0: dma-controller@10e10000 {
0146 compatible = "arm,pl330", "arm,primecell";
0147 reg = <0x10E10000 0x1000>;
0148 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
0149 clocks = <&clock_fsys0 ACLK_PDMA0>;
0150 clock-names = "apb_pclk";
0151 #dma-cells = <1>;
0152 };
0153
0154 pdma1: dma-controller@10eb0000 {
0155 compatible = "arm,pl330", "arm,primecell";
0156 reg = <0x10EB0000 0x1000>;
0157 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
0158 clocks = <&clock_fsys0 ACLK_PDMA1>;
0159 clock-names = "apb_pclk";
0160 #dma-cells = <1>;
0161 };
0162
0163 clock_topc: clock-controller@10570000 {
0164 compatible = "samsung,exynos7-clock-topc";
0165 reg = <0x10570000 0x10000>;
0166 #clock-cells = <1>;
0167 };
0168
0169 clock_top0: clock-controller@105d0000 {
0170 compatible = "samsung,exynos7-clock-top0";
0171 reg = <0x105d0000 0xb000>;
0172 #clock-cells = <1>;
0173 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
0174 <&clock_topc DOUT_SCLK_BUS1_PLL>,
0175 <&clock_topc DOUT_SCLK_CC_PLL>,
0176 <&clock_topc DOUT_SCLK_MFC_PLL>,
0177 <&clock_topc DOUT_SCLK_AUD_PLL>;
0178 clock-names = "fin_pll", "dout_sclk_bus0_pll",
0179 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
0180 "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
0181 };
0182
0183 clock_top1: clock-controller@105e0000 {
0184 compatible = "samsung,exynos7-clock-top1";
0185 reg = <0x105e0000 0xb000>;
0186 #clock-cells = <1>;
0187 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
0188 <&clock_topc DOUT_SCLK_BUS1_PLL>,
0189 <&clock_topc DOUT_SCLK_CC_PLL>,
0190 <&clock_topc DOUT_SCLK_MFC_PLL>;
0191 clock-names = "fin_pll", "dout_sclk_bus0_pll",
0192 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
0193 "dout_sclk_mfc_pll";
0194 };
0195
0196 clock_ccore: clock-controller@105b0000 {
0197 compatible = "samsung,exynos7-clock-ccore";
0198 reg = <0x105b0000 0xd00>;
0199 #clock-cells = <1>;
0200 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
0201 clock-names = "fin_pll", "dout_aclk_ccore_133";
0202 };
0203
0204 clock_peric0: clock-controller@13610000 {
0205 compatible = "samsung,exynos7-clock-peric0";
0206 reg = <0x13610000 0xd00>;
0207 #clock-cells = <1>;
0208 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
0209 <&clock_top0 CLK_SCLK_UART0>;
0210 clock-names = "fin_pll", "dout_aclk_peric0_66",
0211 "sclk_uart0";
0212 };
0213
0214 clock_peric1: clock-controller@14c80000 {
0215 compatible = "samsung,exynos7-clock-peric1";
0216 reg = <0x14c80000 0xd00>;
0217 #clock-cells = <1>;
0218 clocks = <&fin_pll>,
0219 <&clock_top0 DOUT_ACLK_PERIC1>,
0220 <&clock_top0 CLK_SCLK_UART1>,
0221 <&clock_top0 CLK_SCLK_UART2>,
0222 <&clock_top0 CLK_SCLK_UART3>,
0223 <&clock_top0 CLK_SCLK_SPI0>,
0224 <&clock_top0 CLK_SCLK_SPI1>,
0225 <&clock_top0 CLK_SCLK_SPI2>,
0226 <&clock_top0 CLK_SCLK_SPI3>,
0227 <&clock_top0 CLK_SCLK_SPI4>,
0228 <&clock_top0 CLK_SCLK_I2S1>,
0229 <&clock_top0 CLK_SCLK_PCM1>,
0230 <&clock_top0 CLK_SCLK_SPDIF>;
0231 clock-names = "fin_pll",
0232 "dout_aclk_peric1_66",
0233 "sclk_uart1",
0234 "sclk_uart2",
0235 "sclk_uart3",
0236 "sclk_spi0",
0237 "sclk_spi1",
0238 "sclk_spi2",
0239 "sclk_spi3",
0240 "sclk_spi4",
0241 "sclk_i2s1",
0242 "sclk_pcm1",
0243 "sclk_spdif";
0244 };
0245
0246 clock_peris: clock-controller@10040000 {
0247 compatible = "samsung,exynos7-clock-peris";
0248 reg = <0x10040000 0xd00>;
0249 #clock-cells = <1>;
0250 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
0251 clock-names = "fin_pll", "dout_aclk_peris_66";
0252 };
0253
0254 clock_fsys0: clock-controller@10e90000 {
0255 compatible = "samsung,exynos7-clock-fsys0";
0256 reg = <0x10e90000 0xd00>;
0257 #clock-cells = <1>;
0258 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
0259 <&clock_top1 DOUT_SCLK_MMC2>;
0260 clock-names = "fin_pll", "dout_aclk_fsys0_200",
0261 "dout_sclk_mmc2";
0262 };
0263
0264 clock_fsys1: clock-controller@156e0000 {
0265 compatible = "samsung,exynos7-clock-fsys1";
0266 reg = <0x156e0000 0xd00>;
0267 #clock-cells = <1>;
0268 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
0269 <&clock_top1 DOUT_SCLK_MMC0>,
0270 <&clock_top1 DOUT_SCLK_MMC1>,
0271 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
0272 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
0273 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
0274 clock-names = "fin_pll", "dout_aclk_fsys1_200",
0275 "dout_sclk_mmc0", "dout_sclk_mmc1",
0276 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
0277 "dout_sclk_phy_fsys1_26m";
0278 };
0279
0280 serial_0: serial@13630000 {
0281 compatible = "samsung,exynos4210-uart";
0282 reg = <0x13630000 0x100>;
0283 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
0284 clocks = <&clock_peric0 PCLK_UART0>,
0285 <&clock_peric0 SCLK_UART0>;
0286 clock-names = "uart", "clk_uart_baud0";
0287 status = "disabled";
0288 };
0289
0290 serial_1: serial@14c20000 {
0291 compatible = "samsung,exynos4210-uart";
0292 reg = <0x14c20000 0x100>;
0293 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
0294 clocks = <&clock_peric1 PCLK_UART1>,
0295 <&clock_peric1 SCLK_UART1>;
0296 clock-names = "uart", "clk_uart_baud0";
0297 status = "disabled";
0298 };
0299
0300 serial_2: serial@14c30000 {
0301 compatible = "samsung,exynos4210-uart";
0302 reg = <0x14c30000 0x100>;
0303 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
0304 clocks = <&clock_peric1 PCLK_UART2>,
0305 <&clock_peric1 SCLK_UART2>;
0306 clock-names = "uart", "clk_uart_baud0";
0307 status = "disabled";
0308 };
0309
0310 serial_3: serial@14c40000 {
0311 compatible = "samsung,exynos4210-uart";
0312 reg = <0x14c40000 0x100>;
0313 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
0314 clocks = <&clock_peric1 PCLK_UART3>,
0315 <&clock_peric1 SCLK_UART3>;
0316 clock-names = "uart", "clk_uart_baud0";
0317 status = "disabled";
0318 };
0319
0320 pinctrl_alive: pinctrl@10580000 {
0321 compatible = "samsung,exynos7-pinctrl";
0322 reg = <0x10580000 0x1000>;
0323
0324 wakeup-interrupt-controller {
0325 compatible = "samsung,exynos7-wakeup-eint";
0326 interrupt-parent = <&gic>;
0327 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0328 };
0329 };
0330
0331 pinctrl_bus0: pinctrl@13470000 {
0332 compatible = "samsung,exynos7-pinctrl";
0333 reg = <0x13470000 0x1000>;
0334 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
0335 };
0336
0337 pinctrl_nfc: pinctrl@14cd0000 {
0338 compatible = "samsung,exynos7-pinctrl";
0339 reg = <0x14cd0000 0x1000>;
0340 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
0341 };
0342
0343 pinctrl_touch: pinctrl@14ce0000 {
0344 compatible = "samsung,exynos7-pinctrl";
0345 reg = <0x14ce0000 0x1000>;
0346 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
0347 };
0348
0349 pinctrl_ff: pinctrl@14c90000 {
0350 compatible = "samsung,exynos7-pinctrl";
0351 reg = <0x14c90000 0x1000>;
0352 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
0353 };
0354
0355 pinctrl_ese: pinctrl@14ca0000 {
0356 compatible = "samsung,exynos7-pinctrl";
0357 reg = <0x14ca0000 0x1000>;
0358 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
0359 };
0360
0361 pinctrl_fsys0: pinctrl@10e60000 {
0362 compatible = "samsung,exynos7-pinctrl";
0363 reg = <0x10e60000 0x1000>;
0364 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0365 };
0366
0367 pinctrl_fsys1: pinctrl@15690000 {
0368 compatible = "samsung,exynos7-pinctrl";
0369 reg = <0x15690000 0x1000>;
0370 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0371 };
0372
0373 pinctrl_bus1: pinctrl@14870000 {
0374 compatible = "samsung,exynos7-pinctrl";
0375 reg = <0x14870000 0x1000>;
0376 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
0377 };
0378
0379 hsi2c_0: i2c@13640000 {
0380 compatible = "samsung,exynos7-hsi2c";
0381 reg = <0x13640000 0x1000>;
0382 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&hs_i2c0_bus>;
0387 clocks = <&clock_peric0 PCLK_HSI2C0>;
0388 clock-names = "hsi2c";
0389 status = "disabled";
0390 };
0391
0392 hsi2c_1: i2c@13650000 {
0393 compatible = "samsung,exynos7-hsi2c";
0394 reg = <0x13650000 0x1000>;
0395 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
0396 #address-cells = <1>;
0397 #size-cells = <0>;
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&hs_i2c1_bus>;
0400 clocks = <&clock_peric0 PCLK_HSI2C1>;
0401 clock-names = "hsi2c";
0402 status = "disabled";
0403 };
0404
0405 hsi2c_2: i2c@14e60000 {
0406 compatible = "samsung,exynos7-hsi2c";
0407 reg = <0x14e60000 0x1000>;
0408 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
0409 #address-cells = <1>;
0410 #size-cells = <0>;
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&hs_i2c2_bus>;
0413 clocks = <&clock_peric1 PCLK_HSI2C2>;
0414 clock-names = "hsi2c";
0415 status = "disabled";
0416 };
0417
0418 hsi2c_3: i2c@14e70000 {
0419 compatible = "samsung,exynos7-hsi2c";
0420 reg = <0x14e70000 0x1000>;
0421 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
0422 #address-cells = <1>;
0423 #size-cells = <0>;
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&hs_i2c3_bus>;
0426 clocks = <&clock_peric1 PCLK_HSI2C3>;
0427 clock-names = "hsi2c";
0428 status = "disabled";
0429 };
0430
0431 hsi2c_4: i2c@13660000 {
0432 compatible = "samsung,exynos7-hsi2c";
0433 reg = <0x13660000 0x1000>;
0434 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
0435 #address-cells = <1>;
0436 #size-cells = <0>;
0437 pinctrl-names = "default";
0438 pinctrl-0 = <&hs_i2c4_bus>;
0439 clocks = <&clock_peric0 PCLK_HSI2C4>;
0440 clock-names = "hsi2c";
0441 status = "disabled";
0442 };
0443
0444 hsi2c_5: i2c@13670000 {
0445 compatible = "samsung,exynos7-hsi2c";
0446 reg = <0x13670000 0x1000>;
0447 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450 pinctrl-names = "default";
0451 pinctrl-0 = <&hs_i2c5_bus>;
0452 clocks = <&clock_peric0 PCLK_HSI2C5>;
0453 clock-names = "hsi2c";
0454 status = "disabled";
0455 };
0456
0457 hsi2c_6: i2c@14e00000 {
0458 compatible = "samsung,exynos7-hsi2c";
0459 reg = <0x14e00000 0x1000>;
0460 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 pinctrl-names = "default";
0464 pinctrl-0 = <&hs_i2c6_bus>;
0465 clocks = <&clock_peric1 PCLK_HSI2C6>;
0466 clock-names = "hsi2c";
0467 status = "disabled";
0468 };
0469
0470 hsi2c_7: i2c@13e10000 {
0471 compatible = "samsung,exynos7-hsi2c";
0472 reg = <0x13e10000 0x1000>;
0473 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
0474 #address-cells = <1>;
0475 #size-cells = <0>;
0476 pinctrl-names = "default";
0477 pinctrl-0 = <&hs_i2c7_bus>;
0478 clocks = <&clock_peric1 PCLK_HSI2C7>;
0479 clock-names = "hsi2c";
0480 status = "disabled";
0481 };
0482
0483 hsi2c_8: i2c@14e20000 {
0484 compatible = "samsung,exynos7-hsi2c";
0485 reg = <0x14e20000 0x1000>;
0486 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
0487 #address-cells = <1>;
0488 #size-cells = <0>;
0489 pinctrl-names = "default";
0490 pinctrl-0 = <&hs_i2c8_bus>;
0491 clocks = <&clock_peric1 PCLK_HSI2C8>;
0492 clock-names = "hsi2c";
0493 status = "disabled";
0494 };
0495
0496 hsi2c_9: i2c@13680000 {
0497 compatible = "samsung,exynos7-hsi2c";
0498 reg = <0x13680000 0x1000>;
0499 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
0500 #address-cells = <1>;
0501 #size-cells = <0>;
0502 pinctrl-names = "default";
0503 pinctrl-0 = <&hs_i2c9_bus>;
0504 clocks = <&clock_peric0 PCLK_HSI2C9>;
0505 clock-names = "hsi2c";
0506 status = "disabled";
0507 };
0508
0509 hsi2c_10: i2c@13690000 {
0510 compatible = "samsung,exynos7-hsi2c";
0511 reg = <0x13690000 0x1000>;
0512 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
0513 #address-cells = <1>;
0514 #size-cells = <0>;
0515 pinctrl-names = "default";
0516 pinctrl-0 = <&hs_i2c10_bus>;
0517 clocks = <&clock_peric0 PCLK_HSI2C10>;
0518 clock-names = "hsi2c";
0519 status = "disabled";
0520 };
0521
0522 hsi2c_11: i2c@136a0000 {
0523 compatible = "samsung,exynos7-hsi2c";
0524 reg = <0x136a0000 0x1000>;
0525 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 pinctrl-names = "default";
0529 pinctrl-0 = <&hs_i2c11_bus>;
0530 clocks = <&clock_peric0 PCLK_HSI2C11>;
0531 clock-names = "hsi2c";
0532 status = "disabled";
0533 };
0534
0535 pmu_system_controller: system-controller@105c0000 {
0536 compatible = "samsung,exynos7-pmu", "syscon";
0537 reg = <0x105c0000 0x5000>;
0538 };
0539
0540 rtc: rtc@10590000 {
0541 compatible = "samsung,s3c6410-rtc";
0542 reg = <0x10590000 0x100>;
0543 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
0544 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
0545 clocks = <&clock_ccore PCLK_RTC>;
0546 clock-names = "rtc";
0547 status = "disabled";
0548 };
0549
0550 watchdog: watchdog@101d0000 {
0551 compatible = "samsung,exynos7-wdt";
0552 reg = <0x101d0000 0x100>;
0553 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0554 clocks = <&clock_peris PCLK_WDT>;
0555 clock-names = "watchdog";
0556 samsung,syscon-phandle = <&pmu_system_controller>;
0557 status = "disabled";
0558 };
0559
0560 gpu: gpu@14ac0000 {
0561 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
0562 reg = <0x14ac0000 0x5000>;
0563 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
0564 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
0565 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
0566 interrupt-names = "job", "mmu", "gpu";
0567 status = "disabled";
0568 /* TODO: operating points for DVFS, cooling device */
0569 };
0570
0571 mmc_0: mmc@15740000 {
0572 compatible = "samsung,exynos7-dw-mshc-smu";
0573 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0574 #address-cells = <1>;
0575 #size-cells = <0>;
0576 reg = <0x15740000 0x2000>;
0577 clocks = <&clock_fsys1 ACLK_MMC0>,
0578 <&clock_top1 CLK_SCLK_MMC0>;
0579 clock-names = "biu", "ciu";
0580 fifo-depth = <0x40>;
0581 status = "disabled";
0582 };
0583
0584 mmc_1: mmc@15750000 {
0585 compatible = "samsung,exynos7-dw-mshc";
0586 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0587 #address-cells = <1>;
0588 #size-cells = <0>;
0589 reg = <0x15750000 0x2000>;
0590 clocks = <&clock_fsys1 ACLK_MMC1>,
0591 <&clock_top1 CLK_SCLK_MMC1>;
0592 clock-names = "biu", "ciu";
0593 fifo-depth = <0x40>;
0594 status = "disabled";
0595 };
0596
0597 mmc_2: mmc@15560000 {
0598 compatible = "samsung,exynos7-dw-mshc-smu";
0599 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
0600 #address-cells = <1>;
0601 #size-cells = <0>;
0602 reg = <0x15560000 0x2000>;
0603 clocks = <&clock_fsys0 ACLK_MMC2>,
0604 <&clock_top1 CLK_SCLK_MMC2>;
0605 clock-names = "biu", "ciu";
0606 fifo-depth = <0x40>;
0607 status = "disabled";
0608 };
0609
0610 adc: adc@13620000 {
0611 compatible = "samsung,exynos7-adc";
0612 reg = <0x13620000 0x100>;
0613 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
0614 clocks = <&clock_peric0 PCLK_ADCIF>;
0615 clock-names = "adc";
0616 #io-channel-cells = <1>;
0617 status = "disabled";
0618 };
0619
0620 pwm: pwm@136c0000 {
0621 compatible = "samsung,exynos4210-pwm";
0622 reg = <0x136c0000 0x100>;
0623 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
0624 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
0625 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
0626 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
0627 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
0628 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
0629 #pwm-cells = <3>;
0630 clocks = <&clock_peric0 PCLK_PWM>;
0631 clock-names = "timers";
0632 };
0633
0634 tmuctrl_0: tmu@10060000 {
0635 compatible = "samsung,exynos7-tmu";
0636 reg = <0x10060000 0x200>;
0637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0638 clocks = <&clock_peris PCLK_TMU>,
0639 <&clock_peris SCLK_TMU>;
0640 clock-names = "tmu_apbif", "tmu_sclk";
0641 #thermal-sensor-cells = <0>;
0642 };
0643
0644 ufs: ufs@15570000 {
0645 compatible = "samsung,exynos7-ufs";
0646 reg = <0x15570000 0x100>, /* 0: HCI standard */
0647 <0x15570100 0x100>, /* 1: Vendor specificed */
0648 <0x15571000 0x200>, /* 2: UNIPRO */
0649 <0x15572000 0x300>; /* 3: UFS protector */
0650 reg-names = "hci", "vs_hci", "unipro", "ufsp";
0651 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0652 clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
0653 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
0654 clock-names = "core_clk", "sclk_unipro_main";
0655 freq-table-hz = <0 0>, <0 0>;
0656 pinctrl-names = "default";
0657 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
0658 phys = <&ufs_phy>;
0659 phy-names = "ufs-phy";
0660 status = "disabled";
0661 };
0662
0663 ufs_phy: ufs-phy@15571800 {
0664 compatible = "samsung,exynos7-ufs-phy";
0665 reg = <0x15571800 0x240>;
0666 reg-names = "phy-pma";
0667 samsung,pmu-syscon = <&pmu_system_controller>;
0668 #phy-cells = <0>;
0669 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
0670 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
0671 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
0672 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
0673 clock-names = "ref_clk", "rx1_symbol_clk",
0674 "rx0_symbol_clk",
0675 "tx0_symbol_clk";
0676 };
0677
0678 usbdrd_phy: phy@15500000 {
0679 compatible = "samsung,exynos7-usbdrd-phy";
0680 reg = <0x15500000 0x100>;
0681 clocks = <&clock_fsys0 ACLK_USBDRD300>,
0682 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
0683 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
0684 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
0685 <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
0686 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
0687 samsung,pmu-syscon = <&pmu_system_controller>;
0688 #phy-cells = <1>;
0689 };
0690
0691 usbdrd: usb {
0692 compatible = "samsung,exynos7-dwusb3";
0693 clocks = <&clock_fsys0 ACLK_USBDRD300>,
0694 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
0695 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
0696 clock-names = "usbdrd30", "usbdrd30_susp_clk",
0697 "usbdrd30_axius_clk";
0698 #address-cells = <1>;
0699 #size-cells = <1>;
0700 ranges;
0701
0702 usb@15400000 {
0703 compatible = "snps,dwc3";
0704 reg = <0x15400000 0x10000>;
0705 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0706 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
0707 phy-names = "usb2-phy", "usb3-phy";
0708 };
0709 };
0710 };
0711
0712 thermal-zones {
0713 atlas_thermal: cluster0-thermal {
0714 polling-delay-passive = <0>; /* milliseconds */
0715 polling-delay = <0>; /* milliseconds */
0716 thermal-sensors = <&tmuctrl_0>;
0717 #include "exynos7-trip-points.dtsi"
0718 };
0719 };
0720
0721 timer {
0722 compatible = "arm,armv8-timer";
0723 interrupts = <GIC_PPI 13
0724 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0725 <GIC_PPI 14
0726 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0727 <GIC_PPI 11
0728 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0729 <GIC_PPI 10
0730 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0731 };
0732 };
0733
0734 #include "exynos7-pinctrl.dtsi"
0735 #include "arm/exynos-syscon-restart.dtsi"
