0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's Exynos5433 SoC device tree source
0004 *
0005 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
0006 *
0007 * Samsung's Exynos5433 SoC device nodes are listed in this file.
0008 * Exynos5433 based board files can include this file and provide
0009 * values for board specific bindings.
0010 *
0011 * Note: This file does not include device nodes for all the controllers in
0012 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
0013 * additional nodes can be added to this file.
0014 */
0015
0016 #include <dt-bindings/clock/exynos5433.h>
0017 #include <dt-bindings/interrupt-controller/arm-gic.h>
0018
0019 / {
0020 compatible = "samsung,exynos5433";
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 interrupt-parent = <&gic>;
0025
0026 arm-a53-pmu {
0027 compatible = "arm,cortex-a53-pmu";
0028 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0029 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0030 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0031 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0032 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0033 };
0034
0035 arm-a57-pmu {
0036 compatible = "arm,cortex-a57-pmu";
0037 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0038 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0039 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0040 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0041 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0042 };
0043
0044 xxti: clock {
0045 /* XXTI */
0046 compatible = "fixed-clock";
0047 clock-output-names = "oscclk";
0048 #clock-cells = <0>;
0049 };
0050
0051 cpus {
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054
0055 cpu-map {
0056 cluster0 {
0057 core0 {
0058 cpu = <&cpu0>;
0059 };
0060 core1 {
0061 cpu = <&cpu1>;
0062 };
0063 core2 {
0064 cpu = <&cpu2>;
0065 };
0066 core3 {
0067 cpu = <&cpu3>;
0068 };
0069 };
0070
0071 cluster1 {
0072 core0 {
0073 cpu = <&cpu4>;
0074 };
0075 core1 {
0076 cpu = <&cpu5>;
0077 };
0078 core2 {
0079 cpu = <&cpu6>;
0080 };
0081 core3 {
0082 cpu = <&cpu7>;
0083 };
0084 };
0085 };
0086
0087 cpu0: cpu@100 {
0088 device_type = "cpu";
0089 compatible = "arm,cortex-a53";
0090 enable-method = "psci";
0091 reg = <0x100>;
0092 clock-frequency = <1300000000>;
0093 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
0094 clock-names = "apolloclk";
0095 operating-points-v2 = <&cluster_a53_opp_table>;
0096 #cooling-cells = <2>;
0097 i-cache-size = <0x8000>;
0098 i-cache-line-size = <64>;
0099 i-cache-sets = <256>;
0100 d-cache-size = <0x8000>;
0101 d-cache-line-size = <64>;
0102 d-cache-sets = <128>;
0103 next-level-cache = <&cluster_a53_l2>;
0104 };
0105
0106 cpu1: cpu@101 {
0107 device_type = "cpu";
0108 compatible = "arm,cortex-a53";
0109 enable-method = "psci";
0110 reg = <0x101>;
0111 clock-frequency = <1300000000>;
0112 operating-points-v2 = <&cluster_a53_opp_table>;
0113 #cooling-cells = <2>;
0114 i-cache-size = <0x8000>;
0115 i-cache-line-size = <64>;
0116 i-cache-sets = <256>;
0117 d-cache-size = <0x8000>;
0118 d-cache-line-size = <64>;
0119 d-cache-sets = <128>;
0120 next-level-cache = <&cluster_a53_l2>;
0121 };
0122
0123 cpu2: cpu@102 {
0124 device_type = "cpu";
0125 compatible = "arm,cortex-a53";
0126 enable-method = "psci";
0127 reg = <0x102>;
0128 clock-frequency = <1300000000>;
0129 operating-points-v2 = <&cluster_a53_opp_table>;
0130 #cooling-cells = <2>;
0131 i-cache-size = <0x8000>;
0132 i-cache-line-size = <64>;
0133 i-cache-sets = <256>;
0134 d-cache-size = <0x8000>;
0135 d-cache-line-size = <64>;
0136 d-cache-sets = <128>;
0137 next-level-cache = <&cluster_a53_l2>;
0138 };
0139
0140 cpu3: cpu@103 {
0141 device_type = "cpu";
0142 compatible = "arm,cortex-a53";
0143 enable-method = "psci";
0144 reg = <0x103>;
0145 clock-frequency = <1300000000>;
0146 operating-points-v2 = <&cluster_a53_opp_table>;
0147 #cooling-cells = <2>;
0148 i-cache-size = <0x8000>;
0149 i-cache-line-size = <64>;
0150 i-cache-sets = <256>;
0151 d-cache-size = <0x8000>;
0152 d-cache-line-size = <64>;
0153 d-cache-sets = <128>;
0154 next-level-cache = <&cluster_a53_l2>;
0155 };
0156
0157 cpu4: cpu@0 {
0158 device_type = "cpu";
0159 compatible = "arm,cortex-a57";
0160 enable-method = "psci";
0161 reg = <0x0>;
0162 clock-frequency = <1900000000>;
0163 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
0164 clock-names = "atlasclk";
0165 operating-points-v2 = <&cluster_a57_opp_table>;
0166 #cooling-cells = <2>;
0167 i-cache-size = <0xc000>;
0168 i-cache-line-size = <64>;
0169 i-cache-sets = <256>;
0170 d-cache-size = <0x8000>;
0171 d-cache-line-size = <64>;
0172 d-cache-sets = <256>;
0173 next-level-cache = <&cluster_a57_l2>;
0174 };
0175
0176 cpu5: cpu@1 {
0177 device_type = "cpu";
0178 compatible = "arm,cortex-a57";
0179 enable-method = "psci";
0180 reg = <0x1>;
0181 clock-frequency = <1900000000>;
0182 operating-points-v2 = <&cluster_a57_opp_table>;
0183 #cooling-cells = <2>;
0184 i-cache-size = <0xc000>;
0185 i-cache-line-size = <64>;
0186 i-cache-sets = <256>;
0187 d-cache-size = <0x8000>;
0188 d-cache-line-size = <64>;
0189 d-cache-sets = <256>;
0190 next-level-cache = <&cluster_a57_l2>;
0191 };
0192
0193 cpu6: cpu@2 {
0194 device_type = "cpu";
0195 compatible = "arm,cortex-a57";
0196 enable-method = "psci";
0197 reg = <0x2>;
0198 clock-frequency = <1900000000>;
0199 operating-points-v2 = <&cluster_a57_opp_table>;
0200 #cooling-cells = <2>;
0201 i-cache-size = <0xc000>;
0202 i-cache-line-size = <64>;
0203 i-cache-sets = <256>;
0204 d-cache-size = <0x8000>;
0205 d-cache-line-size = <64>;
0206 d-cache-sets = <256>;
0207 next-level-cache = <&cluster_a57_l2>;
0208 };
0209
0210 cpu7: cpu@3 {
0211 device_type = "cpu";
0212 compatible = "arm,cortex-a57";
0213 enable-method = "psci";
0214 reg = <0x3>;
0215 clock-frequency = <1900000000>;
0216 operating-points-v2 = <&cluster_a57_opp_table>;
0217 #cooling-cells = <2>;
0218 i-cache-size = <0xc000>;
0219 i-cache-line-size = <64>;
0220 i-cache-sets = <256>;
0221 d-cache-size = <0x8000>;
0222 d-cache-line-size = <64>;
0223 d-cache-sets = <256>;
0224 next-level-cache = <&cluster_a57_l2>;
0225 };
0226
0227 cluster_a57_l2: l2-cache0 {
0228 compatible = "cache";
0229 cache-size = <0x200000>;
0230 cache-line-size = <64>;
0231 cache-sets = <2048>;
0232 };
0233
0234 cluster_a53_l2: l2-cache1 {
0235 compatible = "cache";
0236 cache-size = <0x40000>;
0237 cache-line-size = <64>;
0238 cache-sets = <256>;
0239 };
0240 };
0241
0242 cluster_a53_opp_table: opp-table-0 {
0243 compatible = "operating-points-v2";
0244 opp-shared;
0245
0246 opp-400000000 {
0247 opp-hz = /bits/ 64 <400000000>;
0248 opp-microvolt = <900000>;
0249 };
0250 opp-500000000 {
0251 opp-hz = /bits/ 64 <500000000>;
0252 opp-microvolt = <925000>;
0253 };
0254 opp-600000000 {
0255 opp-hz = /bits/ 64 <600000000>;
0256 opp-microvolt = <950000>;
0257 };
0258 opp-700000000 {
0259 opp-hz = /bits/ 64 <700000000>;
0260 opp-microvolt = <975000>;
0261 };
0262 opp-800000000 {
0263 opp-hz = /bits/ 64 <800000000>;
0264 opp-microvolt = <1000000>;
0265 };
0266 opp-900000000 {
0267 opp-hz = /bits/ 64 <900000000>;
0268 opp-microvolt = <1050000>;
0269 };
0270 opp-1000000000 {
0271 opp-hz = /bits/ 64 <1000000000>;
0272 opp-microvolt = <1075000>;
0273 };
0274 opp-1100000000 {
0275 opp-hz = /bits/ 64 <1100000000>;
0276 opp-microvolt = <1112500>;
0277 };
0278 opp-1200000000 {
0279 opp-hz = /bits/ 64 <1200000000>;
0280 opp-microvolt = <1112500>;
0281 };
0282 opp-1300000000 {
0283 opp-hz = /bits/ 64 <1300000000>;
0284 opp-microvolt = <1150000>;
0285 };
0286 };
0287
0288 cluster_a57_opp_table: opp-table-1 {
0289 compatible = "operating-points-v2";
0290 opp-shared;
0291
0292 opp-500000000 {
0293 opp-hz = /bits/ 64 <500000000>;
0294 opp-microvolt = <900000>;
0295 };
0296 opp-600000000 {
0297 opp-hz = /bits/ 64 <600000000>;
0298 opp-microvolt = <900000>;
0299 };
0300 opp-700000000 {
0301 opp-hz = /bits/ 64 <700000000>;
0302 opp-microvolt = <912500>;
0303 };
0304 opp-800000000 {
0305 opp-hz = /bits/ 64 <800000000>;
0306 opp-microvolt = <912500>;
0307 };
0308 opp-900000000 {
0309 opp-hz = /bits/ 64 <900000000>;
0310 opp-microvolt = <937500>;
0311 };
0312 opp-1000000000 {
0313 opp-hz = /bits/ 64 <1000000000>;
0314 opp-microvolt = <975000>;
0315 };
0316 opp-1100000000 {
0317 opp-hz = /bits/ 64 <1100000000>;
0318 opp-microvolt = <1012500>;
0319 };
0320 opp-1200000000 {
0321 opp-hz = /bits/ 64 <1200000000>;
0322 opp-microvolt = <1037500>;
0323 };
0324 opp-1300000000 {
0325 opp-hz = /bits/ 64 <1300000000>;
0326 opp-microvolt = <1062500>;
0327 };
0328 opp-1400000000 {
0329 opp-hz = /bits/ 64 <1400000000>;
0330 opp-microvolt = <1087500>;
0331 };
0332 opp-1500000000 {
0333 opp-hz = /bits/ 64 <1500000000>;
0334 opp-microvolt = <1125000>;
0335 };
0336 opp-1600000000 {
0337 opp-hz = /bits/ 64 <1600000000>;
0338 opp-microvolt = <1137500>;
0339 };
0340 opp-1700000000 {
0341 opp-hz = /bits/ 64 <1700000000>;
0342 opp-microvolt = <1175000>;
0343 };
0344 opp-1800000000 {
0345 opp-hz = /bits/ 64 <1800000000>;
0346 opp-microvolt = <1212500>;
0347 };
0348 opp-1900000000 {
0349 opp-hz = /bits/ 64 <1900000000>;
0350 opp-microvolt = <1262500>;
0351 };
0352 };
0353
0354 psci {
0355 compatible = "arm,psci";
0356 method = "smc";
0357 cpu_off = <0x84000002>;
0358 cpu_on = <0xC4000003>;
0359 };
0360
0361 soc: soc@0 {
0362 compatible = "simple-bus";
0363 #address-cells = <1>;
0364 #size-cells = <1>;
0365 ranges = <0x0 0x0 0x0 0x18000000>;
0366
0367 chipid@10000000 {
0368 compatible = "samsung,exynos4210-chipid";
0369 reg = <0x10000000 0x100>;
0370 };
0371
0372 cmu_top: clock-controller@10030000 {
0373 compatible = "samsung,exynos5433-cmu-top";
0374 reg = <0x10030000 0x1000>;
0375 #clock-cells = <1>;
0376
0377 clock-names = "oscclk",
0378 "sclk_mphy_pll",
0379 "sclk_mfc_pll",
0380 "sclk_bus_pll";
0381 clocks = <&xxti>,
0382 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
0383 <&cmu_mif CLK_SCLK_MFC_PLL>,
0384 <&cmu_mif CLK_SCLK_BUS_PLL>;
0385 };
0386
0387 cmu_cpif: clock-controller@10fc0000 {
0388 compatible = "samsung,exynos5433-cmu-cpif";
0389 reg = <0x10fc0000 0x1000>;
0390 #clock-cells = <1>;
0391
0392 clock-names = "oscclk";
0393 clocks = <&xxti>;
0394 };
0395
0396 cmu_mif: clock-controller@105b0000 {
0397 compatible = "samsung,exynos5433-cmu-mif";
0398 reg = <0x105b0000 0x2000>;
0399 #clock-cells = <1>;
0400
0401 clock-names = "oscclk",
0402 "sclk_mphy_pll";
0403 clocks = <&xxti>,
0404 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
0405 };
0406
0407 cmu_peric: clock-controller@14c80000 {
0408 compatible = "samsung,exynos5433-cmu-peric";
0409 reg = <0x14c80000 0x1000>;
0410 #clock-cells = <1>;
0411 };
0412
0413 cmu_peris: clock-controller@10040000 {
0414 compatible = "samsung,exynos5433-cmu-peris";
0415 reg = <0x10040000 0x1000>;
0416 #clock-cells = <1>;
0417 };
0418
0419 cmu_fsys: clock-controller@156e0000 {
0420 compatible = "samsung,exynos5433-cmu-fsys";
0421 reg = <0x156e0000 0x1000>;
0422 #clock-cells = <1>;
0423
0424 clock-names = "oscclk",
0425 "sclk_ufs_mphy",
0426 "aclk_fsys_200",
0427 "sclk_pcie_100_fsys",
0428 "sclk_ufsunipro_fsys",
0429 "sclk_mmc2_fsys",
0430 "sclk_mmc1_fsys",
0431 "sclk_mmc0_fsys",
0432 "sclk_usbhost30_fsys",
0433 "sclk_usbdrd30_fsys";
0434 clocks = <&xxti>,
0435 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
0436 <&cmu_top CLK_ACLK_FSYS_200>,
0437 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
0438 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
0439 <&cmu_top CLK_SCLK_MMC2_FSYS>,
0440 <&cmu_top CLK_SCLK_MMC1_FSYS>,
0441 <&cmu_top CLK_SCLK_MMC0_FSYS>,
0442 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
0443 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
0444 };
0445
0446 cmu_g2d: clock-controller@12460000 {
0447 compatible = "samsung,exynos5433-cmu-g2d";
0448 reg = <0x12460000 0x1000>;
0449 #clock-cells = <1>;
0450
0451 clock-names = "oscclk",
0452 "aclk_g2d_266",
0453 "aclk_g2d_400";
0454 clocks = <&xxti>,
0455 <&cmu_top CLK_ACLK_G2D_266>,
0456 <&cmu_top CLK_ACLK_G2D_400>;
0457 power-domains = <&pd_g2d>;
0458 };
0459
0460 cmu_disp: clock-controller@13b90000 {
0461 compatible = "samsung,exynos5433-cmu-disp";
0462 reg = <0x13b90000 0x1000>;
0463 #clock-cells = <1>;
0464
0465 clock-names = "oscclk",
0466 "sclk_dsim1_disp",
0467 "sclk_dsim0_disp",
0468 "sclk_dsd_disp",
0469 "sclk_decon_tv_eclk_disp",
0470 "sclk_decon_vclk_disp",
0471 "sclk_decon_eclk_disp",
0472 "sclk_decon_tv_vclk_disp",
0473 "aclk_disp_333";
0474 clocks = <&xxti>,
0475 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
0476 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
0477 <&cmu_mif CLK_SCLK_DSD_DISP>,
0478 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
0479 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
0480 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
0481 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
0482 <&cmu_mif CLK_ACLK_DISP_333>;
0483 power-domains = <&pd_disp>;
0484 };
0485
0486 cmu_aud: clock-controller@114c0000 {
0487 compatible = "samsung,exynos5433-cmu-aud";
0488 reg = <0x114c0000 0x1000>;
0489 #clock-cells = <1>;
0490 clock-names = "oscclk", "fout_aud_pll";
0491 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
0492 power-domains = <&pd_aud>;
0493 };
0494
0495 cmu_bus0: clock-controller@13600000 {
0496 compatible = "samsung,exynos5433-cmu-bus0";
0497 reg = <0x13600000 0x1000>;
0498 #clock-cells = <1>;
0499
0500 clock-names = "aclk_bus0_400";
0501 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
0502 };
0503
0504 cmu_bus1: clock-controller@14800000 {
0505 compatible = "samsung,exynos5433-cmu-bus1";
0506 reg = <0x14800000 0x1000>;
0507 #clock-cells = <1>;
0508
0509 clock-names = "aclk_bus1_400";
0510 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
0511 };
0512
0513 cmu_bus2: clock-controller@13400000 {
0514 compatible = "samsung,exynos5433-cmu-bus2";
0515 reg = <0x13400000 0x1000>;
0516 #clock-cells = <1>;
0517
0518 clock-names = "oscclk", "aclk_bus2_400";
0519 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
0520 };
0521
0522 cmu_g3d: clock-controller@14aa0000 {
0523 compatible = "samsung,exynos5433-cmu-g3d";
0524 reg = <0x14aa0000 0x2000>;
0525 #clock-cells = <1>;
0526
0527 clock-names = "oscclk", "aclk_g3d_400";
0528 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
0529 power-domains = <&pd_g3d>;
0530 };
0531
0532 cmu_gscl: clock-controller@13cf0000 {
0533 compatible = "samsung,exynos5433-cmu-gscl";
0534 reg = <0x13cf0000 0x1000>;
0535 #clock-cells = <1>;
0536
0537 clock-names = "oscclk",
0538 "aclk_gscl_111",
0539 "aclk_gscl_333";
0540 clocks = <&xxti>,
0541 <&cmu_top CLK_ACLK_GSCL_111>,
0542 <&cmu_top CLK_ACLK_GSCL_333>;
0543 power-domains = <&pd_gscl>;
0544 };
0545
0546 cmu_apollo: clock-controller@11900000 {
0547 compatible = "samsung,exynos5433-cmu-apollo";
0548 reg = <0x11900000 0x2000>;
0549 #clock-cells = <1>;
0550
0551 clock-names = "oscclk", "sclk_bus_pll_apollo";
0552 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
0553 };
0554
0555 cmu_atlas: clock-controller@11800000 {
0556 compatible = "samsung,exynos5433-cmu-atlas";
0557 reg = <0x11800000 0x2000>;
0558 #clock-cells = <1>;
0559
0560 clock-names = "oscclk", "sclk_bus_pll_atlas";
0561 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
0562 };
0563
0564 cmu_mscl: clock-controller@150d0000 {
0565 compatible = "samsung,exynos5433-cmu-mscl";
0566 reg = <0x150d0000 0x1000>;
0567 #clock-cells = <1>;
0568
0569 clock-names = "oscclk",
0570 "sclk_jpeg_mscl",
0571 "aclk_mscl_400";
0572 clocks = <&xxti>,
0573 <&cmu_top CLK_SCLK_JPEG_MSCL>,
0574 <&cmu_top CLK_ACLK_MSCL_400>;
0575 power-domains = <&pd_mscl>;
0576 };
0577
0578 cmu_mfc: clock-controller@15280000 {
0579 compatible = "samsung,exynos5433-cmu-mfc";
0580 reg = <0x15280000 0x1000>;
0581 #clock-cells = <1>;
0582
0583 clock-names = "oscclk", "aclk_mfc_400";
0584 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
0585 power-domains = <&pd_mfc>;
0586 };
0587
0588 cmu_hevc: clock-controller@14f80000 {
0589 compatible = "samsung,exynos5433-cmu-hevc";
0590 reg = <0x14f80000 0x1000>;
0591 #clock-cells = <1>;
0592
0593 clock-names = "oscclk", "aclk_hevc_400";
0594 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
0595 power-domains = <&pd_hevc>;
0596 };
0597
0598 cmu_isp: clock-controller@146d0000 {
0599 compatible = "samsung,exynos5433-cmu-isp";
0600 reg = <0x146d0000 0x1000>;
0601 #clock-cells = <1>;
0602
0603 clock-names = "oscclk",
0604 "aclk_isp_dis_400",
0605 "aclk_isp_400";
0606 clocks = <&xxti>,
0607 <&cmu_top CLK_ACLK_ISP_DIS_400>,
0608 <&cmu_top CLK_ACLK_ISP_400>;
0609 power-domains = <&pd_isp>;
0610 };
0611
0612 cmu_cam0: clock-controller@120d0000 {
0613 compatible = "samsung,exynos5433-cmu-cam0";
0614 reg = <0x120d0000 0x1000>;
0615 #clock-cells = <1>;
0616
0617 clock-names = "oscclk",
0618 "aclk_cam0_333",
0619 "aclk_cam0_400",
0620 "aclk_cam0_552";
0621 clocks = <&xxti>,
0622 <&cmu_top CLK_ACLK_CAM0_333>,
0623 <&cmu_top CLK_ACLK_CAM0_400>,
0624 <&cmu_top CLK_ACLK_CAM0_552>;
0625 power-domains = <&pd_cam0>;
0626 };
0627
0628 cmu_cam1: clock-controller@145d0000 {
0629 compatible = "samsung,exynos5433-cmu-cam1";
0630 reg = <0x145d0000 0x1000>;
0631 #clock-cells = <1>;
0632
0633 clock-names = "oscclk",
0634 "sclk_isp_uart_cam1",
0635 "sclk_isp_spi1_cam1",
0636 "sclk_isp_spi0_cam1",
0637 "aclk_cam1_333",
0638 "aclk_cam1_400",
0639 "aclk_cam1_552";
0640 clocks = <&xxti>,
0641 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
0642 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
0643 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
0644 <&cmu_top CLK_ACLK_CAM1_333>,
0645 <&cmu_top CLK_ACLK_CAM1_400>,
0646 <&cmu_top CLK_ACLK_CAM1_552>;
0647 power-domains = <&pd_cam1>;
0648 };
0649
0650 cmu_imem: clock-controller@11060000 {
0651 compatible = "samsung,exynos5433-cmu-imem";
0652 reg = <0x11060000 0x1000>;
0653 #clock-cells = <1>;
0654
0655 clock-names = "oscclk",
0656 "aclk_imem_sssx_266",
0657 "aclk_imem_266",
0658 "aclk_imem_200";
0659 clocks = <&xxti>,
0660 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
0661 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
0662 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
0663 };
0664
0665 slim_sss: slim-sss@11140000 {
0666 compatible = "samsung,exynos5433-slim-sss";
0667 reg = <0x11140000 0x1000>;
0668 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
0669 clock-names = "pclk", "aclk";
0670 clocks = <&cmu_imem CLK_PCLK_SLIMSSS>,
0671 <&cmu_imem CLK_ACLK_SLIMSSS>;
0672 };
0673
0674 pd_gscl: power-domain@105c4000 {
0675 compatible = "samsung,exynos5433-pd";
0676 reg = <0x105c4000 0x20>;
0677 #power-domain-cells = <0>;
0678 label = "GSCL";
0679 };
0680
0681 pd_cam0: power-domain@105c4020 {
0682 compatible = "samsung,exynos5433-pd";
0683 reg = <0x105c4020 0x20>;
0684 #power-domain-cells = <0>;
0685 power-domains = <&pd_cam1>;
0686 label = "CAM0";
0687 };
0688
0689 pd_mscl: power-domain@105c4040 {
0690 compatible = "samsung,exynos5433-pd";
0691 reg = <0x105c4040 0x20>;
0692 #power-domain-cells = <0>;
0693 label = "MSCL";
0694 };
0695
0696 pd_g3d: power-domain@105c4060 {
0697 compatible = "samsung,exynos5433-pd";
0698 reg = <0x105c4060 0x20>;
0699 #power-domain-cells = <0>;
0700 label = "G3D";
0701 };
0702
0703 pd_disp: power-domain@105c4080 {
0704 compatible = "samsung,exynos5433-pd";
0705 reg = <0x105c4080 0x20>;
0706 #power-domain-cells = <0>;
0707 label = "DISP";
0708 };
0709
0710 pd_cam1: power-domain@105c40a0 {
0711 compatible = "samsung,exynos5433-pd";
0712 reg = <0x105c40a0 0x20>;
0713 #power-domain-cells = <0>;
0714 label = "CAM1";
0715 };
0716
0717 pd_aud: power-domain@105c40c0 {
0718 compatible = "samsung,exynos5433-pd";
0719 reg = <0x105c40c0 0x20>;
0720 #power-domain-cells = <0>;
0721 label = "AUD";
0722 };
0723
0724 pd_g2d: power-domain@105c4120 {
0725 compatible = "samsung,exynos5433-pd";
0726 reg = <0x105c4120 0x20>;
0727 #power-domain-cells = <0>;
0728 label = "G2D";
0729 };
0730
0731 pd_isp: power-domain@105c4140 {
0732 compatible = "samsung,exynos5433-pd";
0733 reg = <0x105c4140 0x20>;
0734 #power-domain-cells = <0>;
0735 power-domains = <&pd_cam0>;
0736 label = "ISP";
0737 };
0738
0739 pd_mfc: power-domain@105c4180 {
0740 compatible = "samsung,exynos5433-pd";
0741 reg = <0x105c4180 0x20>;
0742 #power-domain-cells = <0>;
0743 label = "MFC";
0744 };
0745
0746 pd_hevc: power-domain@105c41c0 {
0747 compatible = "samsung,exynos5433-pd";
0748 reg = <0x105c41c0 0x20>;
0749 #power-domain-cells = <0>;
0750 label = "HEVC";
0751 };
0752
0753 tmu_atlas0: tmu@10060000 {
0754 compatible = "samsung,exynos5433-tmu";
0755 reg = <0x10060000 0x200>;
0756 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0757 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
0758 <&cmu_peris CLK_SCLK_TMU0>;
0759 clock-names = "tmu_apbif", "tmu_sclk";
0760 #thermal-sensor-cells = <0>;
0761 status = "disabled";
0762 };
0763
0764 tmu_atlas1: tmu@10068000 {
0765 compatible = "samsung,exynos5433-tmu";
0766 reg = <0x10068000 0x200>;
0767 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0768 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
0769 <&cmu_peris CLK_SCLK_TMU0>;
0770 clock-names = "tmu_apbif", "tmu_sclk";
0771 #thermal-sensor-cells = <0>;
0772 status = "disabled";
0773 };
0774
0775 tmu_g3d: tmu@10070000 {
0776 compatible = "samsung,exynos5433-tmu";
0777 reg = <0x10070000 0x200>;
0778 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0779 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
0780 <&cmu_peris CLK_SCLK_TMU1>;
0781 clock-names = "tmu_apbif", "tmu_sclk";
0782 #thermal-sensor-cells = <0>;
0783 status = "disabled";
0784 };
0785
0786 tmu_apollo: tmu@10078000 {
0787 compatible = "samsung,exynos5433-tmu";
0788 reg = <0x10078000 0x200>;
0789 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0790 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
0791 <&cmu_peris CLK_SCLK_TMU1>;
0792 clock-names = "tmu_apbif", "tmu_sclk";
0793 #thermal-sensor-cells = <0>;
0794 status = "disabled";
0795 };
0796
0797 tmu_isp: tmu@1007c000 {
0798 compatible = "samsung,exynos5433-tmu";
0799 reg = <0x1007c000 0x200>;
0800 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0801 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
0802 <&cmu_peris CLK_SCLK_TMU1>;
0803 clock-names = "tmu_apbif", "tmu_sclk";
0804 #thermal-sensor-cells = <0>;
0805 status = "disabled";
0806 };
0807
0808 timer@101c0000 {
0809 compatible = "samsung,exynos5433-mct",
0810 "samsung,exynos4210-mct";
0811 reg = <0x101c0000 0x800>;
0812 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0813 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0814 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0815 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0816 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0817 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0818 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0819 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0820 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0821 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0822 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0823 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0824 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
0825 clock-names = "fin_pll", "mct";
0826 };
0827
0828 ppmu_d0_cpu: ppmu@10480000 {
0829 compatible = "samsung,exynos-ppmu-v2";
0830 reg = <0x10480000 0x2000>;
0831 status = "disabled";
0832 };
0833
0834 ppmu_d0_general: ppmu@10490000 {
0835 compatible = "samsung,exynos-ppmu-v2";
0836 reg = <0x10490000 0x2000>;
0837 status = "disabled";
0838 };
0839
0840 ppmu_d1_cpu: ppmu@104b0000 {
0841 compatible = "samsung,exynos-ppmu-v2";
0842 reg = <0x104b0000 0x2000>;
0843 status = "disabled";
0844 };
0845
0846 ppmu_d1_general: ppmu@104c0000 {
0847 compatible = "samsung,exynos-ppmu-v2";
0848 reg = <0x104c0000 0x2000>;
0849 status = "disabled";
0850 };
0851
0852 pinctrl_alive: pinctrl@10580000 {
0853 compatible = "samsung,exynos5433-pinctrl";
0854 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
0855
0856 wakeup-interrupt-controller {
0857 compatible = "samsung,exynos7-wakeup-eint";
0858 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0859 };
0860 };
0861
0862 pinctrl_aud: pinctrl@114b0000 {
0863 compatible = "samsung,exynos5433-pinctrl";
0864 reg = <0x114b0000 0x1000>;
0865 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0866 power-domains = <&pd_aud>;
0867 };
0868
0869 pinctrl_cpif: pinctrl@10fe0000 {
0870 compatible = "samsung,exynos5433-pinctrl";
0871 reg = <0x10fe0000 0x1000>;
0872 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0873 };
0874
0875 pinctrl_ese: pinctrl@14ca0000 {
0876 compatible = "samsung,exynos5433-pinctrl";
0877 reg = <0x14ca0000 0x1000>;
0878 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
0879 };
0880
0881 pinctrl_finger: pinctrl@14cb0000 {
0882 compatible = "samsung,exynos5433-pinctrl";
0883 reg = <0x14cb0000 0x1000>;
0884 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
0885 };
0886
0887 pinctrl_fsys: pinctrl@15690000 {
0888 compatible = "samsung,exynos5433-pinctrl";
0889 reg = <0x15690000 0x1000>;
0890 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
0891 };
0892
0893 pinctrl_imem: pinctrl@11090000 {
0894 compatible = "samsung,exynos5433-pinctrl";
0895 reg = <0x11090000 0x1000>;
0896 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
0897 };
0898
0899 pinctrl_nfc: pinctrl@14cd0000 {
0900 compatible = "samsung,exynos5433-pinctrl";
0901 reg = <0x14cd0000 0x1000>;
0902 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
0903 };
0904
0905 pinctrl_peric: pinctrl@14cc0000 {
0906 compatible = "samsung,exynos5433-pinctrl";
0907 reg = <0x14cc0000 0x1100>;
0908 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
0909 };
0910
0911 pinctrl_touch: pinctrl@14ce0000 {
0912 compatible = "samsung,exynos5433-pinctrl";
0913 reg = <0x14ce0000 0x1100>;
0914 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
0915 };
0916
0917 pmu_system_controller: system-controller@105c0000 {
0918 compatible = "samsung,exynos5433-pmu", "syscon";
0919 reg = <0x105c0000 0x5008>;
0920 #clock-cells = <1>;
0921 clock-names = "clkout16";
0922 clocks = <&xxti>;
0923
0924 reboot: syscon-reboot {
0925 compatible = "syscon-reboot";
0926 regmap = <&pmu_system_controller>;
0927 offset = <0x400>; /* SWRESET */
0928 mask = <0x1>;
0929 };
0930 };
0931
0932 gic: interrupt-controller@11001000 {
0933 compatible = "arm,gic-400";
0934 #interrupt-cells = <3>;
0935 interrupt-controller;
0936 reg = <0x11001000 0x1000>,
0937 <0x11002000 0x2000>,
0938 <0x11004000 0x2000>,
0939 <0x11006000 0x2000>;
0940 interrupts = <GIC_PPI 9 0xf04>;
0941 };
0942
0943 mipi_phy: video-phy {
0944 compatible = "samsung,exynos5433-mipi-video-phy";
0945 #phy-cells = <1>;
0946 samsung,pmu-syscon = <&pmu_system_controller>;
0947 samsung,cam0-sysreg = <&syscon_cam0>;
0948 samsung,cam1-sysreg = <&syscon_cam1>;
0949 samsung,disp-sysreg = <&syscon_disp>;
0950 };
0951
0952 decon: decon@13800000 {
0953 compatible = "samsung,exynos5433-decon";
0954 reg = <0x13800000 0x2104>;
0955 clocks = <&cmu_disp CLK_PCLK_DECON>,
0956 <&cmu_disp CLK_ACLK_DECON>,
0957 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
0958 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
0959 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
0960 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
0961 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
0962 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
0963 <&cmu_disp CLK_SCLK_DECON_VCLK>,
0964 <&cmu_disp CLK_SCLK_DECON_ECLK>,
0965 <&cmu_disp CLK_SCLK_DSD>;
0966 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
0967 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
0968 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
0969 "pclk_smmu_decon1x", "sclk_decon_vclk",
0970 "sclk_decon_eclk", "dsd";
0971 power-domains = <&pd_disp>;
0972 interrupt-names = "fifo", "vsync", "lcd_sys";
0973 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0974 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0975 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0976 samsung,disp-sysreg = <&syscon_disp>;
0977 status = "disabled";
0978 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
0979 iommu-names = "m0", "m1";
0980
0981 ports {
0982 #address-cells = <1>;
0983 #size-cells = <0>;
0984
0985 port@0 {
0986 reg = <0>;
0987 decon_to_mic: endpoint {
0988 remote-endpoint =
0989 <&mic_to_decon>;
0990 };
0991 };
0992 };
0993 };
0994
0995 decon_tv: decon@13880000 {
0996 compatible = "samsung,exynos5433-decon-tv";
0997 reg = <0x13880000 0x20b8>;
0998 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
0999 <&cmu_disp CLK_ACLK_DECON_TV>,
1000 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1001 <&cmu_disp CLK_ACLK_XIU_TV0X>,
1002 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1003 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1004 <&cmu_disp CLK_ACLK_XIU_TV1X>,
1005 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1006 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
1007 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
1008 <&cmu_disp CLK_SCLK_DSD>;
1009 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1010 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
1011 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
1012 "pclk_smmu_decon1x", "sclk_decon_vclk",
1013 "sclk_decon_eclk", "dsd";
1014 samsung,disp-sysreg = <&syscon_disp>;
1015 power-domains = <&pd_disp>;
1016 interrupt-names = "fifo", "vsync", "lcd_sys";
1017 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1020 status = "disabled";
1021 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
1022 iommu-names = "m0", "m1";
1023 };
1024
1025 dsi: dsi@13900000 {
1026 compatible = "samsung,exynos5433-mipi-dsi";
1027 reg = <0x13900000 0xC0>;
1028 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1029 phys = <&mipi_phy 1>;
1030 phy-names = "dsim";
1031 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
1032 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
1033 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
1034 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
1035 <&cmu_disp CLK_SCLK_DSIM0>;
1036 clock-names = "bus_clk",
1037 "phyclk_mipidphy0_bitclkdiv8",
1038 "phyclk_mipidphy0_rxclkesc0",
1039 "sclk_rgb_vclk_to_dsim0",
1040 "sclk_mipi";
1041 power-domains = <&pd_disp>;
1042 status = "disabled";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045
1046 ports {
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049
1050 port@0 {
1051 reg = <0>;
1052 dsi_to_mic: endpoint {
1053 remote-endpoint = <&mic_to_dsi>;
1054 };
1055 };
1056 };
1057 };
1058
1059 mic: mic@13930000 {
1060 compatible = "samsung,exynos5433-mic";
1061 reg = <0x13930000 0x48>;
1062 clocks = <&cmu_disp CLK_PCLK_MIC0>,
1063 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1064 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1065 power-domains = <&pd_disp>;
1066 samsung,disp-syscon = <&syscon_disp>;
1067 status = "disabled";
1068
1069 ports {
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072
1073 port@0 {
1074 reg = <0>;
1075 mic_to_decon: endpoint {
1076 remote-endpoint =
1077 <&decon_to_mic>;
1078 };
1079 };
1080
1081 port@1 {
1082 reg = <1>;
1083 mic_to_dsi: endpoint {
1084 remote-endpoint = <&dsi_to_mic>;
1085 };
1086 };
1087 };
1088 };
1089
1090 hdmi: hdmi@13970000 {
1091 compatible = "samsung,exynos5433-hdmi";
1092 reg = <0x13970000 0x70000>;
1093 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&cmu_disp CLK_PCLK_HDMI>,
1095 <&cmu_disp CLK_PCLK_HDMIPHY>,
1096 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1097 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1098 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1099 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1100 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1101 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1102 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1103 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1104 "i_tmds_clk", "i_pixel_clk",
1105 "tmds_clko", "tmds_clko_user",
1106 "pixel_clko", "pixel_clko_user",
1107 "oscclk", "i_spdif_clk";
1108 phy = <&hdmiphy>;
1109 ddc = <&hsi2c_11>;
1110 samsung,syscon-phandle = <&pmu_system_controller>;
1111 samsung,sysreg-phandle = <&syscon_disp>;
1112 #sound-dai-cells = <0>;
1113 status = "disabled";
1114 };
1115
1116 hdmiphy: hdmiphy@13af0000 {
1117 reg = <0x13af0000 0x80>;
1118 };
1119
1120 syscon_disp: syscon@13b80000 {
1121 compatible = "samsung,exynos5433-sysreg", "syscon";
1122 reg = <0x13b80000 0x1010>;
1123 };
1124
1125 syscon_cam0: syscon@120f0000 {
1126 compatible = "samsung,exynos5433-sysreg", "syscon";
1127 reg = <0x120f0000 0x1020>;
1128 };
1129
1130 syscon_cam1: syscon@145f0000 {
1131 compatible = "samsung,exynos5433-sysreg", "syscon";
1132 reg = <0x145f0000 0x1038>;
1133 };
1134
1135 syscon_fsys: syscon@156f0000 {
1136 compatible = "samsung,exynos5433-sysreg", "syscon";
1137 reg = <0x156f0000 0x1044>;
1138 };
1139
1140 gsc_0: video-scaler@13c00000 {
1141 compatible = "samsung,exynos5433-gsc";
1142 reg = <0x13c00000 0x1000>;
1143 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1144 clock-names = "pclk", "aclk", "aclk_xiu",
1145 "aclk_gsclbend", "gsd";
1146 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1147 <&cmu_gscl CLK_ACLK_GSCL0>,
1148 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1149 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1150 <&cmu_gscl CLK_ACLK_GSD>;
1151 iommus = <&sysmmu_gscl0>;
1152 power-domains = <&pd_gscl>;
1153 };
1154
1155 gsc_1: video-scaler@13c10000 {
1156 compatible = "samsung,exynos5433-gsc";
1157 reg = <0x13c10000 0x1000>;
1158 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1159 clock-names = "pclk", "aclk", "aclk_xiu",
1160 "aclk_gsclbend", "gsd";
1161 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1162 <&cmu_gscl CLK_ACLK_GSCL1>,
1163 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1164 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1165 <&cmu_gscl CLK_ACLK_GSD>;
1166 iommus = <&sysmmu_gscl1>;
1167 power-domains = <&pd_gscl>;
1168 };
1169
1170 gsc_2: video-scaler@13c20000 {
1171 compatible = "samsung,exynos5433-gsc";
1172 reg = <0x13c20000 0x1000>;
1173 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1174 clock-names = "pclk", "aclk", "aclk_xiu",
1175 "aclk_gsclbend", "gsd";
1176 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1177 <&cmu_gscl CLK_ACLK_GSCL2>,
1178 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1179 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1180 <&cmu_gscl CLK_ACLK_GSD>;
1181 iommus = <&sysmmu_gscl2>;
1182 power-domains = <&pd_gscl>;
1183 };
1184
1185 gpu: gpu@14ac0000 {
1186 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1187 reg = <0x14ac0000 0x5000>;
1188 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1191 interrupt-names = "job", "mmu", "gpu";
1192 clocks = <&cmu_g3d CLK_ACLK_G3D>;
1193 clock-names = "core";
1194 power-domains = <&pd_g3d>;
1195 operating-points-v2 = <&gpu_opp_table>;
1196 status = "disabled";
1197
1198 gpu_opp_table: opp-table {
1199 compatible = "operating-points-v2";
1200
1201 opp-160000000 {
1202 opp-hz = /bits/ 64 <160000000>;
1203 opp-microvolt = <1000000>;
1204 };
1205 opp-267000000 {
1206 opp-hz = /bits/ 64 <267000000>;
1207 opp-microvolt = <1000000>;
1208 };
1209 opp-350000000 {
1210 opp-hz = /bits/ 64 <350000000>;
1211 opp-microvolt = <1025000>;
1212 };
1213 opp-420000000 {
1214 opp-hz = /bits/ 64 <420000000>;
1215 opp-microvolt = <1025000>;
1216 };
1217 opp-500000000 {
1218 opp-hz = /bits/ 64 <500000000>;
1219 opp-microvolt = <1075000>;
1220 };
1221 opp-550000000 {
1222 opp-hz = /bits/ 64 <550000000>;
1223 opp-microvolt = <1125000>;
1224 };
1225 opp-600000000 {
1226 opp-hz = /bits/ 64 <600000000>;
1227 opp-microvolt = <1150000>;
1228 };
1229 opp-700000000 {
1230 opp-hz = /bits/ 64 <700000000>;
1231 opp-microvolt = <1150000>;
1232 };
1233 };
1234 };
1235
1236 scaler_0: scaler@15000000 {
1237 compatible = "samsung,exynos5433-scaler";
1238 reg = <0x15000000 0x1294>;
1239 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1240 clock-names = "pclk", "aclk", "aclk_xiu";
1241 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1242 <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1243 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1244 iommus = <&sysmmu_scaler_0>;
1245 power-domains = <&pd_mscl>;
1246 };
1247
1248 scaler_1: scaler@15010000 {
1249 compatible = "samsung,exynos5433-scaler";
1250 reg = <0x15010000 0x1294>;
1251 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1252 clock-names = "pclk", "aclk", "aclk_xiu";
1253 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1254 <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1255 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1256 iommus = <&sysmmu_scaler_1>;
1257 power-domains = <&pd_mscl>;
1258 };
1259
1260 jpeg: codec@15020000 {
1261 compatible = "samsung,exynos5433-jpeg";
1262 reg = <0x15020000 0x10000>;
1263 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1264 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1265 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1266 <&cmu_mscl CLK_ACLK_JPEG>,
1267 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1268 <&cmu_mscl CLK_SCLK_JPEG>;
1269 iommus = <&sysmmu_jpeg>;
1270 power-domains = <&pd_mscl>;
1271 };
1272
1273 mfc: codec@152e0000 {
1274 compatible = "samsung,exynos5433-mfc";
1275 reg = <0x152E0000 0x10000>;
1276 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1277 clock-names = "pclk", "aclk", "aclk_xiu";
1278 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1279 <&cmu_mfc CLK_ACLK_MFC>,
1280 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1281 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1282 iommu-names = "left", "right";
1283 power-domains = <&pd_mfc>;
1284 };
1285
1286 sysmmu_decon0x: sysmmu@13a00000 {
1287 compatible = "samsung,exynos-sysmmu";
1288 reg = <0x13a00000 0x1000>;
1289 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1290 clock-names = "aclk", "pclk";
1291 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1292 <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
1293 power-domains = <&pd_disp>;
1294 #iommu-cells = <0>;
1295 };
1296
1297 sysmmu_decon1x: sysmmu@13a10000 {
1298 compatible = "samsung,exynos-sysmmu";
1299 reg = <0x13a10000 0x1000>;
1300 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1301 clock-names = "aclk", "pclk";
1302 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1303 <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
1304 #iommu-cells = <0>;
1305 power-domains = <&pd_disp>;
1306 };
1307
1308 sysmmu_tv0x: sysmmu@13a20000 {
1309 compatible = "samsung,exynos-sysmmu";
1310 reg = <0x13a20000 0x1000>;
1311 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-names = "aclk", "pclk";
1313 clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1314 <&cmu_disp CLK_PCLK_SMMU_TV0X>;
1315 #iommu-cells = <0>;
1316 power-domains = <&pd_disp>;
1317 };
1318
1319 sysmmu_tv1x: sysmmu@13a30000 {
1320 compatible = "samsung,exynos-sysmmu";
1321 reg = <0x13a30000 0x1000>;
1322 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1323 clock-names = "aclk", "pclk";
1324 clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1325 <&cmu_disp CLK_PCLK_SMMU_TV1X>;
1326 #iommu-cells = <0>;
1327 power-domains = <&pd_disp>;
1328 };
1329
1330 sysmmu_gscl0: sysmmu@13c80000 {
1331 compatible = "samsung,exynos-sysmmu";
1332 reg = <0x13C80000 0x1000>;
1333 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1334 clock-names = "aclk", "pclk";
1335 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1336 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1337 #iommu-cells = <0>;
1338 power-domains = <&pd_gscl>;
1339 };
1340
1341 sysmmu_gscl1: sysmmu@13c90000 {
1342 compatible = "samsung,exynos-sysmmu";
1343 reg = <0x13C90000 0x1000>;
1344 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1345 clock-names = "aclk", "pclk";
1346 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1347 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1348 #iommu-cells = <0>;
1349 power-domains = <&pd_gscl>;
1350 };
1351
1352 sysmmu_gscl2: sysmmu@13ca0000 {
1353 compatible = "samsung,exynos-sysmmu";
1354 reg = <0x13CA0000 0x1000>;
1355 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1356 clock-names = "aclk", "pclk";
1357 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1358 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1359 #iommu-cells = <0>;
1360 power-domains = <&pd_gscl>;
1361 };
1362
1363 sysmmu_scaler_0: sysmmu@15040000 {
1364 compatible = "samsung,exynos-sysmmu";
1365 reg = <0x15040000 0x1000>;
1366 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1367 clock-names = "aclk", "pclk";
1368 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1369 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
1370 #iommu-cells = <0>;
1371 power-domains = <&pd_mscl>;
1372 };
1373
1374 sysmmu_scaler_1: sysmmu@15050000 {
1375 compatible = "samsung,exynos-sysmmu";
1376 reg = <0x15050000 0x1000>;
1377 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1378 clock-names = "aclk", "pclk";
1379 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1380 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
1381 #iommu-cells = <0>;
1382 power-domains = <&pd_mscl>;
1383 };
1384
1385 sysmmu_jpeg: sysmmu@15060000 {
1386 compatible = "samsung,exynos-sysmmu";
1387 reg = <0x15060000 0x1000>;
1388 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1389 clock-names = "aclk", "pclk";
1390 clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1391 <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
1392 #iommu-cells = <0>;
1393 power-domains = <&pd_mscl>;
1394 };
1395
1396 sysmmu_mfc_0: sysmmu@15200000 {
1397 compatible = "samsung,exynos-sysmmu";
1398 reg = <0x15200000 0x1000>;
1399 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1400 clock-names = "aclk", "pclk";
1401 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1402 <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
1403 #iommu-cells = <0>;
1404 power-domains = <&pd_mfc>;
1405 };
1406
1407 sysmmu_mfc_1: sysmmu@15210000 {
1408 compatible = "samsung,exynos-sysmmu";
1409 reg = <0x15210000 0x1000>;
1410 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1411 clock-names = "aclk", "pclk";
1412 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1413 <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
1414 #iommu-cells = <0>;
1415 power-domains = <&pd_mfc>;
1416 };
1417
1418 serial_0: serial@14c10000 {
1419 compatible = "samsung,exynos5433-uart";
1420 reg = <0x14c10000 0x100>;
1421 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&cmu_peric CLK_PCLK_UART0>,
1423 <&cmu_peric CLK_SCLK_UART0>;
1424 clock-names = "uart", "clk_uart_baud0";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&uart0_bus>;
1427 status = "disabled";
1428 };
1429
1430 serial_1: serial@14c20000 {
1431 compatible = "samsung,exynos5433-uart";
1432 reg = <0x14c20000 0x100>;
1433 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cmu_peric CLK_PCLK_UART1>,
1435 <&cmu_peric CLK_SCLK_UART1>;
1436 clock-names = "uart", "clk_uart_baud0";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&uart1_bus>;
1439 status = "disabled";
1440 };
1441
1442 serial_2: serial@14c30000 {
1443 compatible = "samsung,exynos5433-uart";
1444 reg = <0x14c30000 0x100>;
1445 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1446 clocks = <&cmu_peric CLK_PCLK_UART2>,
1447 <&cmu_peric CLK_SCLK_UART2>;
1448 clock-names = "uart", "clk_uart_baud0";
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&uart2_bus>;
1451 status = "disabled";
1452 };
1453
1454 spi_0: spi@14d20000 {
1455 compatible = "samsung,exynos5433-spi";
1456 reg = <0x14d20000 0x100>;
1457 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1458 dmas = <&pdma0 9>, <&pdma0 8>;
1459 dma-names = "tx", "rx";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1462 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1463 <&cmu_peric CLK_SCLK_SPI0>,
1464 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1465 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1466 samsung,spi-src-clk = <0>;
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&spi0_bus>;
1469 num-cs = <1>;
1470 status = "disabled";
1471 };
1472
1473 spi_1: spi@14d30000 {
1474 compatible = "samsung,exynos5433-spi";
1475 reg = <0x14d30000 0x100>;
1476 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1477 dmas = <&pdma0 11>, <&pdma0 10>;
1478 dma-names = "tx", "rx";
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1481 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1482 <&cmu_peric CLK_SCLK_SPI1>,
1483 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1484 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1485 samsung,spi-src-clk = <0>;
1486 pinctrl-names = "default";
1487 pinctrl-0 = <&spi1_bus>;
1488 num-cs = <1>;
1489 status = "disabled";
1490 };
1491
1492 spi_2: spi@14d40000 {
1493 compatible = "samsung,exynos5433-spi";
1494 reg = <0x14d40000 0x100>;
1495 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1496 dmas = <&pdma0 13>, <&pdma0 12>;
1497 dma-names = "tx", "rx";
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1501 <&cmu_peric CLK_SCLK_SPI2>,
1502 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1503 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1504 samsung,spi-src-clk = <0>;
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&spi2_bus>;
1507 num-cs = <1>;
1508 status = "disabled";
1509 };
1510
1511 spi_3: spi@14d50000 {
1512 compatible = "samsung,exynos5433-spi";
1513 reg = <0x14d50000 0x100>;
1514 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1515 dmas = <&pdma0 23>, <&pdma0 22>;
1516 dma-names = "tx", "rx";
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1520 <&cmu_peric CLK_SCLK_SPI3>,
1521 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1522 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1523 samsung,spi-src-clk = <0>;
1524 pinctrl-names = "default";
1525 pinctrl-0 = <&spi3_bus>;
1526 num-cs = <1>;
1527 status = "disabled";
1528 };
1529
1530 spi_4: spi@14d00000 {
1531 compatible = "samsung,exynos5433-spi";
1532 reg = <0x14d00000 0x100>;
1533 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1534 dmas = <&pdma0 25>, <&pdma0 24>;
1535 dma-names = "tx", "rx";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1538 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1539 <&cmu_peric CLK_SCLK_SPI4>,
1540 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1541 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1542 samsung,spi-src-clk = <0>;
1543 pinctrl-names = "default";
1544 pinctrl-0 = <&spi4_bus>;
1545 num-cs = <1>;
1546 status = "disabled";
1547 };
1548
1549 adc: adc@14d10000 {
1550 compatible = "samsung,exynos7-adc";
1551 reg = <0x14d10000 0x100>;
1552 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1553 clock-names = "adc";
1554 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1555 #io-channel-cells = <1>;
1556 status = "disabled";
1557 };
1558
1559 i2s1: i2s@14d60000 {
1560 compatible = "samsung,exynos7-i2s";
1561 reg = <0x14d60000 0x100>;
1562 dmas = <&pdma0 31>, <&pdma0 30>;
1563 dma-names = "tx", "rx";
1564 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1565 clocks = <&cmu_peric CLK_PCLK_I2S1>,
1566 <&cmu_peric CLK_PCLK_I2S1>,
1567 <&cmu_peric CLK_SCLK_I2S1>;
1568 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1569 #clock-cells = <1>;
1570 #sound-dai-cells = <1>;
1571 status = "disabled";
1572 };
1573
1574 pwm: pwm@14dd0000 {
1575 compatible = "samsung,exynos4210-pwm";
1576 reg = <0x14dd0000 0x100>;
1577 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1580 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1582 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1583 clocks = <&cmu_peric CLK_PCLK_PWM>;
1584 clock-names = "timers";
1585 #pwm-cells = <3>;
1586 status = "disabled";
1587 };
1588
1589 hsi2c_0: i2c@14e40000 {
1590 compatible = "samsung,exynos7-hsi2c";
1591 reg = <0x14e40000 0x1000>;
1592 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&hs_i2c0_bus>;
1597 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1598 clock-names = "hsi2c";
1599 status = "disabled";
1600 };
1601
1602 hsi2c_1: i2c@14e50000 {
1603 compatible = "samsung,exynos7-hsi2c";
1604 reg = <0x14e50000 0x1000>;
1605 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&hs_i2c1_bus>;
1610 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1611 clock-names = "hsi2c";
1612 status = "disabled";
1613 };
1614
1615 hsi2c_2: i2c@14e60000 {
1616 compatible = "samsung,exynos7-hsi2c";
1617 reg = <0x14e60000 0x1000>;
1618 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&hs_i2c2_bus>;
1623 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1624 clock-names = "hsi2c";
1625 status = "disabled";
1626 };
1627
1628 hsi2c_3: i2c@14e70000 {
1629 compatible = "samsung,exynos7-hsi2c";
1630 reg = <0x14e70000 0x1000>;
1631 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1634 pinctrl-names = "default";
1635 pinctrl-0 = <&hs_i2c3_bus>;
1636 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1637 clock-names = "hsi2c";
1638 status = "disabled";
1639 };
1640
1641 hsi2c_4: i2c@14ec0000 {
1642 compatible = "samsung,exynos7-hsi2c";
1643 reg = <0x14ec0000 0x1000>;
1644 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&hs_i2c4_bus>;
1649 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1650 clock-names = "hsi2c";
1651 status = "disabled";
1652 };
1653
1654 hsi2c_5: i2c@14ed0000 {
1655 compatible = "samsung,exynos7-hsi2c";
1656 reg = <0x14ed0000 0x1000>;
1657 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1660 pinctrl-names = "default";
1661 pinctrl-0 = <&hs_i2c5_bus>;
1662 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1663 clock-names = "hsi2c";
1664 status = "disabled";
1665 };
1666
1667 hsi2c_6: i2c@14ee0000 {
1668 compatible = "samsung,exynos7-hsi2c";
1669 reg = <0x14ee0000 0x1000>;
1670 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1673 pinctrl-names = "default";
1674 pinctrl-0 = <&hs_i2c6_bus>;
1675 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1676 clock-names = "hsi2c";
1677 status = "disabled";
1678 };
1679
1680 hsi2c_7: i2c@14ef0000 {
1681 compatible = "samsung,exynos7-hsi2c";
1682 reg = <0x14ef0000 0x1000>;
1683 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&hs_i2c7_bus>;
1688 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1689 clock-names = "hsi2c";
1690 status = "disabled";
1691 };
1692
1693 hsi2c_8: i2c@14d90000 {
1694 compatible = "samsung,exynos7-hsi2c";
1695 reg = <0x14d90000 0x1000>;
1696 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&hs_i2c8_bus>;
1701 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1702 clock-names = "hsi2c";
1703 status = "disabled";
1704 };
1705
1706 hsi2c_9: i2c@14da0000 {
1707 compatible = "samsung,exynos7-hsi2c";
1708 reg = <0x14da0000 0x1000>;
1709 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1712 pinctrl-names = "default";
1713 pinctrl-0 = <&hs_i2c9_bus>;
1714 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1715 clock-names = "hsi2c";
1716 status = "disabled";
1717 };
1718
1719 hsi2c_10: i2c@14de0000 {
1720 compatible = "samsung,exynos7-hsi2c";
1721 reg = <0x14de0000 0x1000>;
1722 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1725 pinctrl-names = "default";
1726 pinctrl-0 = <&hs_i2c10_bus>;
1727 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1728 clock-names = "hsi2c";
1729 status = "disabled";
1730 };
1731
1732 hsi2c_11: i2c@14df0000 {
1733 compatible = "samsung,exynos7-hsi2c";
1734 reg = <0x14df0000 0x1000>;
1735 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&hs_i2c11_bus>;
1740 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1741 clock-names = "hsi2c";
1742 status = "disabled";
1743 };
1744
1745 usbdrd30: usbdrd {
1746 compatible = "samsung,exynos5433-dwusb3";
1747 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1748 <&cmu_fsys CLK_SCLK_USBDRD30>,
1749 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1750 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1751 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1752 #address-cells = <1>;
1753 #size-cells = <1>;
1754 ranges;
1755 status = "disabled";
1756
1757 usbdrd_dwc3: usb@15400000 {
1758 compatible = "snps,dwc3";
1759 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1760 <&cmu_fsys CLK_ACLK_USBDRD30>,
1761 <&cmu_fsys CLK_SCLK_USBDRD30>;
1762 clock-names = "ref", "bus_early", "suspend";
1763 reg = <0x15400000 0x10000>;
1764 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1765 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1766 phy-names = "usb2-phy", "usb3-phy";
1767 };
1768 };
1769
1770 usbdrd30_phy: phy@15500000 {
1771 compatible = "samsung,exynos5433-usbdrd-phy";
1772 reg = <0x15500000 0x100>;
1773 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1774 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1775 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1776 <&cmu_fsys CLK_SCLK_USBDRD30>;
1777 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1778 "itp";
1779 #phy-cells = <1>;
1780 samsung,pmu-syscon = <&pmu_system_controller>;
1781 status = "disabled";
1782 };
1783
1784 usbhost30_phy: phy@15580000 {
1785 compatible = "samsung,exynos5433-usbdrd-phy";
1786 reg = <0x15580000 0x100>;
1787 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1788 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1789 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1790 <&cmu_fsys CLK_SCLK_USBHOST30>;
1791 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1792 "itp";
1793 #phy-cells = <1>;
1794 samsung,pmu-syscon = <&pmu_system_controller>;
1795 status = "disabled";
1796 };
1797
1798 usbhost30: usbhost {
1799 compatible = "samsung,exynos5433-dwusb3";
1800 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1801 <&cmu_fsys CLK_SCLK_USBHOST30>,
1802 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1803 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1804 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1805 #address-cells = <1>;
1806 #size-cells = <1>;
1807 ranges;
1808 status = "disabled";
1809
1810 usbhost_dwc3: usb@15a00000 {
1811 compatible = "snps,dwc3";
1812 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1813 <&cmu_fsys CLK_ACLK_USBHOST30>,
1814 <&cmu_fsys CLK_SCLK_USBHOST30>;
1815 clock-names = "ref", "bus_early", "suspend";
1816 reg = <0x15a00000 0x10000>;
1817 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1818 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1819 phy-names = "usb2-phy", "usb3-phy";
1820 };
1821 };
1822
1823 mshc_0: mmc@15540000 {
1824 compatible = "samsung,exynos7-dw-mshc-smu";
1825 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 reg = <0x15540000 0x2000>;
1829 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1830 <&cmu_fsys CLK_SCLK_MMC0>;
1831 clock-names = "biu", "ciu";
1832 fifo-depth = <0x40>;
1833 status = "disabled";
1834 };
1835
1836 mshc_1: mmc@15550000 {
1837 compatible = "samsung,exynos7-dw-mshc-smu";
1838 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1841 reg = <0x15550000 0x2000>;
1842 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1843 <&cmu_fsys CLK_SCLK_MMC1>;
1844 clock-names = "biu", "ciu";
1845 fifo-depth = <0x40>;
1846 status = "disabled";
1847 };
1848
1849 mshc_2: mmc@15560000 {
1850 compatible = "samsung,exynos7-dw-mshc-smu";
1851 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1854 reg = <0x15560000 0x2000>;
1855 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1856 <&cmu_fsys CLK_SCLK_MMC2>;
1857 clock-names = "biu", "ciu";
1858 fifo-depth = <0x40>;
1859 status = "disabled";
1860 };
1861
1862 pdma0: dma-controller@15610000 {
1863 compatible = "arm,pl330", "arm,primecell";
1864 reg = <0x15610000 0x1000>;
1865 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1866 clocks = <&cmu_fsys CLK_PDMA0>;
1867 clock-names = "apb_pclk";
1868 #dma-cells = <1>;
1869 };
1870
1871 pdma1: dma-controller@15600000 {
1872 compatible = "arm,pl330", "arm,primecell";
1873 reg = <0x15600000 0x1000>;
1874 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1875 clocks = <&cmu_fsys CLK_PDMA1>;
1876 clock-names = "apb_pclk";
1877 #dma-cells = <1>;
1878 };
1879
1880 audio-subsystem@11400000 {
1881 compatible = "samsung,exynos5433-lpass";
1882 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1883 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1884 clock-names = "sfr0_ctrl";
1885 power-domains = <&pd_aud>;
1886 #address-cells = <1>;
1887 #size-cells = <1>;
1888 ranges;
1889
1890 adma: dma-controller@11420000 {
1891 compatible = "arm,pl330", "arm,primecell";
1892 reg = <0x11420000 0x1000>;
1893 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1894 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1895 clock-names = "apb_pclk";
1896 #dma-cells = <1>;
1897 power-domains = <&pd_aud>;
1898 };
1899
1900 i2s0: i2s@11440000 {
1901 compatible = "samsung,exynos7-i2s";
1902 reg = <0x11440000 0x100>;
1903 dmas = <&adma 0>, <&adma 2>;
1904 dma-names = "tx", "rx";
1905 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1908 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1909 <&cmu_aud CLK_SCLK_AUD_I2S>,
1910 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1911 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1912 #clock-cells = <1>;
1913 pinctrl-names = "default";
1914 pinctrl-0 = <&i2s0_bus>;
1915 power-domains = <&pd_aud>;
1916 #sound-dai-cells = <1>;
1917 status = "disabled";
1918 };
1919
1920 serial_3: serial@11460000 {
1921 compatible = "samsung,exynos5433-uart";
1922 reg = <0x11460000 0x100>;
1923 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1925 <&cmu_aud CLK_SCLK_AUD_UART>;
1926 clock-names = "uart", "clk_uart_baud0";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&uart_aud_bus>;
1929 power-domains = <&pd_aud>;
1930 status = "disabled";
1931 };
1932 };
1933
1934 pcie_phy: pcie-phy@15680000 {
1935 compatible = "samsung,exynos5433-pcie-phy";
1936 reg = <0x15680000 0x1000>;
1937 samsung,pmu-syscon = <&pmu_system_controller>;
1938 samsung,fsys-sysreg = <&syscon_fsys>;
1939 #phy-cells = <0>;
1940 status = "disabled";
1941 };
1942
1943 pcie: pcie@15700000 {
1944 compatible = "samsung,exynos5433-pcie";
1945 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1946 <0x0c000000 0x1000>;
1947 reg-names = "dbi", "elbi", "config";
1948 #address-cells = <3>;
1949 #size-cells = <2>;
1950 #interrupt-cells = <1>;
1951 device_type = "pci";
1952 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1953 clocks = <&cmu_fsys CLK_PCIE>,
1954 <&cmu_fsys CLK_PCLK_PCIE_PHY>;
1955 clock-names = "pcie", "pcie_bus";
1956 num-lanes = <1>;
1957 num-viewport = <3>;
1958 bus-range = <0x00 0xff>;
1959 phys = <&pcie_phy>;
1960 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1961 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
1962 status = "disabled";
1963 };
1964 };
1965
1966 timer: timer {
1967 compatible = "arm,armv8-timer";
1968 interrupts = <GIC_PPI 13
1969 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1970 <GIC_PPI 14
1971 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1972 <GIC_PPI 11
1973 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1974 <GIC_PPI 10
1975 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1976 };
1977 };
1978
1979 #include "exynos5433-bus.dtsi"
1980 #include "exynos5433-pinctrl.dtsi"
1981 #include "exynos5433-tmu.dtsi"
