0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * dtsi file for Cavium ThunderX2 CN99XX processor
0004 *
0005 * Copyright (c) 2017 Cavium Inc.
0006 * Copyright (c) 2013-2016 Broadcom
0007 * Author: Zi Shen Lim <zlim@broadcom.com>
0008 */
0009
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 / {
0013 model = "Cavium ThunderX2 CN99XX";
0014 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 /* just 4 cpus now, 128 needed in full config */
0020 cpus {
0021 #address-cells = <0x2>;
0022 #size-cells = <0x0>;
0023
0024 cpu@0 {
0025 device_type = "cpu";
0026 compatible = "cavium,thunder2", "brcm,vulcan";
0027 reg = <0x0 0x0>;
0028 enable-method = "psci";
0029 };
0030
0031 cpu@1 {
0032 device_type = "cpu";
0033 compatible = "cavium,thunder2", "brcm,vulcan";
0034 reg = <0x0 0x1>;
0035 enable-method = "psci";
0036 };
0037
0038 cpu@2 {
0039 device_type = "cpu";
0040 compatible = "cavium,thunder2", "brcm,vulcan";
0041 reg = <0x0 0x2>;
0042 enable-method = "psci";
0043 };
0044
0045 cpu@3 {
0046 device_type = "cpu";
0047 compatible = "cavium,thunder2", "brcm,vulcan";
0048 reg = <0x0 0x3>;
0049 enable-method = "psci";
0050 };
0051 };
0052
0053 psci {
0054 compatible = "arm,psci-0.2";
0055 method = "smc";
0056 };
0057
0058 gic: interrupt-controller@400080000 {
0059 compatible = "arm,gic-v3";
0060 #interrupt-cells = <3>;
0061 #address-cells = <2>;
0062 #size-cells = <2>;
0063 ranges;
0064 interrupt-controller;
0065 #redistributor-regions = <1>;
0066 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
0067 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
0068 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0069
0070 gicits: gic-its@40010000 {
0071 compatible = "arm,gic-v3-its";
0072 msi-controller;
0073 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
0074 };
0075 };
0076
0077 timer {
0078 compatible = "arm,armv8-timer";
0079 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
0083 };
0084
0085 pmu {
0086 compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
0087 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
0088 };
0089
0090 clk125mhz: uart_clk125mhz {
0091 compatible = "fixed-clock";
0092 #clock-cells = <0>;
0093 clock-frequency = <125000000>;
0094 clock-output-names = "clk125mhz";
0095 };
0096
0097 pcie@30000000 {
0098 compatible = "pci-host-ecam-generic";
0099 device_type = "pci";
0100 #interrupt-cells = <1>;
0101 #address-cells = <3>;
0102 #size-cells = <2>;
0103
0104 /* ECAM at 0x3000_0000 - 0x4000_0000 */
0105 reg = <0x0 0x30000000 0x0 0x10000000>;
0106 reg-names = "PCI ECAM";
0107
0108 /*
0109 * PCI ranges:
0110 * IO no supported
0111 * MEM 0x4000_0000 - 0x6000_0000
0112 * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
0113 */
0114 ranges =
0115 <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
0116 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
0117 bus-range = <0 0xff>;
0118 interrupt-map-mask = <0 0 0 7>;
0119 interrupt-map =
0120 /* addr pin ic icaddr icintr */
0121 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
0122 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
0123 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
0124 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0125 msi-parent = <&gicits>;
0126 dma-coherent;
0127 };
0128
0129 soc {
0130 compatible = "simple-bus";
0131 #address-cells = <2>;
0132 #size-cells = <2>;
0133 ranges;
0134
0135 uart0: serial@402020000 {
0136 compatible = "arm,pl011", "arm,primecell";
0137 reg = <0x04 0x02020000 0x0 0x1000>;
0138 interrupt-parent = <&gic>;
0139 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0140 clocks = <&clk125mhz>;
0141 clock-names = "apb_pclk";
0142 };
0143 };
0144
0145 };
