0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 #include <dt-bindings/interrupt-controller/arm-gic.h>
0034
0035 / {
0036 compatible = "brcm,stingray";
0037 interrupt-parent = <&gic>;
0038 #address-cells = <2>;
0039 #size-cells = <2>;
0040
0041 cpus {
0042 #address-cells = <2>;
0043 #size-cells = <0>;
0044
0045 cpu@0 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a72";
0048 reg = <0x0 0x0>;
0049 enable-method = "psci";
0050 next-level-cache = <&CLUSTER0_L2>;
0051 };
0052
0053 cpu@1 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a72";
0056 reg = <0x0 0x1>;
0057 enable-method = "psci";
0058 next-level-cache = <&CLUSTER0_L2>;
0059 };
0060
0061 cpu@100 {
0062 device_type = "cpu";
0063 compatible = "arm,cortex-a72";
0064 reg = <0x0 0x100>;
0065 enable-method = "psci";
0066 next-level-cache = <&CLUSTER1_L2>;
0067 };
0068
0069 cpu@101 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a72";
0072 reg = <0x0 0x101>;
0073 enable-method = "psci";
0074 next-level-cache = <&CLUSTER1_L2>;
0075 };
0076
0077 cpu@200 {
0078 device_type = "cpu";
0079 compatible = "arm,cortex-a72";
0080 reg = <0x0 0x200>;
0081 enable-method = "psci";
0082 next-level-cache = <&CLUSTER2_L2>;
0083 };
0084
0085 cpu@201 {
0086 device_type = "cpu";
0087 compatible = "arm,cortex-a72";
0088 reg = <0x0 0x201>;
0089 enable-method = "psci";
0090 next-level-cache = <&CLUSTER2_L2>;
0091 };
0092
0093 cpu@300 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a72";
0096 reg = <0x0 0x300>;
0097 enable-method = "psci";
0098 next-level-cache = <&CLUSTER3_L2>;
0099 };
0100
0101 cpu@301 {
0102 device_type = "cpu";
0103 compatible = "arm,cortex-a72";
0104 reg = <0x0 0x301>;
0105 enable-method = "psci";
0106 next-level-cache = <&CLUSTER3_L2>;
0107 };
0108
0109 CLUSTER0_L2: l2-cache@0 {
0110 compatible = "cache";
0111 };
0112
0113 CLUSTER1_L2: l2-cache@100 {
0114 compatible = "cache";
0115 };
0116
0117 CLUSTER2_L2: l2-cache@200 {
0118 compatible = "cache";
0119 };
0120
0121 CLUSTER3_L2: l2-cache@300 {
0122 compatible = "cache";
0123 };
0124 };
0125
0126 memory: memory@80000000 {
0127 device_type = "memory";
0128 reg = <0x00000000 0x80000000 0 0x40000000>;
0129 };
0130
0131 psci {
0132 compatible = "arm,psci-0.2";
0133 method = "smc";
0134 };
0135
0136 pmu {
0137 compatible = "arm,armv8-pmuv3";
0138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0139 };
0140
0141 timer {
0142 compatible = "arm,armv8-timer";
0143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0147 };
0148
0149 mhb: syscon@60401000 {
0150 compatible = "brcm,sr-mhb", "syscon";
0151 reg = <0 0x60401000 0 0x38c>;
0152 };
0153
0154 scr {
0155 compatible = "simple-bus";
0156 #address-cells = <1>;
0157 #size-cells = <1>;
0158 ranges = <0x0 0x0 0x61000000 0x05000000>;
0159
0160 ccn: ccn@0 {
0161 compatible = "arm,ccn-502";
0162 reg = <0x00000000 0x900000>;
0163 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
0164 };
0165
0166 gic: interrupt-controller@2c00000 {
0167 compatible = "arm,gic-v3";
0168 #interrupt-cells = <3>;
0169 #address-cells = <1>;
0170 #size-cells = <1>;
0171 ranges;
0172 interrupt-controller;
0173 reg = <0x02c00000 0x010000>, /* GICD */
0174 <0x02e00000 0x600000>; /* GICR */
0175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0176
0177 gic_its: gic-its@63c20000 {
0178 compatible = "arm,gic-v3-its";
0179 msi-controller;
0180 #msi-cells = <1>;
0181 reg = <0x02c20000 0x10000>;
0182 };
0183 };
0184
0185 smmu: mmu@3000000 {
0186 compatible = "arm,mmu-500";
0187 reg = <0x03000000 0x80000>;
0188 #global-interrupts = <1>;
0189 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
0190 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
0191 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
0192 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
0193 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
0194 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
0195 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
0196 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
0197 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
0198 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
0199 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
0200 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
0201 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
0202 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
0203 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
0205 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
0206 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
0208 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
0209 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
0212 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
0213 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
0214 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
0227 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
0228 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
0229 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
0230 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
0232 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
0233 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
0234 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
0235 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
0236 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
0237 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
0238 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
0239 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
0240 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
0241 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
0242 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
0243 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
0244 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
0245 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
0246 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
0247 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
0248 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
0249 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
0250 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
0251 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
0252 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
0253 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
0254 #iommu-cells = <2>;
0255 };
0256 };
0257
0258 crmu: crmu {
0259 compatible = "simple-bus";
0260 #address-cells = <1>;
0261 #size-cells = <1>;
0262 ranges = <0x0 0x0 0x66400000 0x100000>;
0263
0264 #include "stingray-clock.dtsi"
0265
0266 otp: otp@1c400 {
0267 compatible = "brcm,ocotp-v2";
0268 reg = <0x0001c400 0x68>;
0269 brcm,ocotp-size = <2048>;
0270 status = "okay";
0271 };
0272
0273 cdru: syscon@1d000 {
0274 compatible = "brcm,sr-cdru", "syscon";
0275 reg = <0x0001d000 0x400>;
0276 };
0277
0278 gpio_crmu: gpio@24800 {
0279 compatible = "brcm,iproc-gpio";
0280 reg = <0x00024800 0x4c>;
0281 ngpios = <6>;
0282 #gpio-cells = <2>;
0283 gpio-controller;
0284 };
0285 };
0286
0287 #include "stingray-fs4.dtsi"
0288 #include "stingray-pcie.dtsi"
0289 #include "stingray-usb.dtsi"
0290
0291 hsls {
0292 compatible = "simple-bus";
0293 #address-cells = <1>;
0294 #size-cells = <1>;
0295 ranges = <0x0 0x0 0x68900000 0x17700000>;
0296
0297 #include "stingray-pinctrl.dtsi"
0298
0299 mdio_mux_iproc: mdio-mux@20000 {
0300 compatible = "brcm,mdio-mux-iproc";
0301 reg = <0x00020000 0x250>;
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304
0305 mdio@0 { /* PCIe serdes */
0306 reg = <0x0>;
0307 #address-cells = <1>;
0308 #size-cells = <0>;
0309 };
0310
0311 mdio@3 { /* USB */
0312 reg = <0x3>;
0313 #address-cells = <1>;
0314 #size-cells = <0>;
0315 };
0316
0317 mdio@10 { /* RGMII */
0318 reg = <0x10>;
0319 #address-cells = <1>;
0320 #size-cells = <0>;
0321 };
0322 };
0323
0324 pwm: pwm@10000 {
0325 compatible = "brcm,iproc-pwm";
0326 reg = <0x00010000 0x1000>;
0327 clocks = <&crmu_ref25m>;
0328 #pwm-cells = <3>;
0329 status = "disabled";
0330 };
0331
0332 timer0: timer@30000 {
0333 compatible = "arm,sp804", "arm,primecell";
0334 reg = <0x00030000 0x1000>;
0335 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0336 clocks = <&hsls_25m_div2_clk>,
0337 <&hsls_25m_div2_clk>,
0338 <&hsls_div4_clk>;
0339 clock-names = "timer1", "timer2", "apb_pclk";
0340 status = "disabled";
0341 };
0342
0343 timer1: timer@40000 {
0344 compatible = "arm,sp804", "arm,primecell";
0345 reg = <0x00040000 0x1000>;
0346 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0347 clocks = <&hsls_25m_div2_clk>,
0348 <&hsls_25m_div2_clk>,
0349 <&hsls_div4_clk>;
0350 clock-names = "timer1", "timer2", "apb_pclk";
0351 };
0352
0353 timer2: timer@50000 {
0354 compatible = "arm,sp804", "arm,primecell";
0355 reg = <0x00050000 0x1000>;
0356 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
0357 clocks = <&hsls_25m_div2_clk>,
0358 <&hsls_25m_div2_clk>,
0359 <&hsls_div4_clk>;
0360 clock-names = "timer1", "timer2", "apb_pclk";
0361 status = "disabled";
0362 };
0363
0364 timer3: timer@60000 {
0365 compatible = "arm,sp804", "arm,primecell";
0366 reg = <0x00060000 0x1000>;
0367 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
0368 clocks = <&hsls_25m_div2_clk>,
0369 <&hsls_25m_div2_clk>,
0370 <&hsls_div4_clk>;
0371 clock-names = "timer1", "timer2", "apb_pclk";
0372 status = "disabled";
0373 };
0374
0375 timer4: timer@70000 {
0376 compatible = "arm,sp804", "arm,primecell";
0377 reg = <0x00070000 0x1000>;
0378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
0379 clocks = <&hsls_25m_div2_clk>,
0380 <&hsls_25m_div2_clk>,
0381 <&hsls_div4_clk>;
0382 clock-names = "timer1", "timer2", "apb_pclk";
0383 status = "disabled";
0384 };
0385
0386 timer5: timer@80000 {
0387 compatible = "arm,sp804", "arm,primecell";
0388 reg = <0x00080000 0x1000>;
0389 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0390 clocks = <&hsls_25m_div2_clk>,
0391 <&hsls_25m_div2_clk>,
0392 <&hsls_div4_clk>;
0393 clock-names = "timer1", "timer2", "apb_pclk";
0394 status = "disabled";
0395 };
0396
0397 timer6: timer@90000 {
0398 compatible = "arm,sp804", "arm,primecell";
0399 reg = <0x00090000 0x1000>;
0400 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0401 clocks = <&hsls_25m_div2_clk>,
0402 <&hsls_25m_div2_clk>,
0403 <&hsls_div4_clk>;
0404 clock-names = "timer1", "timer2", "apb_pclk";
0405 status = "disabled";
0406 };
0407
0408 timer7: timer@a0000 {
0409 compatible = "arm,sp804", "arm,primecell";
0410 reg = <0x000a0000 0x1000>;
0411 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&hsls_25m_div2_clk>,
0413 <&hsls_25m_div2_clk>,
0414 <&hsls_div4_clk>;
0415 clock-names = "timer1", "timer2", "apb_pclk";
0416 status = "disabled";
0417 };
0418
0419 i2c0: i2c@b0000 {
0420 compatible = "brcm,iproc-i2c";
0421 reg = <0x000b0000 0x100>;
0422 #address-cells = <1>;
0423 #size-cells = <0>;
0424 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
0425 clock-frequency = <100000>;
0426 status = "disabled";
0427 };
0428
0429 wdt0: watchdog@c0000 {
0430 compatible = "arm,sp805", "arm,primecell";
0431 reg = <0x000c0000 0x1000>;
0432 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0433 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
0434 clock-names = "wdog_clk", "apb_pclk";
0435 timeout-sec = <60>;
0436 };
0437
0438 gpio_hsls: gpio@d0000 {
0439 compatible = "brcm,iproc-gpio";
0440 reg = <0x000d0000 0x864>;
0441 ngpios = <151>;
0442 #gpio-cells = <2>;
0443 gpio-controller;
0444 interrupt-controller;
0445 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0446 gpio-ranges = <&pinmux 0 0 16>,
0447 <&pinmux 16 71 2>,
0448 <&pinmux 18 131 8>,
0449 <&pinmux 26 83 6>,
0450 <&pinmux 32 123 4>,
0451 <&pinmux 36 43 24>,
0452 <&pinmux 60 89 2>,
0453 <&pinmux 62 73 4>,
0454 <&pinmux 66 95 28>,
0455 <&pinmux 94 127 4>,
0456 <&pinmux 98 139 10>,
0457 <&pinmux 108 16 27>,
0458 <&pinmux 135 77 6>,
0459 <&pinmux 141 67 4>,
0460 <&pinmux 145 149 6>;
0461 };
0462
0463 i2c1: i2c@e0000 {
0464 compatible = "brcm,iproc-i2c";
0465 reg = <0x000e0000 0x100>;
0466 #address-cells = <1>;
0467 #size-cells = <0>;
0468 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0469 clock-frequency = <100000>;
0470 status = "disabled";
0471 };
0472
0473 uart0: serial@100000 {
0474 device_type = "serial";
0475 compatible = "snps,dw-apb-uart";
0476 reg = <0x00100000 0x1000>;
0477 reg-shift = <2>;
0478 clock-frequency = <25000000>;
0479 interrupt-parent = <&gic>;
0480 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0481 status = "disabled";
0482 };
0483
0484 uart1: serial@110000 {
0485 device_type = "serial";
0486 compatible = "snps,dw-apb-uart";
0487 reg = <0x00110000 0x1000>;
0488 reg-shift = <2>;
0489 clock-frequency = <25000000>;
0490 interrupt-parent = <&gic>;
0491 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0492 status = "disabled";
0493 };
0494
0495 uart2: serial@120000 {
0496 device_type = "serial";
0497 compatible = "snps,dw-apb-uart";
0498 reg = <0x00120000 0x1000>;
0499 reg-shift = <2>;
0500 clock-frequency = <25000000>;
0501 interrupt-parent = <&gic>;
0502 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
0503 status = "disabled";
0504 };
0505
0506 uart3: serial@130000 {
0507 device_type = "serial";
0508 compatible = "snps,dw-apb-uart";
0509 reg = <0x00130000 0x1000>;
0510 reg-shift = <2>;
0511 clock-frequency = <25000000>;
0512 interrupt-parent = <&gic>;
0513 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0514 status = "disabled";
0515 };
0516
0517 ssp0: spi@180000 {
0518 compatible = "arm,pl022", "arm,primecell";
0519 reg = <0x00180000 0x1000>;
0520 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
0521 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
0522 clock-names = "sspclk", "apb_pclk";
0523 num-cs = <1>;
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 status = "disabled";
0527 };
0528
0529 ssp1: spi@190000 {
0530 compatible = "arm,pl022", "arm,primecell";
0531 reg = <0x00190000 0x1000>;
0532 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
0534 clock-names = "sspclk", "apb_pclk";
0535 num-cs = <1>;
0536 #address-cells = <1>;
0537 #size-cells = <0>;
0538 status = "disabled";
0539 };
0540
0541 hwrng: hwrng@220000 {
0542 compatible = "brcm,iproc-rng200";
0543 reg = <0x00220000 0x28>;
0544 };
0545
0546 dma0: dma-controller@310000 {
0547 compatible = "arm,pl330", "arm,primecell";
0548 reg = <0x00310000 0x1000>;
0549 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
0550 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
0551 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
0552 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
0553 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0554 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0555 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0556 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0557 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0558 #dma-cells = <1>;
0559 clocks = <&hsls_div2_clk>;
0560 clock-names = "apb_pclk";
0561 iommus = <&smmu 0x6000 0x0000>;
0562 };
0563
0564 enet: ethernet@340000{
0565 compatible = "brcm,amac";
0566 reg = <0x00340000 0x1000>;
0567 reg-names = "amac_base";
0568 dma-coherent;
0569 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
0570 status = "disabled";
0571 };
0572
0573 nand: nand@360000 {
0574 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
0575 reg = <0x00360000 0x600>,
0576 <0x0050a408 0x600>,
0577 <0x00360f00 0x20>;
0578 reg-names = "nand", "iproc-idm", "iproc-ext";
0579 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0580 #address-cells = <1>;
0581 #size-cells = <0>;
0582 brcm,nand-has-wp;
0583 status = "disabled";
0584 };
0585
0586 sdio0: sdhci@3f1000 {
0587 compatible = "brcm,sdhci-iproc";
0588 reg = <0x003f1000 0x100>;
0589 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
0590 bus-width = <8>;
0591 clocks = <&sdio0_clk>;
0592 iommus = <&smmu 0x6002 0x0000>;
0593 status = "disabled";
0594 };
0595
0596 sdio1: sdhci@3f2000 {
0597 compatible = "brcm,sdhci-iproc";
0598 reg = <0x003f2000 0x100>;
0599 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
0600 bus-width = <8>;
0601 clocks = <&sdio1_clk>;
0602 iommus = <&smmu 0x6003 0x0000>;
0603 status = "disabled";
0604 };
0605 };
0606
0607 tmons {
0608 compatible = "simple-bus";
0609 #address-cells = <1>;
0610 #size-cells = <1>;
0611 ranges = <0x0 0x0 0x8f100000 0x100>;
0612
0613 tmon: tmon@0 {
0614 compatible = "brcm,sr-thermal";
0615 reg = <0x0 0x40>;
0616 brcm,tmon-mask = <0x3f>;
0617 #thermal-sensor-cells = <1>;
0618 };
0619 };
0620
0621 thermal-zones {
0622 ihost0_thermal: ihost0-thermal {
0623 polling-delay-passive = <0>;
0624 polling-delay = <1000>;
0625 thermal-sensors = <&tmon 0>;
0626 trips {
0627 cpu-crit {
0628 temperature = <105000>;
0629 hysteresis = <0>;
0630 type = "critical";
0631 };
0632 };
0633 };
0634 ihost1_thermal: ihost1-thermal {
0635 polling-delay-passive = <0>;
0636 polling-delay = <1000>;
0637 thermal-sensors = <&tmon 1>;
0638 trips {
0639 cpu-crit {
0640 temperature = <105000>;
0641 hysteresis = <0>;
0642 type = "critical";
0643 };
0644 };
0645 };
0646 ihost2_thermal: ihost2-thermal {
0647 polling-delay-passive = <0>;
0648 polling-delay = <1000>;
0649 thermal-sensors = <&tmon 2>;
0650 trips {
0651 cpu-crit {
0652 temperature = <105000>;
0653 hysteresis = <0>;
0654 type = "critical";
0655 };
0656 };
0657 };
0658 ihost3_thermal: ihost3-thermal {
0659 polling-delay-passive = <0>;
0660 polling-delay = <1000>;
0661 thermal-sensors = <&tmon 3>;
0662 trips {
0663 cpu-crit {
0664 temperature = <105000>;
0665 hysteresis = <0>;
0666 type = "critical";
0667 };
0668 };
0669 };
0670 crmu_thermal: crmu-thermal {
0671 polling-delay-passive = <0>;
0672 polling-delay = <1000>;
0673 thermal-sensors = <&tmon 4>;
0674 trips {
0675 cpu-crit {
0676 temperature = <105000>;
0677 hysteresis = <0>;
0678 type = "critical";
0679 };
0680 };
0681 };
0682 nitro_thermal: nitro-thermal {
0683 polling-delay-passive = <0>;
0684 polling-delay = <1000>;
0685 thermal-sensors = <&tmon 5>;
0686 trips {
0687 cpu-crit {
0688 temperature = <105000>;
0689 hysteresis = <0>;
0690 type = "critical";
0691 };
0692 };
0693 };
0694 };
0695
0696 nic-hsls {
0697 compatible = "simple-bus";
0698 #address-cells = <1>;
0699 #size-cells = <1>;
0700 ranges = <0x0 0x0 0x0 0x7fffffff>;
0701
0702 nic_i2c0: i2c@60826100 {
0703 compatible = "brcm,iproc-nic-i2c";
0704 #address-cells = <1>;
0705 #size-cells = <0>;
0706 reg = <0x60826100 0x100>,
0707 <0x60e00408 0x1000>;
0708 brcm,ape-hsls-addr-mask = <0x03400000>;
0709 clock-frequency = <100000>;
0710 status = "disabled";
0711 };
0712 };
0713 };
