0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 #include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
0034
0035 pinconf: pinconf@140000 {
0036 compatible = "pinconf-single";
0037 reg = <0x00140000 0x250>;
0038 pinctrl-single,register-width = <32>;
0039
0040 /* pinconf functions */
0041 };
0042
0043 pinmux: pinmux@14029c {
0044 compatible = "pinctrl-single";
0045 reg = <0x0014029c 0x26c>;
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 pinctrl-single,register-width = <32>;
0049 pinctrl-single,function-mask = <0xf>;
0050 pinctrl-single,gpio-range = <
0051 &range 0 91 MODE_GPIO
0052 &range 95 60 MODE_GPIO
0053 >;
0054 range: gpio-range {
0055 #pinctrl-single,gpio-range-cells = <3>;
0056 };
0057
0058 /* pinctrl functions */
0059 tsio_pins: pinmux_gpio_14 {
0060 pinctrl-single,pins = <
0061 0x038 MODE_NITRO /* tsio_0 */
0062 0x03c MODE_NITRO /* tsio_1 */
0063 >;
0064 };
0065
0066 nor_pins: pinmux_pnor_adv_n {
0067 pinctrl-single,pins = <
0068 0x0ac MODE_PNOR /* nand_ce1_n */
0069 0x0b0 MODE_PNOR /* nand_ce0_n */
0070 0x0b4 MODE_PNOR /* nand_we_n */
0071 0x0b8 MODE_PNOR /* nand_wp_n */
0072 0x0bc MODE_PNOR /* nand_re_n */
0073 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
0074 0x0c4 MODE_PNOR /* nand_io0_0 */
0075 0x0c8 MODE_PNOR /* nand_io1_0 */
0076 0x0cc MODE_PNOR /* nand_io2_0 */
0077 0x0d0 MODE_PNOR /* nand_io3_0 */
0078 0x0d4 MODE_PNOR /* nand_io4_0 */
0079 0x0d8 MODE_PNOR /* nand_io5_0 */
0080 0x0dc MODE_PNOR /* nand_io6_0 */
0081 0x0e0 MODE_PNOR /* nand_io7_0 */
0082 0x0e4 MODE_PNOR /* nand_io8_0 */
0083 0x0e8 MODE_PNOR /* nand_io9_0 */
0084 0x0ec MODE_PNOR /* nand_io10_0 */
0085 0x0f0 MODE_PNOR /* nand_io11_0 */
0086 0x0f4 MODE_PNOR /* nand_io12_0 */
0087 0x0f8 MODE_PNOR /* nand_io13_0 */
0088 0x0fc MODE_PNOR /* nand_io14_0 */
0089 0x100 MODE_PNOR /* nand_io15_0 */
0090 0x104 MODE_PNOR /* nand_ale_0 */
0091 0x108 MODE_PNOR /* nand_cle_0 */
0092 0x040 MODE_PNOR /* pnor_adv_n */
0093 0x044 MODE_PNOR /* pnor_baa_n */
0094 0x048 MODE_PNOR /* pnor_bls_0_n */
0095 0x04c MODE_PNOR /* pnor_bls_1_n */
0096 0x050 MODE_PNOR /* pnor_cre */
0097 0x054 MODE_PNOR /* pnor_cs_2_n */
0098 0x058 MODE_PNOR /* pnor_cs_1_n */
0099 0x05c MODE_PNOR /* pnor_cs_0_n */
0100 0x060 MODE_PNOR /* pnor_we_n */
0101 0x064 MODE_PNOR /* pnor_oe_n */
0102 0x068 MODE_PNOR /* pnor_intr */
0103 0x06c MODE_PNOR /* pnor_dat_0 */
0104 0x070 MODE_PNOR /* pnor_dat_1 */
0105 0x074 MODE_PNOR /* pnor_dat_2 */
0106 0x078 MODE_PNOR /* pnor_dat_3 */
0107 0x07c MODE_PNOR /* pnor_dat_4 */
0108 0x080 MODE_PNOR /* pnor_dat_5 */
0109 0x084 MODE_PNOR /* pnor_dat_6 */
0110 0x088 MODE_PNOR /* pnor_dat_7 */
0111 0x08c MODE_PNOR /* pnor_dat_8 */
0112 0x090 MODE_PNOR /* pnor_dat_9 */
0113 0x094 MODE_PNOR /* pnor_dat_10 */
0114 0x098 MODE_PNOR /* pnor_dat_11 */
0115 0x09c MODE_PNOR /* pnor_dat_12 */
0116 0x0a0 MODE_PNOR /* pnor_dat_13 */
0117 0x0a4 MODE_PNOR /* pnor_dat_14 */
0118 0x0a8 MODE_PNOR /* pnor_dat_15 */
0119 >;
0120 };
0121
0122 nand_pins: pinmux_nand_ce1_n {
0123 pinctrl-single,pins = <
0124 0x0ac MODE_NAND /* nand_ce1_n */
0125 0x0b0 MODE_NAND /* nand_ce0_n */
0126 0x0b4 MODE_NAND /* nand_we_n */
0127 0x0b8 MODE_NAND /* nand_wp_n */
0128 0x0bc MODE_NAND /* nand_re_n */
0129 0x0c0 MODE_NAND /* nand_rdy_bsy_n */
0130 0x0c4 MODE_NAND /* nand_io0_0 */
0131 0x0c8 MODE_NAND /* nand_io1_0 */
0132 0x0cc MODE_NAND /* nand_io2_0 */
0133 0x0d0 MODE_NAND /* nand_io3_0 */
0134 0x0d4 MODE_NAND /* nand_io4_0 */
0135 0x0d8 MODE_NAND /* nand_io5_0 */
0136 0x0dc MODE_NAND /* nand_io6_0 */
0137 0x0e0 MODE_NAND /* nand_io7_0 */
0138 0x0e4 MODE_NAND /* nand_io8_0 */
0139 0x0e8 MODE_NAND /* nand_io9_0 */
0140 0x0ec MODE_NAND /* nand_io10_0 */
0141 0x0f0 MODE_NAND /* nand_io11_0 */
0142 0x0f4 MODE_NAND /* nand_io12_0 */
0143 0x0f8 MODE_NAND /* nand_io13_0 */
0144 0x0fc MODE_NAND /* nand_io14_0 */
0145 0x100 MODE_NAND /* nand_io15_0 */
0146 0x104 MODE_NAND /* nand_ale_0 */
0147 0x108 MODE_NAND /* nand_cle_0 */
0148 >;
0149 };
0150
0151 pwm0_pins: pinmux_pwm_0 {
0152 pinctrl-single,pins = <
0153 0x10c MODE_NITRO
0154 >;
0155 };
0156
0157 pwm1_pins: pinmux_pwm_1 {
0158 pinctrl-single,pins = <
0159 0x110 MODE_NITRO
0160 >;
0161 };
0162
0163 pwm2_pins: pinmux_pwm_2 {
0164 pinctrl-single,pins = <
0165 0x114 MODE_NITRO
0166 >;
0167 };
0168
0169 pwm3_pins: pinmux_pwm_3 {
0170 pinctrl-single,pins = <
0171 0x118 MODE_NITRO
0172 >;
0173 };
0174
0175 dbu_rxd_pins: pinmux_uart1_sin_nitro {
0176 pinctrl-single,pins = <
0177 0x11c MODE_NITRO /* dbu_rxd */
0178 0x120 MODE_NITRO /* dbu_txd */
0179 >;
0180 };
0181
0182 uart1_pins: pinmux_uart1_sin_nand {
0183 pinctrl-single,pins = <
0184 0x11c MODE_NAND /* uart1_sin */
0185 0x120 MODE_NAND /* uart1_out */
0186 >;
0187 };
0188
0189 uart2_pins: pinmux_uart2_sin {
0190 pinctrl-single,pins = <
0191 0x124 MODE_NITRO /* uart2_sin */
0192 0x128 MODE_NITRO /* uart2_out */
0193 >;
0194 };
0195
0196 uart3_pins: pinmux_uart3_sin {
0197 pinctrl-single,pins = <
0198 0x12c MODE_NITRO /* uart3_sin */
0199 0x130 MODE_NITRO /* uart3_out */
0200 >;
0201 };
0202
0203 i2s_pins: pinmux_i2s_bitclk {
0204 pinctrl-single,pins = <
0205 0x134 MODE_NITRO /* i2s_bitclk */
0206 0x138 MODE_NITRO /* i2s_sdout */
0207 0x13c MODE_NITRO /* i2s_sdin */
0208 0x140 MODE_NITRO /* i2s_ws */
0209 0x144 MODE_NITRO /* i2s_mclk */
0210 0x148 MODE_NITRO /* i2s_spdif_out */
0211 >;
0212 };
0213
0214 qspi_pins: pinumx_qspi_hold_n {
0215 pinctrl-single,pins = <
0216 0x14c MODE_NAND /* qspi_hold_n */
0217 0x150 MODE_NAND /* qspi_wp_n */
0218 0x154 MODE_NAND /* qspi_sck */
0219 0x158 MODE_NAND /* qspi_cs_n */
0220 0x15c MODE_NAND /* qspi_mosi */
0221 0x160 MODE_NAND /* qspi_miso */
0222 >;
0223 };
0224
0225 mdio_pins: pinumx_ext_mdio {
0226 pinctrl-single,pins = <
0227 0x164 MODE_NITRO /* ext_mdio */
0228 0x168 MODE_NITRO /* ext_mdc */
0229 >;
0230 };
0231
0232 i2c0_pins: pinmux_i2c0_sda {
0233 pinctrl-single,pins = <
0234 0x16c MODE_NITRO /* i2c0_sda */
0235 0x170 MODE_NITRO /* i2c0_scl */
0236 >;
0237 };
0238
0239 i2c1_pins: pinmux_i2c1_sda {
0240 pinctrl-single,pins = <
0241 0x174 MODE_NITRO /* i2c1_sda */
0242 0x178 MODE_NITRO /* i2c1_scl */
0243 >;
0244 };
0245
0246 sdio0_pins: pinmux_sdio0_cd_l {
0247 pinctrl-single,pins = <
0248 0x17c MODE_NITRO /* sdio0_cd_l */
0249 0x180 MODE_NITRO /* sdio0_clk_sdcard */
0250 0x184 MODE_NITRO /* sdio0_data0 */
0251 0x188 MODE_NITRO /* sdio0_data1 */
0252 0x18c MODE_NITRO /* sdio0_data2 */
0253 0x190 MODE_NITRO /* sdio0_data3 */
0254 0x194 MODE_NITRO /* sdio0_data4 */
0255 0x198 MODE_NITRO /* sdio0_data5 */
0256 0x19c MODE_NITRO /* sdio0_data6 */
0257 0x1a0 MODE_NITRO /* sdio0_data7 */
0258 0x1a4 MODE_NITRO /* sdio0_cmd */
0259 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
0260 0x1ac MODE_NITRO /* sdio0_led_on */
0261 0x1b0 MODE_NITRO /* sdio0_wp */
0262 >;
0263 };
0264
0265 sdio1_pins: pinmux_sdio1_cd_l {
0266 pinctrl-single,pins = <
0267 0x1b4 MODE_NITRO /* sdio1_cd_l */
0268 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
0269 0x1bc MODE_NITRO /* sdio1_data0 */
0270 0x1c0 MODE_NITRO /* sdio1_data1 */
0271 0x1c4 MODE_NITRO /* sdio1_data2 */
0272 0x1c8 MODE_NITRO /* sdio1_data3 */
0273 0x1cc MODE_NITRO /* sdio1_data4 */
0274 0x1d0 MODE_NITRO /* sdio1_data5 */
0275 0x1d4 MODE_NITRO /* sdio1_data6 */
0276 0x1d8 MODE_NITRO /* sdio1_data7 */
0277 0x1dc MODE_NITRO /* sdio1_cmd */
0278 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
0279 0x1e4 MODE_NITRO /* sdio1_led_on */
0280 0x1e8 MODE_NITRO /* sdio1_wp */
0281 >;
0282 };
0283
0284 spi0_pins: pinmux_spi0_sck_nand {
0285 pinctrl-single,pins = <
0286 0x1ec MODE_NITRO /* spi0_sck */
0287 0x1f0 MODE_NITRO /* spi0_rxd */
0288 0x1f4 MODE_NITRO /* spi0_fss */
0289 0x1f8 MODE_NITRO /* spi0_txd */
0290 >;
0291 };
0292
0293 spi1_pins: pinmux_spi1_sck_nand {
0294 pinctrl-single,pins = <
0295 0x1fc MODE_NITRO /* spi1_sck */
0296 0x200 MODE_NITRO /* spi1_rxd */
0297 0x204 MODE_NITRO /* spi1_fss */
0298 0x208 MODE_NITRO /* spi1_txd */
0299 >;
0300 };
0301
0302 nuart_pins: pinmux_uart0_sin_nitro {
0303 pinctrl-single,pins = <
0304 0x20c MODE_NITRO /* nuart_rxd */
0305 0x210 MODE_NITRO /* nuart_txd */
0306 >;
0307 };
0308
0309 uart0_pins: pinumux_uart0_sin_nand {
0310 pinctrl-single,pins = <
0311 0x20c MODE_NAND /* uart0_sin */
0312 0x210 MODE_NAND /* uart0_out */
0313 0x214 MODE_NAND /* uart0_rts */
0314 0x218 MODE_NAND /* uart0_cts */
0315 0x21c MODE_NAND /* uart0_dtr */
0316 0x220 MODE_NAND /* uart0_dcd */
0317 0x224 MODE_NAND /* uart0_dsr */
0318 0x228 MODE_NAND /* uart0_ri */
0319 >;
0320 };
0321
0322 drdu2_pins: pinmux_drdu2_overcurrent {
0323 pinctrl-single,pins = <
0324 0x22c MODE_NITRO /* drdu2_overcurrent */
0325 0x230 MODE_NITRO /* drdu2_vbus_ppc */
0326 0x234 MODE_NITRO /* drdu2_vbus_present */
0327 0x238 MODE_NITRO /* drdu2_id */
0328 >;
0329 };
0330
0331 drdu3_pins: pinmux_drdu3_overcurrent {
0332 pinctrl-single,pins = <
0333 0x23c MODE_NITRO /* drdu3_overcurrent */
0334 0x240 MODE_NITRO /* drdu3_vbus_ppc */
0335 0x244 MODE_NITRO /* drdu3_vbus_present */
0336 0x248 MODE_NITRO /* drdu3_id */
0337 >;
0338 };
0339
0340 usb3h_pins: pinmux_usb3h_overcurrent {
0341 pinctrl-single,pins = <
0342 0x24c MODE_NITRO /* usb3h_overcurrent */
0343 0x250 MODE_NITRO /* usb3h_vbus_ppc */
0344 >;
0345 };
0346 };
