0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 #include <dt-bindings/clock/bcm-sr.h>
0034
0035 osc: oscillator {
0036 #clock-cells = <0>;
0037 compatible = "fixed-clock";
0038 clock-frequency = <50000000>;
0039 };
0040
0041 crmu_ref25m: crmu_ref25m {
0042 #clock-cells = <0>;
0043 compatible = "fixed-factor-clock";
0044 clocks = <&osc>;
0045 clock-div = <2>;
0046 clock-mult = <1>;
0047 };
0048
0049 genpll0: genpll0@1d104 {
0050 #clock-cells = <1>;
0051 compatible = "brcm,sr-genpll0";
0052 reg = <0x0001d104 0x32>,
0053 <0x0001c854 0x4>;
0054 clocks = <&osc>;
0055 clock-output-names = "genpll0", "clk_125m", "clk_scr",
0056 "clk_250", "clk_pcie_axi",
0057 "clk_paxc_axi_x2",
0058 "clk_paxc_axi";
0059 };
0060
0061 genpll2: genpll2@1d1ac {
0062 #clock-cells = <1>;
0063 compatible = "brcm,sr-genpll2";
0064 reg = <0x0001d1ac 0x32>,
0065 <0x0001c854 0x4>;
0066 clocks = <&osc>;
0067 clock-output-names = "genpll2", "clk_nic",
0068 "clk_ts_500_ref", "clk_125_nitro",
0069 "clk_chimp", "clk_nic_flash",
0070 "clk_fs";
0071 };
0072
0073 genpll3: genpll3@1d1e0 {
0074 #clock-cells = <1>;
0075 compatible = "brcm,sr-genpll3";
0076 reg = <0x0001d1e0 0x32>,
0077 <0x0001c854 0x4>;
0078 clocks = <&osc>;
0079 clock-output-names = "genpll3", "clk_hsls",
0080 "clk_sdio";
0081 };
0082
0083 genpll4: genpll4@1d214 {
0084 #clock-cells = <1>;
0085 compatible = "brcm,sr-genpll4";
0086 reg = <0x0001d214 0x32>,
0087 <0x0001c854 0x4>;
0088 clocks = <&osc>;
0089 clock-output-names = "genpll4", "clk_ccn",
0090 "clk_tpiu_pll", "clk_noc",
0091 "clk_chclk_fs4",
0092 "clk_bridge_fscpu";
0093 };
0094
0095 genpll5: genpll5@1d248 {
0096 #clock-cells = <1>;
0097 compatible = "brcm,sr-genpll5";
0098 reg = <0x0001d248 0x32>,
0099 <0x0001c870 0x4>;
0100 clocks = <&osc>;
0101 clock-output-names = "genpll5", "clk_fs4_hf",
0102 "clk_crypto_ae", "clk_raid_ae";
0103 };
0104
0105 lcpll0: lcpll0@1d0c4 {
0106 #clock-cells = <1>;
0107 compatible = "brcm,sr-lcpll0";
0108 reg = <0x0001d0c4 0x3c>,
0109 <0x0001c870 0x4>;
0110 clocks = <&osc>;
0111 clock-output-names = "lcpll0", "clk_sata_refp",
0112 "clk_sata_refn", "clk_sata_350",
0113 "clk_sata_500";
0114 };
0115
0116 lcpll1: lcpll1@1d138 {
0117 #clock-cells = <1>;
0118 compatible = "brcm,sr-lcpll1";
0119 reg = <0x0001d138 0x3c>,
0120 <0x0001c870 0x4>;
0121 clocks = <&osc>;
0122 clock-output-names = "lcpll1", "clk_wan",
0123 "clk_usb_ref",
0124 "clk_crmu_ts";
0125 };
0126
0127 hsls_clk: hsls_clk {
0128 #clock-cells = <0>;
0129 compatible = "fixed-factor-clock";
0130 clocks = <&genpll3 1>;
0131 clock-div = <1>;
0132 clock-mult = <1>;
0133 };
0134
0135 hsls_div2_clk: hsls_div2_clk {
0136 #clock-cells = <0>;
0137 compatible = "fixed-factor-clock";
0138 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
0139 clock-div = <2>;
0140 clock-mult = <1>;
0141
0142 };
0143
0144 hsls_div4_clk: hsls_div4_clk {
0145 #clock-cells = <0>;
0146 compatible = "fixed-factor-clock";
0147 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
0148 clock-div = <4>;
0149 clock-mult = <1>;
0150 };
0151
0152 hsls_25m_clk: hsls_25m_clk {
0153 #clock-cells = <0>;
0154 compatible = "fixed-factor-clock";
0155 clocks = <&crmu_ref25m>;
0156 clock-div = <1>;
0157 clock-mult = <1>;
0158 };
0159
0160 hsls_25m_div2_clk: hsls_25m_div2_clk {
0161 #clock-cells = <0>;
0162 compatible = "fixed-factor-clock";
0163 clocks = <&hsls_25m_clk>;
0164 clock-div = <2>;
0165 clock-mult = <1>;
0166 };
0167
0168 sdio0_clk: sdio0_clk {
0169 #clock-cells = <0>;
0170 compatible = "fixed-factor-clock";
0171 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
0172 clock-div = <1>;
0173 clock-mult = <1>;
0174 };
0175
0176 sdio1_clk: sdio1_clk {
0177 #clock-cells = <0>;
0178 compatible = "fixed-factor-clock";
0179 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
0180 clock-div = <1>;
0181 clock-mult = <1>;
0182 };
