0001 /*
0002 * BSD LICENSE
0003 *
0004 * Copyright (c) 2015 Broadcom. All rights reserved.
0005 *
0006 * Redistribution and use in source and binary forms, with or without
0007 * modification, are permitted provided that the following conditions
0008 * are met:
0009 *
0010 * * Redistributions of source code must retain the above copyright
0011 * notice, this list of conditions and the following disclaimer.
0012 * * Redistributions in binary form must reproduce the above copyright
0013 * notice, this list of conditions and the following disclaimer in
0014 * the documentation and/or other materials provided with the
0015 * distribution.
0016 * * Neither the name of Broadcom Corporation nor the names of its
0017 * contributors may be used to endorse or promote products derived
0018 * from this software without specific prior written permission.
0019 *
0020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031 */
0032
0033 /memreserve/ 0x81000000 0x00200000;
0034
0035 #include <dt-bindings/interrupt-controller/arm-gic.h>
0036 #include <dt-bindings/clock/bcm-ns2.h>
0037
0038 / {
0039 compatible = "brcm,ns2";
0040 interrupt-parent = <&gic>;
0041 #address-cells = <2>;
0042 #size-cells = <2>;
0043
0044 cpus {
0045 #address-cells = <2>;
0046 #size-cells = <0>;
0047
0048 A57_0: cpu@0 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a57";
0051 reg = <0 0>;
0052 enable-method = "psci";
0053 next-level-cache = <&CLUSTER0_L2>;
0054 };
0055
0056 A57_1: cpu@1 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a57";
0059 reg = <0 1>;
0060 enable-method = "psci";
0061 next-level-cache = <&CLUSTER0_L2>;
0062 };
0063
0064 A57_2: cpu@2 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a57";
0067 reg = <0 2>;
0068 enable-method = "psci";
0069 next-level-cache = <&CLUSTER0_L2>;
0070 };
0071
0072 A57_3: cpu@3 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a57";
0075 reg = <0 3>;
0076 enable-method = "psci";
0077 next-level-cache = <&CLUSTER0_L2>;
0078 };
0079
0080 CLUSTER0_L2: l2-cache@0 {
0081 compatible = "cache";
0082 };
0083 };
0084
0085 psci {
0086 compatible = "arm,psci-1.0";
0087 method = "smc";
0088 };
0089
0090 timer {
0091 compatible = "arm,armv8-timer";
0092 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
0093 IRQ_TYPE_LEVEL_LOW)>,
0094 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
0095 IRQ_TYPE_LEVEL_LOW)>,
0096 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
0097 IRQ_TYPE_LEVEL_LOW)>,
0098 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
0099 IRQ_TYPE_LEVEL_LOW)>;
0100 };
0101
0102 pmu {
0103 compatible = "arm,armv8-pmuv3";
0104 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
0108 interrupt-affinity = <&A57_0>,
0109 <&A57_1>,
0110 <&A57_2>,
0111 <&A57_3>;
0112 };
0113
0114 pcie0: pcie@20020000 {
0115 compatible = "brcm,iproc-pcie";
0116 reg = <0 0x20020000 0 0x1000>;
0117 dma-coherent;
0118
0119 #interrupt-cells = <1>;
0120 interrupt-map-mask = <0 0 0 0>;
0121 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
0122
0123 linux,pci-domain = <0>;
0124
0125 bus-range = <0x00 0xff>;
0126
0127 #address-cells = <3>;
0128 #size-cells = <2>;
0129 device_type = "pci";
0130 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
0131
0132 brcm,pcie-ob;
0133 brcm,pcie-ob-oarr-size;
0134 brcm,pcie-ob-axi-offset = <0x00000000>;
0135 brcm,pcie-ob-window-size = <256>;
0136
0137 status = "disabled";
0138
0139 phys = <&pci_phy0>;
0140 phy-names = "pcie-phy";
0141
0142 msi-parent = <&v2m0>;
0143 };
0144
0145 pcie4: pcie@50020000 {
0146 compatible = "brcm,iproc-pcie";
0147 reg = <0 0x50020000 0 0x1000>;
0148 dma-coherent;
0149
0150 #interrupt-cells = <1>;
0151 interrupt-map-mask = <0 0 0 0>;
0152 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
0153
0154 linux,pci-domain = <4>;
0155
0156 bus-range = <0x00 0xff>;
0157
0158 #address-cells = <3>;
0159 #size-cells = <2>;
0160 device_type = "pci";
0161 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
0162
0163 brcm,pcie-ob;
0164 brcm,pcie-ob-oarr-size;
0165 brcm,pcie-ob-axi-offset = <0x30000000>;
0166 brcm,pcie-ob-window-size = <256>;
0167
0168 status = "disabled";
0169
0170 phys = <&pci_phy1>;
0171 phy-names = "pcie-phy";
0172
0173 msi-parent = <&v2m0>;
0174 };
0175
0176 pcie8: pcie@60c00000 {
0177 compatible = "brcm,iproc-pcie-paxc";
0178 reg = <0 0x60c00000 0 0x1000>;
0179 dma-coherent;
0180 linux,pci-domain = <8>;
0181
0182 bus-range = <0x0 0x1>;
0183
0184 #address-cells = <3>;
0185 #size-cells = <2>;
0186 device_type = "pci";
0187 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
0188
0189 status = "disabled";
0190
0191 msi-parent = <&v2m0>;
0192 };
0193
0194 soc: soc {
0195 compatible = "simple-bus";
0196 #address-cells = <1>;
0197 #size-cells = <1>;
0198 ranges = <0 0 0 0xffffffff>;
0199
0200 #include "ns2-clock.dtsi"
0201
0202 enet: ethernet@61000000 {
0203 compatible = "brcm,ns2-amac";
0204 reg = <0x61000000 0x1000>,
0205 <0x61090000 0x1000>,
0206 <0x61030000 0x100>;
0207 reg-names = "amac_base", "idm_base", "nicpm_base";
0208 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
0209 dma-coherent;
0210 phy-handle = <&gphy0>;
0211 phy-mode = "rgmii";
0212 status = "disabled";
0213 };
0214
0215 pdc0: iproc-pdc0@612c0000 {
0216 compatible = "brcm,iproc-pdc-mbox";
0217 reg = <0x612c0000 0x445>; /* PDC FS0 regs */
0218 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
0219 #mbox-cells = <1>;
0220 dma-coherent;
0221 brcm,rx-status-len = <32>;
0222 brcm,use-bcm-hdr;
0223 };
0224
0225 crypto0: crypto@612d0000 {
0226 compatible = "brcm,spum-crypto";
0227 reg = <0x612d0000 0x900>;
0228 mboxes = <&pdc0 0>;
0229 };
0230
0231 pdc1: iproc-pdc1@612e0000 {
0232 compatible = "brcm,iproc-pdc-mbox";
0233 reg = <0x612e0000 0x445>; /* PDC FS1 regs */
0234 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0235 #mbox-cells = <1>;
0236 dma-coherent;
0237 brcm,rx-status-len = <32>;
0238 brcm,use-bcm-hdr;
0239 };
0240
0241 crypto1: crypto@612f0000 {
0242 compatible = "brcm,spum-crypto";
0243 reg = <0x612f0000 0x900>;
0244 mboxes = <&pdc1 0>;
0245 };
0246
0247 pdc2: iproc-pdc2@61300000 {
0248 compatible = "brcm,iproc-pdc-mbox";
0249 reg = <0x61300000 0x445>; /* PDC FS2 regs */
0250 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
0251 #mbox-cells = <1>;
0252 dma-coherent;
0253 brcm,rx-status-len = <32>;
0254 brcm,use-bcm-hdr;
0255 };
0256
0257 crypto2: crypto@61310000 {
0258 compatible = "brcm,spum-crypto";
0259 reg = <0x61310000 0x900>;
0260 mboxes = <&pdc2 0>;
0261 };
0262
0263 pdc3: iproc-pdc3@61320000 {
0264 compatible = "brcm,iproc-pdc-mbox";
0265 reg = <0x61320000 0x445>; /* PDC FS3 regs */
0266 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0267 #mbox-cells = <1>;
0268 dma-coherent;
0269 brcm,rx-status-len = <32>;
0270 brcm,use-bcm-hdr;
0271 };
0272
0273 crypto3: crypto@61330000 {
0274 compatible = "brcm,spum-crypto";
0275 reg = <0x61330000 0x900>;
0276 mboxes = <&pdc3 0>;
0277 };
0278
0279 dma0: dma-controller@61360000 {
0280 compatible = "arm,pl330", "arm,primecell";
0281 reg = <0x61360000 0x1000>;
0282 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0283 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
0284 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0285 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0286 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0287 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0288 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
0289 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
0290 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
0291 #dma-cells = <1>;
0292 clocks = <&iprocslow>;
0293 clock-names = "apb_pclk";
0294 };
0295
0296 smmu: mmu@64000000 {
0297 compatible = "arm,mmu-500";
0298 reg = <0x64000000 0x40000>;
0299 #global-interrupts = <2>;
0300 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
0305 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
0306 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
0307 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
0308 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
0309 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
0310 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
0311 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
0312 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
0313 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
0314 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
0315 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
0316 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
0317 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
0318 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
0319 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
0320 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
0321 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
0322 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
0323 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
0324 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
0325 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
0329 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
0330 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
0331 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
0332 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
0333 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
0334 #iommu-cells = <1>;
0335 };
0336
0337 pinctrl: pinctrl@6501d130 {
0338 compatible = "brcm,ns2-pinmux";
0339 reg = <0x6501d130 0x08>,
0340 <0x660a0028 0x04>,
0341 <0x660009b0 0x40>;
0342 };
0343
0344 gpio_aon: gpio@65024800 {
0345 compatible = "brcm,iproc-gpio";
0346 reg = <0x65024800 0x50>,
0347 <0x65024008 0x18>;
0348 ngpios = <6>;
0349 #gpio-cells = <2>;
0350 gpio-controller;
0351 };
0352
0353 gic: interrupt-controller@65210000 {
0354 compatible = "arm,gic-400";
0355 #interrupt-cells = <3>;
0356 interrupt-controller;
0357 reg = <0x65210000 0x1000>,
0358 <0x65220000 0x1000>,
0359 <0x65240000 0x2000>,
0360 <0x65260000 0x1000>;
0361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
0362 IRQ_TYPE_LEVEL_HIGH)>;
0363
0364 #address-cells = <1>;
0365 #size-cells = <1>;
0366 ranges = <0 0x652e0000 0x80000>;
0367
0368 v2m0: v2m@0 {
0369 compatible = "arm,gic-v2m-frame";
0370 interrupt-parent = <&gic>;
0371 msi-controller;
0372 reg = <0x00000 0x1000>;
0373 arm,msi-base-spi = <72>;
0374 arm,msi-num-spis = <16>;
0375 };
0376
0377 v2m1: v2m@10000 {
0378 compatible = "arm,gic-v2m-frame";
0379 interrupt-parent = <&gic>;
0380 msi-controller;
0381 reg = <0x10000 0x1000>;
0382 arm,msi-base-spi = <88>;
0383 arm,msi-num-spis = <16>;
0384 };
0385
0386 v2m2: v2m@20000 {
0387 compatible = "arm,gic-v2m-frame";
0388 interrupt-parent = <&gic>;
0389 msi-controller;
0390 reg = <0x20000 0x1000>;
0391 arm,msi-base-spi = <104>;
0392 arm,msi-num-spis = <16>;
0393 };
0394
0395 v2m3: v2m@30000 {
0396 compatible = "arm,gic-v2m-frame";
0397 interrupt-parent = <&gic>;
0398 msi-controller;
0399 reg = <0x30000 0x1000>;
0400 arm,msi-base-spi = <120>;
0401 arm,msi-num-spis = <16>;
0402 };
0403
0404 v2m4: v2m@40000 {
0405 compatible = "arm,gic-v2m-frame";
0406 interrupt-parent = <&gic>;
0407 msi-controller;
0408 reg = <0x40000 0x1000>;
0409 arm,msi-base-spi = <136>;
0410 arm,msi-num-spis = <16>;
0411 };
0412
0413 v2m5: v2m@50000 {
0414 compatible = "arm,gic-v2m-frame";
0415 interrupt-parent = <&gic>;
0416 msi-controller;
0417 reg = <0x50000 0x1000>;
0418 arm,msi-base-spi = <152>;
0419 arm,msi-num-spis = <16>;
0420 };
0421
0422 v2m6: v2m@60000 {
0423 compatible = "arm,gic-v2m-frame";
0424 interrupt-parent = <&gic>;
0425 msi-controller;
0426 reg = <0x60000 0x1000>;
0427 arm,msi-base-spi = <168>;
0428 arm,msi-num-spis = <16>;
0429 };
0430
0431 v2m7: v2m@70000 {
0432 compatible = "arm,gic-v2m-frame";
0433 interrupt-parent = <&gic>;
0434 msi-controller;
0435 reg = <0x70000 0x1000>;
0436 arm,msi-base-spi = <184>;
0437 arm,msi-num-spis = <16>;
0438 };
0439 };
0440
0441 cci@65590000 {
0442 compatible = "arm,cci-400";
0443 #address-cells = <1>;
0444 #size-cells = <1>;
0445 reg = <0x65590000 0x1000>;
0446 ranges = <0 0x65590000 0x10000>;
0447
0448 pmu@9000 {
0449 compatible = "arm,cci-400-pmu,r1",
0450 "arm,cci-400-pmu";
0451 reg = <0x9000 0x4000>;
0452 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
0453 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
0454 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
0455 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
0456 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
0458 };
0459 };
0460
0461 usbdrd_phy: phy@66000960 {
0462 #phy-cells = <0>;
0463 compatible = "brcm,ns2-drd-phy";
0464 reg = <0x66000960 0x24>,
0465 <0x67012800 0x4>,
0466 <0x6501d148 0x4>,
0467 <0x664d0700 0x4>;
0468 reg-names = "icfg", "rst-ctrl",
0469 "crmu-ctrl", "usb2-strap";
0470 id-gpios = <&gpio_g 30 0>;
0471 vbus-gpios = <&gpio_g 31 0>;
0472 status = "disabled";
0473 };
0474
0475 pwm: pwm@66010000 {
0476 compatible = "brcm,iproc-pwm";
0477 reg = <0x66010000 0x28>;
0478 clocks = <&osc>;
0479 #pwm-cells = <3>;
0480 status = "disabled";
0481 };
0482
0483 mdio_mux_iproc: mdio-mux@66020000 {
0484 compatible = "brcm,mdio-mux-iproc";
0485 reg = <0x66020000 0x250>;
0486 #address-cells = <1>;
0487 #size-cells = <0>;
0488
0489 mdio@0 {
0490 reg = <0x0>;
0491 #address-cells = <1>;
0492 #size-cells = <0>;
0493
0494 pci_phy0: pci-phy@0 {
0495 compatible = "brcm,ns2-pcie-phy";
0496 reg = <0x0>;
0497 #phy-cells = <0>;
0498 status = "disabled";
0499 };
0500 };
0501
0502 mdio@7 {
0503 reg = <0x7>;
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506
0507 pci_phy1: pci-phy@0 {
0508 compatible = "brcm,ns2-pcie-phy";
0509 reg = <0x0>;
0510 #phy-cells = <0>;
0511 status = "disabled";
0512 };
0513 };
0514
0515 mdio@10 {
0516 reg = <0x10>;
0517 #address-cells = <1>;
0518 #size-cells = <0>;
0519 };
0520 };
0521
0522 timer0: timer@66030000 {
0523 compatible = "arm,sp804", "arm,primecell";
0524 reg = <0x66030000 0x1000>;
0525 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
0526 clocks = <&iprocslow>,
0527 <&iprocslow>,
0528 <&iprocslow>;
0529 clock-names = "timer1", "timer2", "apb_pclk";
0530 };
0531
0532 timer1: timer@66040000 {
0533 compatible = "arm,sp804", "arm,primecell";
0534 reg = <0x66040000 0x1000>;
0535 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
0536 clocks = <&iprocslow>,
0537 <&iprocslow>,
0538 <&iprocslow>;
0539 clock-names = "timer1", "timer2", "apb_pclk";
0540 };
0541
0542 timer2: timer@66050000 {
0543 compatible = "arm,sp804", "arm,primecell";
0544 reg = <0x66050000 0x1000>;
0545 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
0546 clocks = <&iprocslow>,
0547 <&iprocslow>,
0548 <&iprocslow>;
0549 clock-names = "timer1", "timer2", "apb_pclk";
0550 };
0551
0552 timer3: timer@66060000 {
0553 compatible = "arm,sp804", "arm,primecell";
0554 reg = <0x66060000 0x1000>;
0555 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
0556 clocks = <&iprocslow>,
0557 <&iprocslow>,
0558 <&iprocslow>;
0559 clock-names = "timer1", "timer2", "apb_pclk";
0560 };
0561
0562 i2c0: i2c@66080000 {
0563 compatible = "brcm,iproc-i2c";
0564 reg = <0x66080000 0x100>;
0565 #address-cells = <1>;
0566 #size-cells = <0>;
0567 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
0568 clock-frequency = <100000>;
0569 status = "disabled";
0570 };
0571
0572 wdt0: watchdog@66090000 {
0573 compatible = "arm,sp805", "arm,primecell";
0574 reg = <0x66090000 0x1000>;
0575 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
0576 clocks = <&iprocslow>, <&iprocslow>;
0577 clock-names = "wdog_clk", "apb_pclk";
0578 };
0579
0580 gpio_g: gpio@660a0000 {
0581 compatible = "brcm,iproc-gpio";
0582 reg = <0x660a0000 0x50>;
0583 ngpios = <32>;
0584 #gpio-cells = <2>;
0585 gpio-controller;
0586 interrupt-controller;
0587 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
0588 };
0589
0590 i2c1: i2c@660b0000 {
0591 compatible = "brcm,iproc-i2c";
0592 reg = <0x660b0000 0x100>;
0593 #address-cells = <1>;
0594 #size-cells = <0>;
0595 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
0596 clock-frequency = <100000>;
0597 status = "disabled";
0598 };
0599
0600 uart0: serial@66100000 {
0601 compatible = "snps,dw-apb-uart";
0602 reg = <0x66100000 0x100>;
0603 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
0604 clocks = <&iprocslow>;
0605 reg-shift = <2>;
0606 reg-io-width = <4>;
0607 status = "disabled";
0608 };
0609
0610 uart1: serial@66110000 {
0611 compatible = "snps,dw-apb-uart";
0612 reg = <0x66110000 0x100>;
0613 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
0614 clocks = <&iprocslow>;
0615 reg-shift = <2>;
0616 reg-io-width = <4>;
0617 status = "disabled";
0618 };
0619
0620 uart2: serial@66120000 {
0621 compatible = "snps,dw-apb-uart";
0622 reg = <0x66120000 0x100>;
0623 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
0624 clocks = <&iprocslow>;
0625 reg-shift = <2>;
0626 reg-io-width = <4>;
0627 status = "disabled";
0628 };
0629
0630 uart3: serial@66130000 {
0631 compatible = "snps,dw-apb-uart";
0632 reg = <0x66130000 0x100>;
0633 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
0634 reg-shift = <2>;
0635 reg-io-width = <4>;
0636 clocks = <&osc>;
0637 status = "disabled";
0638 };
0639
0640 ssp0: spi@66180000 {
0641 compatible = "arm,pl022", "arm,primecell";
0642 reg = <0x66180000 0x1000>;
0643 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
0644 clocks = <&iprocslow>, <&iprocslow>;
0645 clock-names = "sspclk", "apb_pclk";
0646 #address-cells = <1>;
0647 #size-cells = <0>;
0648 status = "disabled";
0649 };
0650
0651 ssp1: spi@66190000 {
0652 compatible = "arm,pl022", "arm,primecell";
0653 reg = <0x66190000 0x1000>;
0654 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
0655 clocks = <&iprocslow>, <&iprocslow>;
0656 clock-names = "sspclk", "apb_pclk";
0657 #address-cells = <1>;
0658 #size-cells = <0>;
0659 status = "disabled";
0660 };
0661
0662 hwrng: hwrng@66220000 {
0663 compatible = "brcm,iproc-rng200";
0664 reg = <0x66220000 0x28>;
0665 };
0666
0667 sata_phy: sata_phy@663f0100 {
0668 compatible = "brcm,iproc-ns2-sata-phy";
0669 reg = <0x663f0100 0x1f00>,
0670 <0x663f004c 0x10>;
0671 reg-names = "phy", "phy-ctrl";
0672 #address-cells = <1>;
0673 #size-cells = <0>;
0674
0675 sata_phy0: sata-phy@0 {
0676 reg = <0>;
0677 #phy-cells = <0>;
0678 status = "disabled";
0679 };
0680
0681 sata_phy1: sata-phy@1 {
0682 reg = <1>;
0683 #phy-cells = <0>;
0684 status = "disabled";
0685 };
0686 };
0687
0688 sata: sata@663f2000 {
0689 compatible = "brcm,iproc-ahci", "generic-ahci";
0690 reg = <0x663f2000 0x1000>;
0691 dma-coherent;
0692 reg-names = "ahci";
0693 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
0694 #address-cells = <1>;
0695 #size-cells = <0>;
0696 status = "disabled";
0697
0698 sata0: sata-port@0 {
0699 reg = <0>;
0700 phys = <&sata_phy0>;
0701 phy-names = "sata-phy";
0702 };
0703
0704 sata1: sata-port@1 {
0705 reg = <1>;
0706 phys = <&sata_phy1>;
0707 phy-names = "sata-phy";
0708 };
0709 };
0710
0711 sdio0: sdhci@66420000 {
0712 compatible = "brcm,sdhci-iproc-cygnus";
0713 reg = <0x66420000 0x100>;
0714 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
0715 dma-coherent;
0716 bus-width = <8>;
0717 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
0718 status = "disabled";
0719 };
0720
0721 sdio1: sdhci@66430000 {
0722 compatible = "brcm,sdhci-iproc-cygnus";
0723 reg = <0x66430000 0x100>;
0724 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
0725 dma-coherent;
0726 bus-width = <8>;
0727 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
0728 status = "disabled";
0729 };
0730
0731 nand: nand@66460000 {
0732 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
0733 reg = <0x66460000 0x600>,
0734 <0x67015408 0x600>,
0735 <0x66460f00 0x20>;
0736 reg-names = "nand", "iproc-idm", "iproc-ext";
0737 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
0738
0739 #address-cells = <1>;
0740 #size-cells = <0>;
0741
0742 brcm,nand-has-wp;
0743 };
0744
0745 qspi: spi@66470200 {
0746 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
0747 reg = <0x66470200 0x184>,
0748 <0x66470000 0x124>,
0749 <0x67017408 0x004>,
0750 <0x664703a0 0x01c>;
0751 reg-names = "mspi", "bspi", "intr_regs",
0752 "intr_status_reg";
0753 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
0754 interrupt-names = "spi_l1_intr";
0755 clocks = <&iprocmed>;
0756 clock-names = "iprocmed";
0757 num-cs = <2>;
0758 #address-cells = <1>;
0759 #size-cells = <0>;
0760 };
0761
0762 };
0763 };
