0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 / {
0010 compatible = "brcm,bcm6813", "brcm,bcmbca";
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <2>;
0018 #size-cells = <0>;
0019
0020 B53_0: cpu@0 {
0021 compatible = "brcm,brahma-b53";
0022 device_type = "cpu";
0023 reg = <0x0 0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 B53_1: cpu@1 {
0029 compatible = "brcm,brahma-b53";
0030 device_type = "cpu";
0031 reg = <0x0 0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 B53_2: cpu@2 {
0037 compatible = "brcm,brahma-b53";
0038 device_type = "cpu";
0039 reg = <0x0 0x2>;
0040 next-level-cache = <&L2_0>;
0041 enable-method = "psci";
0042 };
0043
0044 B53_3: cpu@3 {
0045 compatible = "brcm,brahma-b53";
0046 device_type = "cpu";
0047 reg = <0x0 0x3>;
0048 next-level-cache = <&L2_0>;
0049 enable-method = "psci";
0050 };
0051
0052 L2_0: l2-cache0 {
0053 compatible = "cache";
0054 };
0055 };
0056
0057 timer {
0058 compatible = "arm,armv8-timer";
0059 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0060 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0061 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0062 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0063 };
0064
0065 pmu: pmu {
0066 compatible = "arm,cortex-a53-pmu";
0067 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0071 interrupt-affinity = <&B53_0>, <&B53_1>,
0072 <&B53_2>, <&B53_3>;
0073 };
0074
0075 clocks: clocks {
0076 periph_clk: periph-clk {
0077 compatible = "fixed-clock";
0078 #clock-cells = <0>;
0079 clock-frequency = <200000000>;
0080 };
0081 uart_clk: uart-clk {
0082 compatible = "fixed-factor-clock";
0083 #clock-cells = <0>;
0084 clocks = <&periph_clk>;
0085 clock-div = <4>;
0086 clock-mult = <1>;
0087 };
0088 };
0089
0090 psci {
0091 compatible = "arm,psci-0.2";
0092 method = "smc";
0093 };
0094
0095 axi@81000000 {
0096 compatible = "simple-bus";
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 ranges = <0x0 0x0 0x81000000 0x8000>;
0100
0101 gic: interrupt-controller@1000 {
0102 compatible = "arm,gic-400";
0103 #interrupt-cells = <3>;
0104 interrupt-controller;
0105 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0106 reg = <0x1000 0x1000>,
0107 <0x2000 0x2000>,
0108 <0x4000 0x2000>,
0109 <0x6000 0x2000>;
0110 };
0111 };
0112
0113 bus@ff800000 {
0114 compatible = "simple-bus";
0115 #address-cells = <1>;
0116 #size-cells = <1>;
0117 ranges = <0x0 0x0 0xff800000 0x800000>;
0118
0119 uart0: serial@12000 {
0120 compatible = "arm,pl011", "arm,primecell";
0121 reg = <0x12000 0x1000>;
0122 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0123 clocks = <&uart_clk>, <&uart_clk>;
0124 clock-names = "uartclk", "apb_pclk";
0125 status = "disabled";
0126 };
0127 };
0128 };
