0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 / {
0010 compatible = "brcm,bcm63146", "brcm,bcmbca";
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <2>;
0018 #size-cells = <0>;
0019
0020 B53_0: cpu@0 {
0021 compatible = "brcm,brahma-b53";
0022 device_type = "cpu";
0023 reg = <0x0 0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 B53_1: cpu@1 {
0029 compatible = "brcm,brahma-b53";
0030 device_type = "cpu";
0031 reg = <0x0 0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 L2_0: l2-cache0 {
0037 compatible = "cache";
0038 };
0039 };
0040
0041 timer {
0042 compatible = "arm,armv8-timer";
0043 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0044 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0045 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0046 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0047 };
0048
0049 pmu: pmu {
0050 compatible = "arm,cortex-a53-pmu";
0051 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0052 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0053 interrupt-affinity = <&B53_0>, <&B53_1>;
0054 };
0055
0056 clocks: clocks {
0057 periph_clk: periph-clk {
0058 compatible = "fixed-clock";
0059 #clock-cells = <0>;
0060 clock-frequency = <200000000>;
0061 };
0062 uart_clk: uart-clk {
0063 compatible = "fixed-factor-clock";
0064 #clock-cells = <0>;
0065 clocks = <&periph_clk>;
0066 clock-div = <4>;
0067 clock-mult = <1>;
0068 };
0069 };
0070
0071 psci {
0072 compatible = "arm,psci-0.2";
0073 method = "smc";
0074 };
0075
0076 axi@81000000 {
0077 compatible = "simple-bus";
0078 #address-cells = <1>;
0079 #size-cells = <1>;
0080 ranges = <0x0 0x0 0x81000000 0x8000>;
0081
0082 gic: interrupt-controller@1000 {
0083 compatible = "arm,gic-400";
0084 #interrupt-cells = <3>;
0085 interrupt-controller;
0086 reg = <0x1000 0x1000>,
0087 <0x2000 0x2000>,
0088 <0x4000 0x2000>,
0089 <0x6000 0x2000>;
0090 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
0091 IRQ_TYPE_LEVEL_HIGH)>;
0092 };
0093 };
0094
0095 bus@ff800000 {
0096 compatible = "simple-bus";
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 ranges = <0x0 0x0 0xff800000 0x800000>;
0100
0101 uart0: serial@12000 {
0102 compatible = "arm,pl011", "arm,primecell";
0103 reg = <0x12000 0x1000>;
0104 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0105 clocks = <&uart_clk>, <&uart_clk>;
0106 clock-names = "uartclk", "apb_pclk";
0107 status = "disabled";
0108 };
0109 };
0110 };
