0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2019 Linaro Ltd.
0004 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0005 */
0006
0007 #include <dt-bindings/clock/bm1880-clock.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
0010
0011 / {
0012 compatible = "bitmain,bm1880";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a53";
0024 reg = <0x0>;
0025 enable-method = "psci";
0026 };
0027
0028 cpu1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a53";
0031 reg = <0x1>;
0032 enable-method = "psci";
0033 };
0034 };
0035
0036 reserved-memory {
0037 #address-cells = <2>;
0038 #size-cells = <2>;
0039 ranges;
0040
0041 secmon@100000000 {
0042 reg = <0x1 0x00000000 0x0 0x20000>;
0043 no-map;
0044 };
0045
0046 jpu@130000000 {
0047 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
0048 no-map;
0049 };
0050
0051 vpu@138000000 {
0052 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
0053 no-map;
0054 };
0055 };
0056
0057 psci {
0058 compatible = "arm,psci-0.2";
0059 method = "smc";
0060 };
0061
0062 timer {
0063 compatible = "arm,armv8-timer";
0064 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0065 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0066 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0067 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0068 };
0069
0070 osc: osc {
0071 compatible = "fixed-clock";
0072 clock-frequency = <25000000>;
0073 #clock-cells = <0>;
0074 };
0075
0076 soc {
0077 compatible = "simple-bus";
0078 #address-cells = <2>;
0079 #size-cells = <2>;
0080 ranges;
0081
0082 gic: interrupt-controller@50001000 {
0083 compatible = "arm,gic-400";
0084 reg = <0x0 0x50001000 0x0 0x1000>,
0085 <0x0 0x50002000 0x0 0x2000>;
0086 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
0087 interrupt-controller;
0088 #interrupt-cells = <3>;
0089 };
0090
0091 sctrl: system-controller@50010000 {
0092 compatible = "bitmain,bm1880-sctrl", "syscon",
0093 "simple-mfd";
0094 reg = <0x0 0x50010000 0x0 0x1000>;
0095 #address-cells = <1>;
0096 #size-cells = <1>;
0097 ranges = <0x0 0x0 0x50010000 0x1000>;
0098
0099 pinctrl: pinctrl@400 {
0100 compatible = "bitmain,bm1880-pinctrl";
0101 reg = <0x400 0x120>;
0102 };
0103
0104 clk: clock-controller@e8 {
0105 compatible = "bitmain,bm1880-clk";
0106 reg = <0xe8 0x0c>, <0x800 0xb0>;
0107 reg-names = "pll", "sys";
0108 clocks = <&osc>;
0109 clock-names = "osc";
0110 #clock-cells = <1>;
0111 };
0112
0113 rst: reset-controller@c00 {
0114 compatible = "bitmain,bm1880-reset";
0115 reg = <0xc00 0x8>;
0116 #reset-cells = <1>;
0117 };
0118 };
0119
0120 gpio0: gpio@50027000 {
0121 #address-cells = <1>;
0122 #size-cells = <0>;
0123 compatible = "snps,dw-apb-gpio";
0124 reg = <0x0 0x50027000 0x0 0x400>;
0125
0126 porta: gpio-controller@0 {
0127 compatible = "snps,dw-apb-gpio-port";
0128 gpio-controller;
0129 #gpio-cells = <2>;
0130 ngpios = <32>;
0131 reg = <0>;
0132 interrupt-controller;
0133 #interrupt-cells = <2>;
0134 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0135 };
0136 };
0137
0138 gpio1: gpio@50027400 {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 compatible = "snps,dw-apb-gpio";
0142 reg = <0x0 0x50027400 0x0 0x400>;
0143
0144 portb: gpio-controller@0 {
0145 compatible = "snps,dw-apb-gpio-port";
0146 gpio-controller;
0147 #gpio-cells = <2>;
0148 ngpios = <32>;
0149 reg = <0>;
0150 interrupt-controller;
0151 #interrupt-cells = <2>;
0152 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0153 };
0154 };
0155
0156 gpio2: gpio@50027800 {
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 compatible = "snps,dw-apb-gpio";
0160 reg = <0x0 0x50027800 0x0 0x400>;
0161
0162 portc: gpio-controller@0 {
0163 compatible = "snps,dw-apb-gpio-port";
0164 gpio-controller;
0165 #gpio-cells = <2>;
0166 ngpios = <8>;
0167 reg = <0>;
0168 interrupt-controller;
0169 #interrupt-cells = <2>;
0170 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0171 };
0172 };
0173
0174 uart0: serial@58018000 {
0175 compatible = "snps,dw-apb-uart";
0176 reg = <0x0 0x58018000 0x0 0x2000>;
0177 clocks = <&clk BM1880_CLK_UART_500M>,
0178 <&clk BM1880_CLK_APB_UART>;
0179 clock-names = "baudclk", "apb_pclk";
0180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0181 reg-shift = <2>;
0182 reg-io-width = <4>;
0183 resets = <&rst BM1880_RST_UART0_1_CLK>;
0184 status = "disabled";
0185 };
0186
0187 uart1: serial@5801A000 {
0188 compatible = "snps,dw-apb-uart";
0189 reg = <0x0 0x5801a000 0x0 0x2000>;
0190 clocks = <&clk BM1880_CLK_UART_500M>,
0191 <&clk BM1880_CLK_APB_UART>;
0192 clock-names = "baudclk", "apb_pclk";
0193 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0194 reg-shift = <2>;
0195 reg-io-width = <4>;
0196 resets = <&rst BM1880_RST_UART0_1_ACLK>;
0197 status = "disabled";
0198 };
0199
0200 uart2: serial@5801C000 {
0201 compatible = "snps,dw-apb-uart";
0202 reg = <0x0 0x5801c000 0x0 0x2000>;
0203 clocks = <&clk BM1880_CLK_UART_500M>,
0204 <&clk BM1880_CLK_APB_UART>;
0205 clock-names = "baudclk", "apb_pclk";
0206 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0207 reg-shift = <2>;
0208 reg-io-width = <4>;
0209 resets = <&rst BM1880_RST_UART2_3_CLK>;
0210 status = "disabled";
0211 };
0212
0213 uart3: serial@5801E000 {
0214 compatible = "snps,dw-apb-uart";
0215 reg = <0x0 0x5801e000 0x0 0x2000>;
0216 clocks = <&clk BM1880_CLK_UART_500M>,
0217 <&clk BM1880_CLK_APB_UART>;
0218 clock-names = "baudclk", "apb_pclk";
0219 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0220 reg-shift = <2>;
0221 reg-io-width = <4>;
0222 resets = <&rst BM1880_RST_UART2_3_ACLK>;
0223 status = "disabled";
0224 };
0225 };
0226 };
