0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * LogicTile Express 20MG
0006 * V2F-1XV7
0007 *
0008 * Cortex-A53 (2 cores) Soft Macrocell Model
0009 *
0010 * HBI-0247C
0011 */
0012
0013 /dts-v1/;
0014
0015 #include <dt-bindings/interrupt-controller/arm-gic.h>
0016 #include "vexpress-v2m-rs1.dtsi"
0017
0018 / {
0019 model = "V2F-1XV7 Cortex-A53x2 SMM";
0020 arm,hbi = <0x247>;
0021 arm,vexpress,site = <0xf>;
0022 compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
0023 interrupt-parent = <&gic>;
0024 #address-cells = <2>;
0025 #size-cells = <2>;
0026
0027 chosen {
0028 stdout-path = "serial0:38400n8";
0029 };
0030
0031 aliases {
0032 serial0 = &v2m_serial0;
0033 serial1 = &v2m_serial1;
0034 serial2 = &v2m_serial2;
0035 serial3 = &v2m_serial3;
0036 i2c0 = &v2m_i2c_dvi;
0037 i2c1 = &v2m_i2c_pcie;
0038 };
0039
0040 cpus {
0041 #address-cells = <2>;
0042 #size-cells = <0>;
0043
0044 cpu@0 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a53";
0047 reg = <0 0>;
0048 next-level-cache = <&L2_0>;
0049 };
0050
0051 cpu@1 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a53";
0054 reg = <0 1>;
0055 next-level-cache = <&L2_0>;
0056 };
0057
0058 L2_0: l2-cache0 {
0059 compatible = "cache";
0060 };
0061 };
0062
0063 memory@80000000 {
0064 device_type = "memory";
0065 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
0066 };
0067
0068 reserved-memory {
0069 #address-cells = <2>;
0070 #size-cells = <2>;
0071 ranges;
0072
0073 /* Chipselect 2 is physically at 0x18000000 */
0074 vram: vram@18000000 {
0075 /* 8 MB of designated video RAM */
0076 compatible = "shared-dma-pool";
0077 reg = <0 0x18000000 0 0x00800000>;
0078 no-map;
0079 };
0080 };
0081
0082 gic: interrupt-controller@2c001000 {
0083 compatible = "arm,gic-400";
0084 #interrupt-cells = <3>;
0085 #address-cells = <0>;
0086 interrupt-controller;
0087 reg = <0 0x2c001000 0 0x1000>,
0088 <0 0x2c002000 0 0x2000>,
0089 <0 0x2c004000 0 0x2000>,
0090 <0 0x2c006000 0 0x2000>;
0091 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0092 };
0093
0094 timer {
0095 compatible = "arm,armv8-timer";
0096 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0097 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0098 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0099 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0100 };
0101
0102 pmu {
0103 compatible = "arm,armv8-pmuv3";
0104 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0106 };
0107
0108 dcc {
0109 compatible = "arm,vexpress,config-bus";
0110 arm,vexpress,config-bridge = <&v2m_sysreg>;
0111
0112 smbclk: smclk {
0113 /* SMC clock */
0114 compatible = "arm,vexpress-osc";
0115 arm,vexpress-sysreg,func = <1 4>;
0116 freq-range = <40000000 40000000>;
0117 #clock-cells = <0>;
0118 clock-output-names = "smclk";
0119 };
0120
0121 volt-vio {
0122 /* VIO to expansion board above */
0123 compatible = "arm,vexpress-volt";
0124 arm,vexpress-sysreg,func = <2 0>;
0125 regulator-name = "VIO_UP";
0126 regulator-min-microvolt = <800000>;
0127 regulator-max-microvolt = <1800000>;
0128 regulator-always-on;
0129 };
0130
0131 volt-12v {
0132 /* 12V from power connector J6 */
0133 compatible = "arm,vexpress-volt";
0134 arm,vexpress-sysreg,func = <2 1>;
0135 regulator-name = "12";
0136 regulator-always-on;
0137 };
0138
0139 temp-fpga {
0140 /* FPGA temperature */
0141 compatible = "arm,vexpress-temp";
0142 arm,vexpress-sysreg,func = <4 0>;
0143 label = "FPGA";
0144 };
0145 };
0146
0147 smb: bus@8000000 {
0148 ranges = <0x8000000 0 0x8000000 0x18000000>;
0149 };
0150 };
