0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Fast Models
0004 *
0005 * Versatile Express (VE) system model
0006 * Motherboard component
0007 *
0008 * VEMotherBoard.lisa
0009 */
0010 / {
0011 v2m_clk24mhz: clk24mhz {
0012 compatible = "fixed-clock";
0013 #clock-cells = <0>;
0014 clock-frequency = <24000000>;
0015 clock-output-names = "v2m:clk24mhz";
0016 };
0017
0018 v2m_refclk1mhz: refclk1mhz {
0019 compatible = "fixed-clock";
0020 #clock-cells = <0>;
0021 clock-frequency = <1000000>;
0022 clock-output-names = "v2m:refclk1mhz";
0023 };
0024
0025 v2m_refclk32khz: refclk32khz {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <32768>;
0029 clock-output-names = "v2m:refclk32khz";
0030 };
0031
0032 v2m_fixed_3v3: v2m-3v3 {
0033 compatible = "regulator-fixed";
0034 regulator-name = "3V3";
0035 regulator-min-microvolt = <3300000>;
0036 regulator-max-microvolt = <3300000>;
0037 regulator-always-on;
0038 };
0039
0040 mcc {
0041 compatible = "arm,vexpress,config-bus";
0042 arm,vexpress,config-bridge = <&v2m_sysreg>;
0043
0044 v2m_oscclk1: oscclk1 {
0045 /* CLCD clock */
0046 compatible = "arm,vexpress-osc";
0047 arm,vexpress-sysreg,func = <1 1>;
0048 freq-range = <23750000 63500000>;
0049 #clock-cells = <0>;
0050 clock-output-names = "v2m:oscclk1";
0051 };
0052
0053 reset {
0054 compatible = "arm,vexpress-reset";
0055 arm,vexpress-sysreg,func = <5 0>;
0056 };
0057
0058 muxfpga {
0059 compatible = "arm,vexpress-muxfpga";
0060 arm,vexpress-sysreg,func = <7 0>;
0061 };
0062
0063 shutdown {
0064 compatible = "arm,vexpress-shutdown";
0065 arm,vexpress-sysreg,func = <8 0>;
0066 };
0067
0068 reboot {
0069 compatible = "arm,vexpress-reboot";
0070 arm,vexpress-sysreg,func = <9 0>;
0071 };
0072
0073 dvimode {
0074 compatible = "arm,vexpress-dvimode";
0075 arm,vexpress-sysreg,func = <11 0>;
0076 };
0077 };
0078
0079 bus@8000000 {
0080 compatible = "simple-bus";
0081 #address-cells = <2>;
0082 #size-cells = <1>;
0083 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
0084
0085 motherboard-bus@8000000 {
0086 compatible = "arm,vexpress,v2m-p1", "simple-bus";
0087 #address-cells = <2>; /* SMB chipselect number and offset */
0088 #size-cells = <1>;
0089 ranges = <0 0 0 0x08000000 0x04000000>,
0090 <1 0 0 0x14000000 0x04000000>,
0091 <2 0 0 0x18000000 0x04000000>,
0092 <3 0 0 0x1c000000 0x04000000>,
0093 <4 0 0 0x0c000000 0x04000000>,
0094 <5 0 0 0x10000000 0x04000000>;
0095
0096 flash@0 {
0097 compatible = "arm,vexpress-flash", "cfi-flash";
0098 reg = <0 0x00000000 0x04000000>,
0099 <4 0x00000000 0x04000000>;
0100 bank-width = <4>;
0101 };
0102
0103 ethernet@202000000 {
0104 compatible = "smsc,lan91c111";
0105 reg = <2 0x02000000 0x10000>;
0106 interrupts = <15>;
0107 };
0108
0109 iofpga-bus@300000000 {
0110 compatible = "simple-bus";
0111 #address-cells = <1>;
0112 #size-cells = <1>;
0113 ranges = <0 3 0 0x210000>;
0114
0115 v2m_sysreg: sysreg@10000 {
0116 compatible = "arm,vexpress-sysreg";
0117 reg = <0x010000 0x1000>;
0118 gpio-controller;
0119 #gpio-cells = <2>;
0120 };
0121
0122 v2m_sysctl: sysctl@20000 {
0123 compatible = "arm,sp810", "arm,primecell";
0124 reg = <0x020000 0x1000>;
0125 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
0126 clock-names = "refclk", "timclk", "apb_pclk";
0127 #clock-cells = <1>;
0128 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
0129 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
0130 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
0131 };
0132
0133 aaci@40000 {
0134 compatible = "arm,pl041", "arm,primecell";
0135 reg = <0x040000 0x1000>;
0136 interrupts = <11>;
0137 clocks = <&v2m_clk24mhz>;
0138 clock-names = "apb_pclk";
0139 };
0140
0141 mmc@50000 {
0142 compatible = "arm,pl180", "arm,primecell";
0143 reg = <0x050000 0x1000>;
0144 interrupts = <9>, <10>;
0145 cd-gpios = <&v2m_sysreg 0 0>;
0146 wp-gpios = <&v2m_sysreg 1 0>;
0147 max-frequency = <12000000>;
0148 vmmc-supply = <&v2m_fixed_3v3>;
0149 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0150 clock-names = "mclk", "apb_pclk";
0151 };
0152
0153 kmi@60000 {
0154 compatible = "arm,pl050", "arm,primecell";
0155 reg = <0x060000 0x1000>;
0156 interrupts = <12>;
0157 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0158 clock-names = "KMIREFCLK", "apb_pclk";
0159 };
0160
0161 kmi@70000 {
0162 compatible = "arm,pl050", "arm,primecell";
0163 reg = <0x070000 0x1000>;
0164 interrupts = <13>;
0165 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0166 clock-names = "KMIREFCLK", "apb_pclk";
0167 };
0168
0169 v2m_serial0: serial@90000 {
0170 compatible = "arm,pl011", "arm,primecell";
0171 reg = <0x090000 0x1000>;
0172 interrupts = <5>;
0173 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0174 clock-names = "uartclk", "apb_pclk";
0175 };
0176
0177 v2m_serial1: serial@a0000 {
0178 compatible = "arm,pl011", "arm,primecell";
0179 reg = <0x0a0000 0x1000>;
0180 interrupts = <6>;
0181 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0182 clock-names = "uartclk", "apb_pclk";
0183 };
0184
0185 v2m_serial2: serial@b0000 {
0186 compatible = "arm,pl011", "arm,primecell";
0187 reg = <0x0b0000 0x1000>;
0188 interrupts = <7>;
0189 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0190 clock-names = "uartclk", "apb_pclk";
0191 };
0192
0193 v2m_serial3: serial@c0000 {
0194 compatible = "arm,pl011", "arm,primecell";
0195 reg = <0x0c0000 0x1000>;
0196 interrupts = <8>;
0197 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0198 clock-names = "uartclk", "apb_pclk";
0199 };
0200
0201 watchdog@f0000 {
0202 compatible = "arm,sp805", "arm,primecell";
0203 reg = <0x0f0000 0x1000>;
0204 interrupts = <0>;
0205 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
0206 clock-names = "wdog_clk", "apb_pclk";
0207 };
0208
0209 v2m_timer01: timer@110000 {
0210 compatible = "arm,sp804", "arm,primecell";
0211 reg = <0x110000 0x1000>;
0212 interrupts = <2>;
0213 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
0214 clock-names = "timclken1", "timclken2", "apb_pclk";
0215 };
0216
0217 v2m_timer23: timer@120000 {
0218 compatible = "arm,sp804", "arm,primecell";
0219 reg = <0x120000 0x1000>;
0220 interrupts = <3>;
0221 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
0222 clock-names = "timclken1", "timclken2", "apb_pclk";
0223 };
0224
0225 virtio@130000 {
0226 compatible = "virtio,mmio";
0227 reg = <0x130000 0x200>;
0228 interrupts = <42>;
0229 };
0230
0231 rtc@170000 {
0232 compatible = "arm,pl031", "arm,primecell";
0233 reg = <0x170000 0x1000>;
0234 interrupts = <4>;
0235 clocks = <&v2m_clk24mhz>;
0236 clock-names = "apb_pclk";
0237 };
0238
0239 clcd@1f0000 {
0240 compatible = "arm,pl111", "arm,primecell";
0241 reg = <0x1f0000 0x1000>;
0242 interrupt-names = "combined";
0243 interrupts = <14>;
0244 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
0245 clock-names = "clcdclk", "apb_pclk";
0246 memory-region = <&vram>;
0247
0248 port {
0249 clcd_pads: endpoint {
0250 remote-endpoint = <&panel_in>;
0251 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0252 };
0253 };
0254 };
0255 };
0256 };
0257 };
0258 };
